Data detection method and device, electronic equipment and storage medium

Abstract

The invention discloses a data detection method and device, electronic equipment and a storage medium, and relates to the technical field of communication, the method is executed by a serial peripheral interface slave, and the method comprises the following steps: in response to an obtained first chip selection signal, judging whether the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude; wherein the first chip selection signal is a rising edge pulse signal; if the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude, judging whether the high level duration of the first chip selection signal is greater than or equal to the standard high level duration; and if the high level duration of the first chip selection signal is greater than or equal to the standard high level duration, determining that the first chip selection signal is an end data frame sent by the serial peripheral interface host. According to the technical scheme provided by the embodiment of the invention, the detection and acquisition of the end data frame sent by the SPI host by the SPI slave are realized, the data transmission speed between the SPI host and the SPI slave is improved, and the detection efficiency of the end data frame is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data detection method, device, electronic equipment and storage medium. Background Art

[0002] With the continuous development of communication technology, the Serial Peripheral Interface (SPI) communication protocol, as a full-duplex communication method, is being adopted by more and more electronic devices.

[0003] For the SPI slave, since it cannot perceive the data length sent by the SPI master, the SPI slave can only receive the frame header and length data according to the pre-set instruction format, and continue to receive the remaining length of data after parsing, or add a new handshake signal line between the SPI master and the SPI slave, so that the SPI slave can meet the data transmission requirements with the help of the newly added handshake signal line.

[0004] However, this data transmission method greatly reduces the data receiving speed of the SPI slave and cannot meet the high-speed data transmission requirements. The communication method of adding a handshake signal line not only increases the hardware cost of the device, but also increases the communication complexity of the SPI device. Summary of the invention

[0005] The present invention provides a data detection method, device, electronic equipment and storage medium to solve the problem of low data transmission efficiency between a SPI host and a SPI slave.

[0006] According to one aspect of the present invention, there is provided a data detection method, which is performed by a serial peripheral interface slave, wherein the serial peripheral interface slave is communicatively connected to a serial peripheral interface host, and comprises:

[0007] In response to obtaining a first chip select signal, determining whether the level amplitude of the first chip select signal is greater than or equal to a minimum high level amplitude; wherein the first chip select signal is a rising edge pulse signal;

[0008] If the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude, determining whether the high level duration of the first chip select signal is greater than or equal to the standard high level duration;

[0009] If the high level duration of the first chip select signal is greater than or equal to the standard high level duration, it is determined that the first chip select signal is an end data frame sent by the serial peripheral interface host.

[0010] If the level amplitude of the first chip select signal is smaller than the minimum high level amplitude, or the high level duration of the first chip select signal is smaller than the standard high level duration, it is determined that the first chip select signal is a glitch signal.

[0011] Configure the filtering parameters of the serial peripheral interface slave; wherein the filtering parameters include at least one of a filtering enable state, the minimum high level amplitude, and the standard high level duration.

[0012] In response to obtaining a second chip select signal, determine whether the second chip select signal is a starting data frame sent by the serial peripheral interface host; wherein the second chip select signal is a falling edge pulse signal; if the second chip select signal is a starting data frame sent by the serial peripheral interface host, configure the filtering enable state of the serial peripheral interface slave to be enabled; if the second chip select signal is not a starting data frame sent by the serial peripheral interface host, configure the filtering enable state of the serial peripheral interface slave to be disabled.

[0013] The standard high level duration is configured according to the average pull-down duration of multiple falling edge pulse signals within a preset time.

[0014] If it is determined that the first chip selection signal is a glitch signal, the glitch state bit is set, and the glitch count bit is accumulated.

[0015] According to one aspect of the present invention, there is provided a data detection device, which is executed by a serial peripheral interface slave, and the serial peripheral interface slave is communicatively connected with a serial peripheral interface host, comprising:

[0016] A level amplitude judgment module, used for judging whether the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude in response to obtaining the first chip selection signal; wherein the first chip selection signal is a rising edge pulse signal;

[0017] A level duration judgment module, used for judging whether the high level duration of the first chip select signal is greater than or equal to the standard high level duration if the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude;

[0018] The data detection execution module is used to determine that the first chip select signal is an end data frame sent by the serial peripheral interface host if the high level duration of the first chip select signal is greater than or equal to the standard high level duration.

[0019] According to another aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data detection method described in any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data detection method described in any embodiment of the present invention when executed.

[0021] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the data detection method according to any embodiment of the present invention is implemented.

[0022] The technical solution of the embodiment of the present invention, after acquiring the rising edge pulse signal, compares the level amplitude of the rising edge pulse signal with the minimum high level amplitude, and compares the high level duration of the rising edge pulse signal with the standard high level duration, so as to obtain the end data frame sent by the SPI master. Without increasing the hardware cost of the SPI slave and without changing the communication logic between the SPI master and the SPI slave, the SPI slave can detect and obtain the end data frame sent by the SPI master, thereby improving the data transmission speed between the SPI master and the SPI slave and improving the detection efficiency of the end data frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a flow chart of a data detection method provided according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the structure of an original chip select signal, a digital chip select signal and a reference clock signal provided according to an embodiment of the present invention;

[0026] Figure 3 is a flow chart of a SPI slave performing data detection according to an embodiment of the present invention;

[0027] Figure 4is a flow chart of another data detection method provided according to an embodiment of the present invention;

[0028] Figure 5 is a flow chart of the SPI slave configuration enabling state provided according to an embodiment of the present invention;

[0029] Figure 6 is a structural schematic diagram of a digital filter provided according to an embodiment of the present invention;

[0030] Figure 7 A data flow diagram between a SPI host and a SPI slave provided according to an embodiment of the present invention;

[0031] Figure 8 is a structural schematic diagram of a data detection device provided according to an embodiment of the present invention;

[0032] Fig. 9 It is a structural schematic diagram of an electronic device for implementing the data detection method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] Figure 1A flowchart of a data detection method provided by an embodiment of the present invention, this embodiment can be applied to the case where an SPI slave detects and obtains the end data frame sent by an SPI host, the method can be executed by a data detection device in an embodiment of the present invention, the data detection device can be implemented in the form of hardware and / or software, the data detection device can be configured in a chip, for example, configured in a TPM (Trusted Platform Module) chip or a SE (Secure Element) chip, the chip can be configured in an electronic device, and used as an SPI slave under the SPI communication protocol. Figure 1 As shown, the method includes:

[0036] S101. In response to obtaining a first chip select signal, determine whether a level amplitude of the first chip select signal is greater than or equal to a minimum high level amplitude; wherein the first chip select signal is a rising edge pulse signal.

[0037] The SPI bus protocol consists of a host (i.e., master device) and multiple slaves (i.e., slave devices). Each SPI slave has a separate chip select signal. When the SPI host sends data to a SPI slave, it will first pull down the chip select signal (ChipSelect) level so that the corresponding SPI slave is selected under the low-level chip select signal. At this time, the SPI host starts to send data to the SPI slave, and the SPI slave can be regarded as obtaining the start data frame (i.e., the first frame of the transmitted data). When the SPI host completes the data transmission, it pulls up the chip select signal to end the data transmission to the current SPI slave, and the SPI slave can be regarded as obtaining the end data frame (i.e., the last frame of the transmitted data).

[0038] In different SPI communication scenarios, the level amplitude of the high-level transmission signal between the SPI master and the SPI slave is often different. For example, 1.8V may be used as the high level of the transmission signal, or 3.5V may be used as the high level of the transmission signal; the minimum high-level amplitude is a critical value that can be regarded as a high level and is pre-set according to the chip communication requirements. That is, a pulse signal with a level value greater than or equal to the minimum high-level amplitude is a high-level pulse signal, and a pulse signal with a level value less than the minimum high-level amplitude is not a high-level pulse signal.

[0039] After obtaining the first chip select signal with a rising edge signal state, the level amplitude of the first chip select signal is compared with the minimum high level amplitude; if the level amplitude of the first chip select signal is less than the minimum high level amplitude, it indicates that the first chip select signal is not sent by the SPI host, and the first chip select signal will not be used as the end data frame sent by the SPI host.

[0040] In particular, since the first chip select signal is a rising edge pulse signal, once a value greater than or equal to the minimum high level amplitude is detected, it can be determined that the maximum value that can be reached subsequently must be greater than or equal to the minimum high level amplitude. At this time, it can be directly determined that the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude, thereby reducing the level amplitude comparison time of the first chip select signal and improving the detection efficiency of the rising edge pulse signal.

[0041] S102: If the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude, determine whether the high level duration of the first chip select signal is greater than or equal to a standard high level duration.

[0042] When the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude, the first chip select signal may be a real chip select signal issued by the SPI host, or it may be a glitch signal with a large glitch amplitude. Therefore, it is necessary to further determine whether the first chip select signal is a real chip select signal issued by the SPI host based on the high level duration of the first chip select signal.

[0043] In different SPI communication scenarios, the duration of the high-level pulse signal between the SPI master and the SPI slave may be different; the standard high-level duration is the standard duration of the high-level pulse signal pre-set according to the chip communication requirements, that is, the pulse signal with a high-level duration greater than or equal to the standard high-level duration is considered to be a real chip select signal sent by the SPI master, and the pulse signal with a high-level duration less than the standard high-level duration is considered to be a glitch signal; among them, the standard high-level duration is configured as an integer multiple of the reference clock signal, that is, the standard high-level duration is equal to n*T sysclk ; T sysclk Represents the reference clock signal, where n is an integer.

[0044] S103: If the high level duration of the first chip select signal is greater than or equal to the standard high level duration, determine that the first chip select signal is an end data frame sent by the serial peripheral interface host.

[0045] like Figure 2 As shown, the first chip select signal (i.e., the original chip select signal) refers to the input signal on the chip pin, and the digital chip select signal refers to the logic chip select signal after the original chip select signal passes through the gate circuit of the current chip; if the original chip select signal is a glitch signal with a large glitch amplitude, that is, the level amplitude exceeds the minimum level amplitude of the logic input high level of the SPI slave (wherein, Figure 2 The "V" in the figure represents the minimum level amplitude). The gate circuit of the chip will process the level amplitude as a high-level pulse signal at the time point when the level amplitude is greater than or equal to the minimum level amplitude. Figure 2The time between the two "V"s is processed as a high-level pulse signal, so the glitch signal is converted into a short-duration high-level signal after being processed by the chip's gate circuit (where, Figure 2 The "t" in the figure represents the high level duration). Therefore, the high level duration of the first chip select signal, i.e. Figure 2 The duration between the two "V"s is actually equivalent to the high level duration of the digital chip select signal after deformation, that is, Figure 2 In addition, the duration of the high-level signal converted from the glitch signal is obviously shorter than the duration of the glitch signal itself.

[0046] According to the above characteristics of the glitch signal, if the high level duration of the first chip select signal is greater than or equal to the standard high level duration, that is, t≥n*T sysclk It indicates that the first chip select signal is not a glitch signal, but an end data frame sent by the SPI host; if the high level duration of the first chip select signal is less than the standard high level duration, that is, t<n*T sysclk , indicating that the first chip select signal is a glitch signal, thereby realizing timely detection of glitch signals, especially large-amplitude glitch signals, ensuring the acquisition of accurate end data frames, improving the detection efficiency and detection accuracy of end data frames, and improving the data transmission efficiency between the SPI master and the SPI slave.

[0047] Compared with the prior art, in which the SPI slave can only receive the frame header and length data first according to a pre-set instruction format, and continue to receive data of the remaining length after parsing, the SPI slave in the embodiment of the present invention can directly complete the acquisition of the end data frame according to the rising edge pulse signal, thereby improving the data transmission speed between the SPI host and the SPI slave; and compared with adding a new handshake signal line between the SPI host and the SPI slave, the technical solution of the embodiment of the present invention does not increase the hardware cost of the SPI slave, and does not change the communication logic between the SPI host and the SPI slave, thereby reducing the management complexity of the SPI slave; in addition, compared with adding a filtering mechanism of the chip select signal in an application circuit outside the chip, the technical solution of the example of the present invention configures the filtering mechanism inside the chip, which not only does not increase the hardware cost of the application circuit, but also avoids the chip adaptation difference due to board-level environmental differences, thereby affecting the detection efficiency and detection accuracy of the upper edge pulse signal.

[0048] Optionally, in an embodiment of the present invention, it also includes configuring the filtering parameters of the serial peripheral interface slave; wherein the filtering parameters include at least one of the filtering enable state, the minimum high level amplitude and the standard high level duration.

[0049] Specifically, whether the SPI slave executes the above-mentioned filtering detection mechanism for the rising edge pulse signal can be managed by configuring the filter enable status of the chip through parameters, thereby ensuring the timely detection of the rising edge pulse signal by the chip, reducing the data processing pressure of the chip, and reducing the occupation of data processing resources; the minimum high-level amplitude and standard high-level duration can also be managed by configuring parameters to enable the chip to adapt to different circuit environments and ensure the communication adaptation between the SPI slave and the SPI host in different circuit environments.

[0050] Optionally, in an embodiment of the present invention, if it is determined that the first chip select signal is a glitch signal, the glitch status bit is set, and the glitch count bit is numerically accumulated. Specifically, the glitch status bit and the glitch count bit can be managed respectively by setting a glitch status register and a glitch count register in the SPI slave; wherein the glitch status bit indicates whether there is a glitch signal in the current transmission data (i.e., all data frames from a start data frame to an end data frame), or whether there is a glitch signal in the transmission data within a specified time period, if so, the glitch status bit is set to 1, otherwise it is set to 0; the glitch count bit indicates the number of glitch signals in the current transmission data, or the number of glitch signals in the transmission data within a specified time period, and each time a glitch signal is obtained, the value of the glitch count bit is added by one; the glitch status bit and the glitch count bit truly reflect the data transmission quality between the SPI host and the SPI slave, and ensure the traceability and management of the data transmission quality between the SPI host and the SPI slave.

[0051] Figure 3 This is the flow chart of the SPI slave performing data detection, including the following steps:

[0052] S201, obtain a first chip select signal; execute S202.

[0053] S202, determine whether the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude; if so, execute S203; if not, execute S206.

[0054] S203, determine whether the high level duration of the first chip select signal is greater than or equal to the standard high level duration; if so, execute S204; if not, execute S205.

[0055] S204: Determine that the first chip select signal is an end data frame sent by the serial peripheral interface host.

[0056] S205: Determine whether the first chip select signal is a glitch signal.

[0057] S206: Determine that the first chip select signal is not an end data frame sent by the serial peripheral interface host.

[0058] The technical solution of the embodiment of the present invention, after acquiring the rising edge pulse signal, compares the level amplitude of the rising edge pulse signal with the minimum high level amplitude, and compares the high level duration of the rising edge pulse signal with the standard high level duration, so as to obtain the end data frame sent by the SPI master. Without increasing the hardware cost of the SPI slave and without changing the communication logic between the SPI master and the SPI slave, the SPI slave can detect and obtain the end data frame sent by the SPI master, thereby improving the data transmission speed between the SPI master and the SPI slave and improving the detection efficiency of the end data frame.

[0059] Figure 4 The present invention provides a flowchart of a data detection method. The relationship between the present embodiment and the above embodiment is that after determining that the start data frame sent by the SPI host is detected, the filter detection function of the SPI slave is enabled. Figure 4 As shown, the method includes:

[0060] S301. In response to obtaining a second chip select signal, determine whether the second chip select signal is a start data frame sent by the serial peripheral interface host; wherein the second chip select signal is a falling edge pulse signal.

[0061] As described in the above technical solution, when the SPI master sends transmission data to an SPI slave, it will first pull down the level of the chip select signal (Chip Select). Therefore, after the SPI slave obtains the second chip select signal with a falling edge signal state, it compares the level amplitude of the second chip select signal with the maximum low level amplitude; wherein the maximum low level amplitude is a critical value that can be regarded as a low level and is pre-set according to the chip communication requirements, that is, a pulse signal with a level value less than or equal to the maximum low level amplitude is a low level pulse signal, and a pulse signal with a level value greater than the maximum low level amplitude is not a low level pulse signal; therefore, if the level amplitude of the second chip select signal is less than or equal to the maximum low level amplitude, it indicates that the first chip select signal is the start data frame sent by the SPI master; if the level amplitude of the second chip select signal is greater than the maximum low level amplitude, it indicates that the first chip select signal is not the start data frame sent by the SPI master.

[0062] S302: If the second chip select signal is a start data frame sent by the serial peripheral interface host, configure the filter enable state of the serial peripheral interface slave to enable.

[0063] The purpose of enabling the above-mentioned filtering detection function of the SPI slave is to detect the rising edge pulse signal and timely detect and obtain the end data frame sent by the SPI host. The premise for the SPI host to send the end data frame is to send the start data frame first, and then the end data frame will be sent. Therefore, for the management of the filtering enable state of the SPI slave, it can be configured in advance through the detection result of the start data frame, that is, if the second chip select signal is the start data frame sent by the SPI host, the filtering enable state of the SPI slave is configured to enable, so as to enable the filtering detection of the SPI for the rising edge pulse signal.

[0064] S303: If the second chip select signal is not a start data frame sent by the serial peripheral interface host, configure the filter enable state of the serial peripheral interface slave to be disabled.

[0065] If the second chip select signal is not the start data frame sent by the SPI master, the filter enable state of the SPI slave is configured to be disabled to turn off the filter detection of the SPI slave for the rising edge pulse signal; thereby ensuring that the filter detection function of the SPI slave for the end data frame is turned on in time, and avoiding the waste of filter detection resources when there is no transmission data.

[0066] Optionally, in an embodiment of the present invention, it also includes: configuring the standard high level duration according to the average pull-down duration of multiple falling edge pulse signals within a preset time. Specifically, since the pull-down duration of the falling edge pulse signal reflects the data transmission characteristics of the SPI host, it has a strong correlation with the pull-up duration of the rising edge pulse signal. Therefore, according to the average pull-down duration of each falling edge pulse signal in the past period of time, the corresponding average pull-up duration can be calculated and obtained, and it is configured as the standard high level duration, thereby ensuring that the configured standard high level duration meets the transmission requirements in the current SPI communication environment, avoiding the phenomenon of misdetecting the burr signal as the end data frame when the standard high level duration value is too small, and avoiding the misdetection of the end data frame sent by the SPI host as a burr signal when the standard high level duration value is too large, further improving the accuracy of the rising edge pulse signal detection result.

[0067] Figure 5 This is a flowchart of the SPI slave configuration enable state, including the following steps:

[0068] S401, obtain a second chip select signal; execute S402.

[0069] S402, determine whether the second chip select signal is a start data frame sent by the serial peripheral interface host; if so, execute S403; if not, execute S404.

[0070] S403: Configure the filter enable state of the serial peripheral interface slave to be enabled.

[0071] S404: Configure the filter enable state of the serial peripheral interface slave to be disabled.

[0072] The technical solution of the embodiment of the present invention, in response to obtaining a falling edge pulse signal, determines whether the second chip select signal is a start data frame sent by a serial peripheral interface host; if the second chip select signal is a start data frame sent by the serial peripheral interface host, the filter enable state of the serial peripheral interface slave is configured to be enabled, otherwise it is configured to be disabled, thereby ensuring that the filter detection function of the SPI slave for the end data frame sent by the SPI host is timely turned on, and avoiding the waste of filter detection resources when there is no transmission data.

[0073] Figure 6 A structural schematic diagram of a digital filter provided in an embodiment of the present invention, wherein the digital filter is configured in a chip, and when the chip is used as an SPI slave, the data detection method described in any of the above embodiments is executed. The digital filter comprises: a rising edge detection unit 401, a high level counting unit 402, a filtering time register 403, a filtering enable register 404, a glitch status register 405 and a glitch counting register 406.

[0074] Among them, the rising edge detection unit 401 is used to detect the rising edge pulse signal; the high level counting unit 402 is used to obtain the high level duration of the rising edge pulse signal; the filter duration register 403 is used to configure the standard high level duration; the filter enable register 404 is used to configure the filter enable state of the digital filter; the burr status register 405 is used to manage the burr status bit; the burr count register 406 is used to manage the burr count bit.

[0075] Specifically, the data filter turns on the filter detection function through the filter enable register 404; when the rising edge detection unit 401 detects the rising edge pulse signal, it determines whether the level amplitude of the rising edge pulse signal is greater than or equal to the minimum high level amplitude; if the rising edge detection unit 401 determines that the level amplitude of the rising edge pulse signal is greater than or equal to the minimum high level amplitude, the high level duration of the rising edge pulse signal is recorded through the high level counting unit 402.

[0076] If the high-level counting unit 402 determines that the high-level duration of the rising edge pulse signal is less than the standard high-level duration configured in the filter duration register 403, it determines that the rising edge pulse signal is a glitch signal; at this time, the glitch status register 405 sets the glitch status bit, and the glitch count register 406 accumulates the glitch count bit.

[0077] The technical solution of the embodiment of the present invention obtains the end data frame sent by the SPI master through a digital filter configured in the SPI slave, thereby realizing the detection and acquisition of the end data frame sent by the SPI master by the SPI slave, improving the data transmission speed between the SPI master and the SPI slave, and improving the detection efficiency of the end data frame.

[0078] Figure 7 The data flow diagram between the SPI master and the SPI slave provided by the embodiment of the present invention is as follows: Figure 7 As shown:

[0079] The SPI slave configures a receiving space in a direct memory access (DMA) mode; since the length of the transmission data sent by the SPI host is unknown, the SPI slave pre-configures a larger receiving space; the SPI slave enables the filtering function of the rising edge pulse signal; the SPI host sends transmission data to the SPI slave; wherein the length of the transmission data is not fixed; the SPI slave receives the transmission data sent by the SPI host; after the SPI host sends the end data frame, it pulls up the pulse signal, that is, sends a rising edge pulse signal; after the SPI slave detects the rising edge pulse signal, it determines that the end data frame has been obtained, that is, it determines that the data transmission has been completed, thereby triggering a transmission data interrupt to end this data transmission, and finally performs parsing processing on subsequent data frames.

[0080] According to the technical solution of the embodiment of the present invention, the SPI slave realizes the detection and acquisition of the end data frame sent by the SPI master, thereby improving the data transmission speed between the SPI master and the SPI slave and enhancing the detection efficiency of the end data frame.

[0081] Figure 8 6 is a structural block diagram of a data detection device provided by an embodiment of the present invention. The data detection device 600 specifically includes:

[0082] A level amplitude judgment module 601 is used to judge whether the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude in response to obtaining the first chip selection signal; wherein the first chip selection signal is a rising edge pulse signal;

[0083] A level duration judgment module 602 is used to judge whether the high level duration of the first chip select signal is greater than or equal to a standard high level duration if the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude;

[0084] The data detection execution module 603 is used to determine that the first chip select signal is an end data frame sent by the serial peripheral interface host if the high level duration of the first chip select signal is greater than or equal to the standard high level duration.

[0085] The technical solution of the embodiment of the present invention, after acquiring the rising edge pulse signal, compares the level amplitude of the rising edge pulse signal with the minimum high level amplitude, and compares the high level duration of the rising edge pulse signal with the standard high level duration, so as to obtain the end data frame sent by the SPI master. Without increasing the hardware cost of the SPI slave and without changing the communication logic between the SPI master and the SPI slave, the SPI slave can detect and obtain the end data frame sent by the SPI master, thereby improving the data transmission speed between the SPI master and the SPI slave and improving the detection efficiency of the end data frame.

[0086] Optionally, the data detection execution module 603 is also used to determine that the first chip select signal is a glitch signal if the level amplitude of the first chip select signal is less than the minimum high level amplitude, or the high level duration of the first chip select signal is less than the standard high level duration.

[0087] Optionally, the data detection device 600 is also used to configure the filtering parameters of the serial peripheral interface slave; wherein the filtering parameters include at least one of the filtering enable state, the minimum high level amplitude and the standard high level duration.

[0088] Optionally, the data detection device 600 is also used to determine whether the second chip select signal is a starting data frame sent by the serial peripheral interface host in response to obtaining a second chip select signal; wherein the second chip select signal is a falling edge pulse signal; if the second chip select signal is a starting data frame sent by the serial peripheral interface host, the filtering enable state of the serial peripheral interface slave is configured to be enabled; if the second chip select signal is not a starting data frame sent by the serial peripheral interface host, the filtering enable state of the serial peripheral interface slave is configured to be disabled.

[0089] Optionally, the data detection device 600 is further used to configure the standard high level duration according to the average pull-down duration of multiple falling edge pulse signals within a preset time.

[0090] Optionally, the data detection device 600 is further configured to set a glitch state bit and accumulate a glitch count bit if it is determined that the first chip selection signal is a glitch signal.

[0091] The data detection device provided by the present invention can execute the data detection method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the data detection method provided by any embodiment of the present invention.

[0092] Fig. 9A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0093] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0094] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0095] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a data detection method.

[0096] In some embodiments, the data detection method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the data detection method described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the data detection method by any other appropriate means (e.g., by means of firmware).

[0097] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The computer program for implementing the method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data detection device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0099] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0100] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0101] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0102] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0103] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0104] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data detection method, characterized in that: The method is executed by a serial peripheral interface slave, which is communicatively connected with a serial peripheral interface host, and includes: In response to obtaining a first chip select signal, determining whether the level amplitude of the first chip select signal is greater than or equal to a minimum high level amplitude; wherein the first chip select signal is a rising edge pulse signal; If the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude, determining whether the high level duration of the first chip select signal is greater than or equal to the standard high level duration; If the high level duration of the first chip select signal is greater than or equal to the standard high level duration, it is determined that the first chip select signal is an end data frame sent by the serial peripheral interface host.

2. The method according to claim 1, characterized in that: Also includes: If the level amplitude of the first chip select signal is smaller than the minimum high level amplitude, or the high level duration of the first chip select signal is smaller than the standard high level duration, it is determined that the first chip select signal is a glitch signal.

3. The method according to claim 1, characterized in that Also includes: Configure the filtering parameters of the serial peripheral interface slave; wherein the filtering parameters include at least one of a filtering enable state, the minimum high level amplitude, and the standard high level duration.

4. The method according to claim 3, characterized in that Also includes: In response to obtaining a second chip select signal, determining whether the second chip select signal is a start data frame sent by the serial peripheral interface host; wherein the second chip select signal is a falling edge pulse signal; If the second chip select signal is a start data frame sent by the serial peripheral interface host, configuring the filter enable state of the serial peripheral interface slave to be enabled; If the second chip select signal is not a start data frame sent by the serial peripheral interface host, the filter enable state of the serial peripheral interface slave is configured to be disabled.

5. The method according to claim 3, characterized in that: Also includes: The standard high level duration is configured according to the average pull-down duration of multiple falling edge pulse signals within a preset time.

6. The method according to claim 2, characterized in that Also includes: If it is determined that the first chip selection signal is a glitch signal, the glitch state bit is set, and the glitch count bit is accumulated.

7. A data detection device, characterized in that: The method is executed by a serial peripheral interface slave, which is communicatively connected with a serial peripheral interface host, and includes: A level amplitude judgment module, used for judging whether the level amplitude of the first chip selection signal is greater than or equal to the minimum high level amplitude in response to obtaining the first chip selection signal; wherein the first chip selection signal is a rising edge pulse signal; A level duration judgment module, used for judging whether the high level duration of the first chip select signal is greater than or equal to the standard high level duration if the level amplitude of the first chip select signal is greater than or equal to the minimum high level amplitude; The data detection execution module is used to determine that the first chip select signal is an end data frame sent by the serial peripheral interface host if the high level duration of the first chip select signal is greater than or equal to the standard high level duration.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the data detection method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data detection method according to any one of claims 1 to 6 when executed.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the data detection method according to claims 1-6.

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