UVM verification platform and verification test execution method

Abstract

The invention discloses a UVM verification platform and a verification test execution method, and relates to the technical field of integrated circuits, the verification platform comprises a file management module used for sending a test case file to a script processing module; the script processing module is used for acquiring a test case name and a hardware parameter according to the test case file, and sending the test case name and the hardware parameter to the command generation module; the command generation module is used for generating a target simulation command according to the test case name and the hardware parameters and sending the target simulation command to the compiling library; and the compiling library is used for verifying and testing the design unit according to the basic use case information and the target simulation command. According to the technical scheme, on the premise that the number of the test cases is not changed, the scale of the compiling library of the UVM verification platform is reduced, the compiling time consumption and the dynamic simulation time consumption of the compiling library are reduced, and the verification test execution efficiency of the UVM verification platform is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a UVM verification platform and a verification test execution method. Background Art

[0002] With the continuous development of chip technology, SOC (System on Chip) chips integrate more and more modules and their functions become more and more complex. In order to ensure the correctness of their various functions, verification testing has become particularly important.

[0003] In the prior art, verification testing of design under test (DUT) on SOC chips is usually performed through a UVM (Universal Verification Methodology) verification platform, which generates stimulus signals by compiling test cases through a compilation library, and then performs verification testing on the design units based on the stimulus signals.

[0004] However, with the increasing number of test cases, the size of the compilation library of the traditional UVM verification platform is also increasing, which not only increases the compilation time of the compilation library, but also increases the running time of the test cases, greatly affecting the verification test efficiency. At the same time, the chip resources occupied by the test cases are also increasing when they are running. Summary of the invention

[0005] The invention provides a UVM verification platform and a verification test execution method, so as to solve the problem that the verification of a traditional UVM verification platform takes too long.

[0006] According to one aspect of the present invention, a UVM verification platform is provided, comprising: a command generation component and a compilation library; the command generation component comprises a file management module, a script processing module and a command generation module;

[0007] The file management module is used to store at least one test case file and send the test case file to the script processing module;

[0008] The script processing module is used to obtain the test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to the command generation module; wherein the hardware parameters include stimulus configuration parameters and compilation library operation parameters;

[0009] The command generation module is used to generate a target simulation command according to the test case name and the hardware parameters, and send the target simulation command to the compilation library;

[0010] The compilation library is in communication connection with the command generation module, and is used to perform verification test on the design unit according to the basic use case information and the target simulation command.

[0011] The script processing module is also used to obtain a use case execution program according to the test case file and send the use case execution program to the command generation module; the command generation module is also used to generate a target simulation command according to the test case name, the hardware parameters and the use case execution program.

[0012] The script processing module is also used to obtain the target storage address of the use case execution program according to the test case file, and send the target storage address to the command generation module; the command generation module is also used to obtain the target storage file according to the target storage address, and obtain the use case execution program according to the target storage file.

[0013] The compilation library includes: a use case management module, a driver execution module, a first monitoring module, a reference model module, a second monitoring module and a performance evaluation module; the use case management module is used to obtain the stimulus configuration parameters and the compilation library operation parameters according to the target simulation command issued by the command generation module, and generate a stimulus signal according to the stimulus configuration parameters and basic use case information; wherein the compilation library operation parameters include a driving mode; the driver execution module is used to send the stimulus signal to the design unit according to the driving mode; the first monitoring module is used to obtain the input end information of the design unit and send the input end information to the reference model module; the reference model module is used to obtain the expected output information according to the input end information and send the expected output information to the performance evaluation module; the second monitoring module is used to obtain the output end information of the design unit and send the output end information to the performance evaluation module; the performance evaluation module is used to obtain the verification test result of the design unit according to the output end information and the expected output information.

[0014] The basic use case information includes a plurality of variable interfaces; the use case management module is further used to generate an incentive signal by modifying the variable information of the basic use case information according to the incentive configuration parameters and at least one of the variable interfaces.

[0015] The command generation module is specifically used to send the target simulation command to the compilation library through the target processor class; wherein the target processor class includes uvm_cmdline_processor.

[0016] According to another aspect of the present invention, a verification test execution method is provided, which is applied to the UVM verification platform described in any embodiment of the present invention, comprising:

[0017] The file management module sends the stored test case files to the script processing module;

[0018] The script processing module obtains the test case name and hardware parameters according to the test case file, and sends the test case name and the hardware parameters to the command generation module;

[0019] The command generation module generates a target simulation command according to the test case name and the hardware parameters, and sends the target simulation command to the compilation library;

[0020] The compilation library performs verification testing on the design unit according to the basic use case information and the target simulation command.

[0021] According to another aspect of the present invention, a verification test execution device is provided, which is applied to the UVM verification platform described in any embodiment of the present invention, including:

[0022] A file sending execution module, configured in the file management module, for sending the stored test case files to the script processing module;

[0023] A parameter sending execution module, configured in the script processing module, is used to obtain a test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to a command generation module;

[0024] A command sending execution module, configured in the command generating module, for generating a target simulation command according to the test case name and the hardware parameters, and sending the target simulation command to a compiling library;

[0025] The verification test execution module is configured in the compilation library and is used to perform verification tests on the design unit according to the basic use case information and the target simulation command.

[0026] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the verification test execution method described in any embodiment of the present invention when executed.

[0027] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the verification test execution method according to any embodiment of the present invention is implemented.

[0028] According to the technical solution of the embodiment of the present invention, a UVM verification platform completes test case file storage and stimulus configuration parameter extraction through a command generation component, and then sends a command containing the stimulus configuration parameter to a compilation library through a simulation command generation method, and the compilation library executes the verification test of the design unit through basic case information and the stimulus configuration parameter, thereby reducing the compilation library scale of the UVM verification platform without changing the number of test cases, reducing the compilation time and dynamic simulation time of the compilation library, greatly improving the verification test efficiency of the UVM verification platform, and reducing the occupation of chip resources by the verification test.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a structural schematic diagram of a UVM verification platform provided according to Embodiment 1 of the present invention;

[0032] Figure 2 It is a structural diagram of another UVM verification platform provided according to Embodiment 2 of the present invention;

[0033] Figure 3 It is a flow chart of executing a test case in a UVM verification platform provided by Embodiment 3 of the present invention;

[0034] Figure 4 is a flowchart of a verification test execution method provided according to Embodiment 4 of the present invention;

[0035] Figure 5 It is a structural diagram of a verification test execution device provided according to Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Embodiment 1

[0039] Figure 1 A schematic diagram of the structure of a UVM verification platform provided in Embodiment 1 of the present invention is shown in FIG. Figure 1 As shown, the UVM verification platform includes a command generation component 100 and a compilation library 200; the command generation component 100 includes a file management module 110, a script processing module 120 and a command generation module 130; the file management module 110 is used to store at least one test case file, and send the test case file to the script processing module 120; the script processing module 120 is used to obtain a test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to the command generation module 130; wherein the hardware parameters include stimulus configuration parameters and compilation library operation parameters.

[0040] Specifically, the file management module 110 stores a plurality of test case files, each of which corresponds to a test case and is used to store sequence information of the test case; wherein the sequence information includes the test case name and hardware parameters; the hardware parameters include stimulus configuration parameters and compilation library operation parameters; the stimulus configuration parameters refer to function variables for generating stimulus signals, which determine which type of stimulus signal is generated; the compilation library operation parameters refer to operation parameters of each structural component inside the compilation library 200 when executing a verification test, which determine how each structural component operates when executing a verification test.

[0041] For example, when the compilation library 200 inputs different stimulus signals to the design unit 300 through the driver execution module, the compilation library operating parameters may include the driving mode of the driver execution module; wherein the driving mode refers to the way in which the driver execution module sends the stimulus signal, that is, the way in which the driver execution module sends the stimulus signal to the design unit 300; wherein the above-mentioned sending mode may include time-sharing transmission, specified protocol type transmission, and process-sharing transmission, etc.

[0042] The script processing module 120 can extract key information such as the test case name and hardware parameters from the test case file through regular expressions, and send the extracted key information to the command generation module 130; for example, the script processing module 120 can obtain the test case name and various hardware parameters in sequence through a pre-built global regular expression, so as to realize key information extraction for the sequentially generated test case file; wherein, the sequentially generated test case file means that the various information to be extracted in the test case file are arranged in sequence according to a fixed order, that is, when the test case file is constructed, the test case name and various hardware parameters are arranged in sequence according to a fixed order; the global regular expression includes extraction identifiers of all information to be extracted.

[0043] The script processing module 120 can also obtain the test case name and various hardware parameters respectively through multiple pre-constructed local regular expressions, so as to realize key information extraction for the test case files generated in disorder; wherein, the test case files generated in disorder refer to the test case files in which the various information to be extracted are not arranged in sequence according to a fixed order, that is, when the test case files are constructed, the test case names and various hardware parameters can be arranged in any order; the local regular expression only includes an extraction identifier for the information to be extracted.

[0044] The command generation module 130 is used to generate a target simulation command according to the test case name and the hardware parameters, and send the target simulation command to the compile library 200. After obtaining the test case name and the hardware parameters, the command generation module 130 generates a target simulation command that can be read by the compile library 200 according to a command format pre-agreed with the compile library 200, and the target simulation command includes the test case name and the hardware parameters.

[0045] The compile library 200 is in communication connection with the command generation module 130, and is used to perform verification test on the design unit 300 according to the basic use case information and the target simulation command. The compile library 200 stores the pre-written basic use case information, which reflects the basic sequence information of the corresponding test case; the compile library 200 obtains the matching basic use case information according to the test case name, and then updates the basic use case information according to the stimulus configuration parameters. The updated basic use case information is a stimulus set containing multiple stimulus signals; the compile library 200 sends different stimulus signals to the design unit 300 to perform the verification test of the design unit 300.

[0046] Compared with the traditional UVM verification platform, the UVM verification platform in the embodiment of the present invention configures the command generation component 100 outside the compilation library 200, reduces the compilation volume of the verification environment, and reduces the compilation time of the UVM verification platform in the compilation stage; at the same time, in the dynamic simulation stage after the compilation of the compilation library 200 is completed, that is, in the process of verifying the design unit 300 through the stimulus signal, since the compilation library 200 does not include a test case file, it has removed a large amount of code logic used in the verification, thereby reducing the verification time of the dynamic simulation stage, and also reducing the occupation of chip resources in the dynamic simulation stage.

[0047] Optionally, in an embodiment of the present invention, the script processing module 120 is also used to obtain a use case execution program based on the test case file, and send the use case execution program to the command generation module 130; the command generation module 130 is also used to generate a target simulation command based on the test case name, the hardware parameters and the use case execution program.

[0048] Specifically, the use case execution program refers to the software code that needs to be run inside the design unit 300 when performing verification testing under the current test case. The software code provides a software basis for the execution of the test case. Different test cases often have corresponding use case execution programs. Before triggering various stimulus signals under the current test case, the corresponding use case execution program needs to be deployed to the design unit 300 in advance so that the design unit 300 can perform verification testing based on the current use case execution program.

[0049] In an embodiment of the present invention, the use case execution program is stored in a test case file, so that the script processing module 120 can simultaneously extract the use case execution program while extracting the test case name and hardware parameters, and send the use case execution program to the command generation module 130; the command generation module 130 jointly generates a target simulation command according to the test case name, hardware parameters and the use case execution program; after obtaining the target simulation command, the compilation library 200 first deploys the use case execution program to the design unit 300, and then sends an excitation signal according to the test case name and hardware parameters as described in the above technical solution.

[0050] Compared with configuring the use case execution program in the compilation library 200, the technical solution of the embodiment of the present invention further reduces the amount of code in the compilation library 200 itself, reduces the compilation volume of the verification environment, and shortens the time consumption of the compilation stage and the dynamic simulation stage; at the same time, the command generation component includes the test case name, hardware parameters and the use case execution program, which actually includes all the elements of the SOC chip system-level verification and has high reusability.

[0051] Optionally, in an embodiment of the present invention, the script processing module 120 is also used to obtain the target storage address of the use case execution program according to the test case file, and send the target storage address to the command generation module 130; the command generation module 130 is also used to obtain the target storage file according to the target storage address, and obtain the use case execution program according to the target storage file.

[0052] Specifically, the use case execution program can also be pre-stored as a specified type of file, for example, a ".hex" type file, and the storage address of the storage file (i.e., the target storage address) is recorded in the test case file; the script processing module 120, after extracting the target storage address from the test case file, sends the target storage address to the command generation module 130; the command generation module 130 obtains the target storage file according to the obtained target storage address, and then obtains the use case execution program in the target storage file, thereby improving the information extraction efficiency of the script processing module 120, and the information transmission efficiency between the script processing module 120 and the command generation module 130, thereby further improving the verification test efficiency of the UVM verification platform.

[0053] According to the technical solution of the embodiment of the present invention, a UVM verification platform completes test case file storage and stimulus configuration parameter extraction through a command generation component, and then sends a command containing the stimulus configuration parameter to a compilation library through a simulation command generation method, and the compilation library executes the verification test of the design unit through basic case information and the stimulus configuration parameter, thereby reducing the compilation library scale of the UVM verification platform without changing the number of test cases, reducing the compilation time and dynamic simulation time of the compilation library, greatly improving the verification test efficiency of the UVM verification platform, and reducing the occupation of chip resources by the verification test.

[0054] Embodiment 2

[0055] Figure 2 A schematic diagram of the structure of a UVM verification platform provided by Embodiment 2 of the present invention is as follows: Figure 2 As shown, the compile library 200 includes: a use case management module 210, a driver execution module 220, a first monitoring module 230, a second monitoring module 240, a reference model module 250 and a performance evaluation module 260; the use case management module 210 is used to obtain the stimulus configuration parameters and the compile library operating parameters according to the target simulation command issued by the command generation module 300, and generate a stimulus signal according to the stimulus configuration parameters and basic use case information; wherein the compile library operating parameters include a driving mode; the driver execution module 220 is used to issue the stimulus signal to the design unit 300 according to the driving mode.

[0056] Specifically, after obtaining the target simulation command, the use case management module 210 parses and obtains the stimulus configuration parameters and the compilation library running parameters; wherein, the parsed and obtained compilation library 200 running function includes the driving mode; the basic use case information includes the basic sequence information required for the generation of the stimulus signal, and the use case management module 210 updates the basic use case information through the stimulus configuration parameters, for example, the variables in the basic use case information are modified through the stimulus configuration parameters to configure and generate different stimulus signals.

[0057] After the use case management module 210 sends the driving mode to the driving execution module 220, the driving execution module 220 sends an excitation signal to the design unit 300 according to the driving mode; wherein, the driving execution module 220 sends an excitation request to the use case management module 210 each time it needs to send an excitation signal to the design unit 300; the use case management module 210 sends the excitation signal to be sent to the driving execution module 220 according to the excitation request and in the order in which the excitation signal is generated, so as to send the excitation signal to the design unit 300 through the driving execution module 220.

[0058] The first monitoring module 230 is used to obtain the input end information of the design unit 300 and send the input end information to the reference model module 250; the reference model module 250 is used to obtain the expected output end information according to the input end information, and send the expected output end information to the performance evaluation module 260; the second monitoring module 240 is used to obtain the output end information of the design unit 300 and send the output end information to the performance evaluation module 260; the performance evaluation module 260 is used to obtain the verification test result of the design unit 300 according to the output end information and the expected output information.

[0059] Specifically, the first monitoring module 230 is connected to the input interface of the design unit 300, and is used to obtain the input end information of the design unit 300, that is, to obtain the various excitation signals sent to the design unit 300 by the driving execution module 220, and then send the obtained excitation signals to the reference model module 250; wherein, the design unit 300 itself has a hardware structure and hardware function, and the reference model is different from the design unit 300, which is a functional component created at the software verification end for simulating the hardware behavior of the design unit 300; since the reference model module 250 has the same function as the design unit 300, the output result of the reference model module 250 for the above-mentioned input end information is actually the expected output result of the design unit 300.

[0060] The second monitoring module 240 is connected to the output interface of the design unit 300, and the output information of the design unit 300 obtained is sent to the performance evaluation module 260; after obtaining the output information of the design unit 300, the performance evaluation module 260 compares the output information with the above-mentioned expected output information, so as to evaluate the verification test result of the design unit 300 according to the comparison result; thus, the compilation library 200 not only realizes the verification test of the design unit 300, but also greatly reduces the time-consuming dynamic simulation under the premise of removing a large amount of code logic used in the verification, and improves the verification test efficiency of the UVM verification platform. In addition, the use case management module 210, the driver execution module 220 and the first monitoring module 230 can also be encapsulated as an input component 270, and the second monitoring module 240 can be encapsulated as an output component 280 to save hardware resources and strengthen the management of the above modules.

[0061] Optionally, in an embodiment of the present invention, the basic use case information includes multiple variable interfaces; the use case management module 210 is also used to generate an excitation signal by modifying the variable information of the basic use case information according to the excitation configuration parameters and at least one of the variable interfaces. Multiple variable interfaces are reserved in the basic use case information, which are used as modification channels for different variables. After obtaining the target simulation command issued by the command generation component 130, the use case management module 210 calls the variable interfaces of different variables through command line parameters, thereby completing the modification configuration of the variables and generating different excitation signals, thereby improving the convenience of updating the excitation function and the efficiency of generating the excitation signal.

[0062] Optionally, in an embodiment of the present invention, the command generation module 130 is specifically used to send the target simulation command to the compilation library 200 through the target processor class; wherein the target processor class includes uvm_cmdline_processor. Specifically, when the command generation module 130 modifies the built-in variables of the basic use case information, it can be completed through the uvm_cmdline_processor class. For example, the "int" type variable can be passed into the compilation library 200 through the command line through "uvm_set_config_int", and the string type variable can be passed into the compilation library 200 through "uvm_set_config_string"; in addition, the uvm_cmdline_processor class also supports the passing of variables of enumeration type and array type;

[0063] After obtaining the command line parameters transmitted by the uvm_cmdline_processor class, the use case management module 210 can change the variables in the basic use case information through the "p_sequencer" method; compared with other processor classes (for example, the uvm_config_db class), the uvm_cmdline_processor class used in the embodiment of the present invention will not interfere with the compilation itself, thereby ensuring the accuracy of the verification test results.

[0064] According to the technical solution of the embodiment of the present invention, the compilation library sequentially completes the operations of stimulus signal generation, stimulus signal driving, output terminal information acquisition, expected output information acquisition, and verification test result evaluation through a use case management module, a driver execution module, a first monitoring module, a reference model module, a second monitoring module, and a performance evaluation module, which not only realizes the verification test of the design unit, but also greatly reduces the time consumption of dynamic simulation and improves the verification test efficiency of the UVM verification platform under the premise of removing a large amount of code logic used in the verification.

[0065] Embodiment 3

[0066] Figure 3 A flow chart of a UVM verification platform executing a test case provided by Embodiment 3 of the present invention, such as Figure 3 As shown:

[0067] The command generation component 100 starts running; after the command generation component 100 starts running, it parses the test case file; the command generation component 100 generates a target simulation command according to the parsing result of the test case file; while the command generation component 100 completes the above operation steps, the compilation library 200 starts compiling; after the compilation library 200 completes the compilation, it can receive the target simulation command issued by the command generation component 100; the compilation library 200 starts executing the test case according to the received target simulation command. In particular, during the verification process of the test case, the stimulus content can also be debugged according to the simulation result, and the test case does not need to be compiled twice by the compilation library 200, and can be immediately simulated twice, which further improves the verification efficiency.

[0068] According to the technical solution of the embodiment of the present invention, while the compilation library executes compilation, the command generation component can complete the parsing of the test case file and the generation operation of the target simulation command, thereby improving the verification test efficiency of the UVM verification platform. Since the command generation component has been removed from the compilation library, the compilation library scale of the UVM verification platform is reduced, and the compilation time of the compilation library is reduced.

[0069] Embodiment 4

[0070] Figure 4 The flowchart of a verification test execution method provided in the fourth embodiment of the present invention can be executed by a verification test execution device, which can be implemented in the form of hardware and / or software. The verification test execution device can be configured in the UVM verification platform in any embodiment of the present invention, and the UVM verification platform can be configured in a SOC chip. Figure 4 As shown, the method includes:

[0071] S401. The file management module sends the stored test case files to the script processing module.

[0072] S402: The script processing module obtains a test case name and hardware parameters according to the test case file, and sends the test case name and the hardware parameters to a command generation module.

[0073] S403: The command generation module generates a target simulation command according to the test case name and the hardware parameters, and sends the target simulation command to a compilation library.

[0074] S404: The compilation library performs verification testing on the design unit according to the basic use case information and the target simulation command.

[0075] According to the technical solution of the embodiment of the present invention, a UVM verification platform completes test case file storage and stimulus configuration parameter extraction through a command generation component, and then sends a command containing the stimulus configuration parameter to a compilation library through a simulation command generation method, and the compilation library executes the verification test of the design unit through basic case information and the stimulus configuration parameter, thereby reducing the compilation library scale of the UVM verification platform without changing the number of test cases, reducing the compilation time and dynamic simulation time of the compilation library, greatly improving the verification test efficiency of the UVM verification platform, and reducing the occupation of chip resources by the verification test.

[0076] Embodiment 5

[0077] Figure 5 : is a structural block diagram of a verification test execution device provided by Embodiment 5 of the present invention, the device specifically comprises:

[0078] A file sending execution module 501, configured in the file management module, is used to send the stored test case file to the script processing module;

[0079] A parameter sending execution module 502, configured in the script processing module, is used to obtain a test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to a command generation module;

[0080] A command sending execution module 503, configured in the command generating module, is used to generate a target simulation command according to the test case name and the hardware parameters, and send the target simulation command to a compiling library;

[0081] The verification test execution module 504 is configured in the compilation library and is used to perform verification tests on the design unit according to the basic use case information and the target simulation command.

[0082] According to the technical solution of the embodiment of the present invention, a UVM verification platform completes test case file storage and stimulus configuration parameter extraction through a command generation component, and then sends a command containing the stimulus configuration parameter to a compilation library through a simulation command generation method, and the compilation library executes the verification test of the design unit through basic case information and the stimulus configuration parameter, thereby reducing the compilation library scale of the UVM verification platform without changing the number of test cases, reducing the compilation time and dynamic simulation time of the compilation library, greatly improving the verification test efficiency of the UVM verification platform, and reducing the occupation of chip resources by the verification test.

[0083] The above device can execute the verification test execution method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the verification test execution method provided by any embodiment of the present invention.

[0084] Embodiment 6

[0085] In some embodiments, the verification test execution method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the verification test execution method described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the verification test execution method in any other appropriate manner (e.g., by means of firmware).

[0086] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0087] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0088] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0089] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0090] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0091] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0092] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0093] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A UVM verification platform, characterized in that: include: Command generation component and compilation library; the command generation component includes a file management module, a script processing module and a command generation module; The file management module is used to store at least one test case file and send the test case file to the script processing module; The script processing module is used to obtain the test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to the command generation module; wherein the hardware parameters include stimulus configuration parameters and compilation library operation parameters; The command generation module is used to generate a target simulation command according to the test case name and the hardware parameters, and send the target simulation command to the compilation library; The compilation library is in communication connection with the command generation module, and is used to perform verification test on the design unit according to the basic use case information and the target simulation command.

2. The UVM verification platform according to claim 1, wherein The script processing module is further used to obtain a test case execution program according to the test case file, and send the test case execution program to the command generation module; The command generation module is also used to generate a target simulation command according to the test case name, the hardware parameters and the test case execution program.

3. The UVM verification platform according to claim 2, characterized in that, The script processing module is further used to obtain a target storage address of a test case execution program according to the test case file, and send the target storage address to the command generation module; The command generation module is also used to obtain the target storage file according to the target storage address, and obtain the use case execution program according to the target storage file.

4. The UVM verification platform according to claim 1, wherein The compilation library includes: a use case management module, a driver execution module, a first monitoring module, a reference model module, a second monitoring module and a performance evaluation module; The use case management module is used to obtain the stimulus configuration parameters and the compile library operation parameters according to the target simulation command issued by the command generation module, and generate a stimulus signal according to the stimulus configuration parameters and basic use case information; wherein the compile library operation parameters include a driving mode; The driving execution module is used to send the excitation signal to the design unit according to the driving mode; The first monitoring module is used to obtain input terminal information of the design unit and send the input terminal information to the reference model module; The reference model module is used to obtain expected output information according to the input terminal information, and send the expected output information to the performance evaluation module; The second monitoring module is used to obtain the output terminal information of the design unit and send the output terminal information to the performance evaluation module; The performance evaluation module is used to obtain the verification test result of the design unit according to the output terminal information and the expected output information.

5. The UVM verification platform according to claim 4, characterized in that, The basic use case information includes multiple variable interfaces; The use case management module is further used to generate an incentive signal by modifying the variable information of the basic use case information according to the incentive configuration parameters and at least one of the variable interfaces.

6. The UVM verification platform according to claim 1, characterized in that, The command generation module is specifically used to send the target simulation command to the compilation library through the target processor class; wherein the target processor class includes uvm_cmdline_processor.

7. A verification test execution method, characterized in that: The UVM verification platform applied to any one of claims 1 to 6 comprises: The file management module sends the stored test case files to the script processing module; The script processing module obtains the test case name and hardware parameters according to the test case file, and sends the test case name and the hardware parameters to the command generation module; The command generation module generates a target simulation command according to the test case name and the hardware parameters, and sends the target simulation command to the compilation library; The compilation library performs verification testing on the design unit according to the basic use case information and the target simulation command.

8. A verification test execution device, characterized in that: The UVM verification platform applied to any one of claims 1 to 6 comprises: A file sending execution module, configured in the file management module, for sending the stored test case files to the script processing module; A parameter sending execution module, configured in the script processing module, is used to obtain a test case name and hardware parameters according to the test case file, and send the test case name and the hardware parameters to a command generation module; A command sending execution module, configured in the command generating module, is used to generate a target simulation command according to the test case name and the hardware parameters, and send the target simulation command to a compiling library; The verification test execution module is configured in the compilation library and is used to perform verification tests on the design unit according to the basic use case information and the target simulation command.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the verification test execution method of claim 7 when executed.

10. According to another aspect of the present invention, there is provided a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the verification test execution method according to claim 7 is implemented.

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