Methods, devices, apparatus, and storage media for handling memory pages

Abstract

This application discloses a method, apparatus, device, and storage medium for processing memory pages, belonging to the field of communication technology. The method involves pre-filling the allocated memory page with first data after allocating a memory page for the virtual address that triggers a page fault. Then, the memory page filled with the first data is accessed. If the data in the memory page is subsequently moved to a cache, the first data filled in the memory page is also moved to the cache. If the data of the memory page in the cache is evicted from memory, the evicted cached data may also include the first data. Since the first data is data in the data sequence corresponding to the cache compression mode, when cached data including the first data is evicted back to memory, the probability of the cached data matching the cache compression mode is increased, thereby improving the compression ratio of the cached data.

Description

[0001] This application claims priority to Chinese Patent Application No. 202310740304.0, filed on June 20, 2023, entitled "A Method for Setting Up a Memory", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a method, apparatus, device, and storage medium for processing memory pages. Background Technology

[0003] To alleviate the performance bottleneck caused by the memory wall, related technologies attempt to compensate for the performance gap between the central processing unit (CPU) and memory through microarchitecture-level optimizations. For example, chip microarchitecture design attempts to reduce the amount of data communicated off-chip through cache compression techniques such as frequent pattern compression (FPC). Specifically, when data in the CPU cache is evicted from a cache line to memory, the memory management unit (MMU) compresses the data in the cache line according to the cache compression pattern that matches the data in the cache line, obtains compressed data, and stores the compressed data in memory, thereby achieving the purpose of evicting data from the cache line to memory.

[0004] However, in addition to the data written by the application, there may be some random values ​​in the cache line, which may cause the data in the cache line to not match the data compression mode well. Data that does not match the data compression mode cannot be stored in memory in a compressed manner when it is evicted from the cache line, which reduces the compression rate of cached data when it is evicted from the cache to memory. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for processing memory pages, which can improve the compression ratio of cached data. The technical solution is as follows:

[0006] Firstly, a method for processing memory pages is provided, comprising the following steps: when a page fault is triggered by a virtual address accessed by an application (referred to as a first address virtual), a memory page (referred to as a first memory page) is allocated to the first virtual address; then, data (referred to as first data) in a cache compression mode corresponding to a data sequence is filled into the first memory page, wherein the cache compression mode is a data compression mode used when migrating data written by the application in the cache to the memory page; and then, the filled first memory page is accessed based on the first virtual address.

[0007] This method pre-fills the allocated memory page with the first data after allocating the memory page for the virtual address that triggers the page fault. Then, the memory page filled with the first data is accessed. If the data in the memory page is subsequently moved to the cache, the first data filled in the memory page will also be moved to the cache. If the data of the memory page in the cache is evicted to memory, the evicted cache data may also include the first data. Since the first data is the data in the data sequence corresponding to the cache compression mode, when cache data including the first data is evicted back to memory, the probability of cache data matching the cache compression mode can be increased, thereby improving the compression ratio of cache data.

[0008] In one possible implementation, the process of filling the first memory page with the first data described above can be: when the application enables the memory prefilling function, the first data is filled into the first memory page, wherein the memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

[0009] Based on the above possible implementation methods, the first data will only be pre-filled for the memory pages allocated to the application when the application enables the memory pre-filling function. This eliminates the need to pre-fill the first data for the memory pages allocated to each running application, thus reducing the workload of filling the first data.

[0010] In one possible implementation, if the application has memory prefilling enabled, before filling the first memory page with the first data, the method further includes the following step: periodically enabling memory prefilling for the application based on the application's running status.

[0011] In one possible implementation, if the application has memory prefilling enabled, before filling the first memory page with the first data, the method further includes the following steps: if the application type is a target type, enable memory prefilling for the application, and the target type application is subject to cache compression mode.

[0012] Based on the above possible implementation methods, the memory prefilling function will only be enabled for the application if the application is subject to this cache compression mode. This will improve the compression efficiency of the application's data when migrating from the cache to memory by prefilling the application's memory pages with the first data during the application's operation. It will also avoid filling the memory pages of applications that are not subject to this cache compression mode with the first data, thus reducing the workload of filling the first data.

[0013] In one possible implementation, the above-mentioned access to the filled first memory page based on the first virtual address includes the following steps: first, receiving a first write request from the application, the first write request instructing the writing of second data to the first virtual address, and then updating the first data at the corresponding position of the first virtual address in the first memory page to the second data.

[0014] Based on the above possible implementation methods, the first data is the data that the application fills into the memory page before writing data. When the application writes data to the memory page later, it can update the first data with the data to be written. In this way, the cache compression rate can be improved by pre-filling the first data without affecting the normal data writing of the application.

[0015] In one possible implementation, multiple second memory pages are used to store task data for the same computational task of the application, and the multiple second memory pages are filled with first data. The method further includes the following steps: receiving a second write request from the application, the second write request indicating that task data is written to a second virtual address; and updating the first data at the corresponding position of the second virtual address in the multiple second memory pages with task data.

[0016] Based on the above possible implementation methods, multiple memory pages corresponding to the same computing task are all filled with the first data. When writing task data to any memory page, the first data in any memory page can be updated to the task data. Even if no task data is written to any of the multiple memory pages, the existence of the first data will prevent random values ​​from being written to that memory page, thereby avoiding random values ​​from affecting the compression of the cached data of that memory page and thus improving the cache compression rate.

[0017] In one possible implementation, the first data is any data in the data sequence; or, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0018] Based on the above possible implementation methods, the first data in the data sequence is filled into the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, some of the first data may still be retained in the cache so that the cache data can more easily match the data compression mode, thereby further improving the compression rate of the cache data.

[0019] In one possible implementation, the first data is the S most frequent data items among multiple data sequences, which correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0020] Based on the above possible implementation methods, the first data in multiple data sequences is filled into the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, some of the first data may still be retained in the cache. This makes it easier for the cache data to match these multiple data compression modes, increasing the probability that the cache data matches the data compression mode, thereby further improving the compression rate of the cache data.

[0021] Secondly, a method for processing memory pages is provided, which includes the following steps: after obtaining an allocation notification message, filling a first memory page with first data, wherein the allocation notification message is used to notify that a page fault caused by the application accessing a first virtual address has been triggered, and that a first memory page has been allocated to the first virtual address, and the first data is data in the data sequence corresponding to the cache compression mode, and the cache compression mode is the data compression mode used when migrating data written by the application in the cache to the memory page.

[0022] In one possible implementation, filling the first memory page with the first data includes the following steps: when the application has enabled the memory prefilling function, the first data is filled into the first memory page, wherein the memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

[0023] In one possible implementation, if the application has memory prefilling enabled, before filling the first memory page with the first data, the method further includes the following step: periodically enabling memory prefilling for the application based on the application's running status.

[0024] In one possible implementation, if the application has memory prefilling enabled, before filling the first memory page with the first data, the method further includes the following steps: if the application type is a target type, enable memory prefilling for the application, and the target type application is subject to cache compression mode.

[0025] In one possible implementation, the first data is any data in the data sequence; or, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0026] In one possible implementation, the first data is the S most frequent data items among multiple data sequences, which correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0027] Thirdly, a memory page processing apparatus is provided, the memory page processing apparatus including a functional module for performing the memory page processing method provided in the first aspect or any alternative manner of the first aspect.

[0028] Fourthly, a memory filling apparatus is provided, the memory filling apparatus including a functional module for performing the memory page processing method provided in the second aspect or any alternative manner of the second aspect.

[0029] Fifthly, an electronic device is provided, comprising a processor for executing program code that causes the electronic device to perform operations performed by the memory page processing method provided in the first aspect or any alternative manner of the first aspect.

[0030] A sixth aspect provides a memory filling apparatus comprising a processor configured to execute program code, causing the memory filling apparatus to perform operations performed by the memory page processing method provided in the second aspect above or any alternative embodiment of the second aspect above.

[0031] In a seventh aspect, a computer-readable storage medium is provided, the storage medium storing at least one piece of program code, which is read by a processor to cause an electronic device to perform operations as provided in the first aspect or any alternative method of the first aspect for processing memory pages.

[0032] Eighthly, a computer-readable storage medium is provided, the storage medium storing at least one piece of program code, which is read by a processor to cause a memory filling device to perform operations as provided in the second aspect or any alternative method of the second aspect above for processing memory pages.

[0033] In a ninth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor of an electronic device reading the program code from the computer-readable storage medium, the processor executing the program code, causing the electronic device to perform the method provided in the first aspect or various optional implementations of the first aspect.

[0034] In a tenth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor of a memory filling device reading the program code from the computer-readable storage medium, the processor executing the program code, causing the memory filling device to perform the method provided in the second aspect or various alternative implementations of the second aspect.

[0035] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0036] Figure 1 This is an electronic device architecture diagram of an application memory page processing method provided in an embodiment of this application;

[0037] Figure 2 This is a flowchart of a memory page processing method provided in an embodiment of this application;

[0038] Figure 3 This is an electronic device architecture diagram of another method for processing application memory pages provided in an embodiment of this application;

[0039] Figure 4 This is a flowchart of another memory page processing method provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram illustrating an application accessing memory according to an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the structure of a memory page processing device provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the structure of a memory filling device provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of another memory filling device provided in an embodiment of this application. Detailed Implementation

[0044] To facilitate understanding of the specific implementation methods of this application, some of the terms used in these specific implementation methods are introduced as follows.

[0045] Memory page: The memory space is divided into equal-sized partitions, each partition being a memory page. Each memory page is represented by a physical page number. Different memory pages have different physical page numbers. Memory pages are also called physical blocks or page frames.

[0046] Virtual pages: The virtual address space of an application is divided into regions of equal size, each region being the same size as a memory page. Each region is a virtual page, and each virtual page is represented by a virtual page number. Different virtual pages have different virtual page numbers. Virtual pages are also called pages or pages.

[0047] Page table: Includes multiple page table entries (PTEs). Each PTE includes a virtual page number of a virtual page, a physical page number of a physical page, and a validity flag to indicate whether the virtual page is mapped to the memory page (i.e., whether the virtual page is loaded into the memory page). The value of the validity flag is used to indicate whether the mapping relationship between the virtual page and the physical page is valid (i.e., whether the PTE is valid). For example, a validity flag value of 1 indicates that the mapping relationship is valid and the virtual page has been loaded into the memory page. A validity flag value of 0 indicates that the mapping relationship is invalid and the virtual page has not been loaded into the memory page.

[0048] Page fault: When an application accesses a virtual page, the memory management unit (MMU) checks the page table to determine if the virtual page has already been loaded into memory. Whenever the virtual page is not loaded into memory, a page fault occurs. The operating system then allocates memory for the virtual page from the memory allocated to the application and loads the virtual page into the allocated memory page to resolve the page fault.

[0049] Virtual address (VA): An address in a virtual address space. The virtual address space includes multiple virtual addresses. A virtual address includes a virtual page number of a virtual page and an offset within the page. The offset within the page indicates the address offset of the virtual address within the virtual page.

[0050] Physical address (PA): This is an address in the physical address space, which is the space provided by memory. The physical address space includes multiple physical addresses. A physical address includes the physical page number of a physical page and the offset within the page. The offset within the page indicates the address offset of the physical address within the memory page.

[0051] Cache compression algorithm: A data compression algorithm used when migrating data from the cache to memory pages. A cache compression algorithm defines at least one cache compression mode, the data compression method for each mode, and the required data sequence for each mode. Different cache compression modes require different data sequences. A cache compression mode is the data compression mode used when migrating cache data to memory pages. When the cache data to be compressed is the same as (matches) the data sequence required by any cache compression mode, the cache compression scheme applicable to that mode can be used to compress the cache data. If the cache data to be compressed is different from the data sequence required by any of the at least one cache compression mode, then data compression cannot be performed. The data sequence required by any cache compression mode includes N (N>1) data points. These N data points are N values ​​in the same N-ary system. Therefore, this data sequence can also be called a numerical sequence. For example, in hexadecimal, each of the N data points is a hexadecimal value from 0 to F. Similarly, in decimal, each data point is a decimal value from 0 to 9. The N data points may be the same value or different values. Each of the N data points is stored in binary data form. When storing, each data point is represented by M (M>0) bits of binary value (0 / 1). Taking N=16 and M=4 as an example, a hexadecimal data point is represented by a 4-bit binary value. When storing, the length of this data sequence is M*N bits.

[0052] FPC is a cache compression algorithm based on cache line compression / decompression. Each cache line is divided into 32-bit words. For example, a 64-byte cache line is 16 words. Each 32-bit word is encoded as a 3-bit prefix plus the data. Specifically, FPC defines seven cache compression modes: zero run, 4-bit sign-extended, 1-byte sign-extended, halfword sign-extended, halfword padded with a zerohalfword, two halfwords (each a byte sign-extended), and word consisting of repeated bytes. Each cache compression mode corresponds to a 3-bit prefix, which represents the corresponding data compression method. Taking zero-run mode as an example, the prefix corresponding to zero-run is 000. The data sequence required by zero-run mode is a 32-bit word represented by the value 0. If the cached data to be compressed is a 32-bit word and the cached data is 0x00000000000000000, then the cached data matches the zero-run mode. The zero-run mode is used to compress the cached data to obtain compressed data 0x0, that is, the compressed data is 0 bits of data + 3 bits of prefix.

[0053] First data: Data that the memory filling device pre-fills in an empty memory page before the application reads or writes data to it. An empty memory page is a memory page that has not been written with any data.

[0054] Memory prefilling function: Instructs the initial data to be filled into an empty memory page before the application accesses it.

[0055] Next, the application environment of the memory page processing method provided in this application will be introduced with reference to the accompanying drawings.

[0056] Figure 1 This is an electronic device architecture diagram illustrating a method for processing application memory pages provided in an embodiment of this application. Figure 1 The electronic device 100 shown can be a terminal, server, or network device. In this embodiment, the device type of the electronic device 100 is not limited.

[0057] like Figure 1As shown, the electronic device 100 includes a processor core 101, a performance monitoring unit (PMU) 102, a translation lookaside buffer (TLB) 103, an memory management unit (MMU) 104, a memory filling device 105, memory 106, and a bus 107. The processor core 101, PMU 102, MMU 104, and TLB 103 are all integrated into a central processing unit (CPU). The CPU includes one or more processor cores 101. The CPU may also include a cache for caching data stored in memory 106. The cache in the CPU can be a multi-level cache, such as a level 1 to level 3 cache, or a level 1 and level 2 cache. In this embodiment, the number and level of caches in the CPU are not limited. The MMU 104 communicates with memory 106 via bus 107. Memory 106 is also called main memory.

[0058] The processor core 101 is used to run applications. One processor core 101 can run one or more applications. During the execution of the application on the processor core 101, the application performs read and write access to the virtual page (i.e., read access or write access). The processor core 101 performs read and write access to the memory page corresponding to the virtual page in memory 106 through MMU 104 to complete the read and write access to the virtual page. Read access refers to reading data in the page, and write access refers to writing data in the page.

[0059] PMU102 is a CPU-embedded performance monitoring component used to collect statistics on specific hardware events (called PMU events) that occur in the CPU. These events include those related to the processor core, cache, and TLB. Processor core-related events include the number of instructions executed, exception capture, clock cycles, and branch prediction errors. Cache-related events include the number of accesses to each cache level and cache misses. TLB103-related events include TLB misses.

[0060] TLB103 is used to cache page table entries in the page table, which is stored in memory 106. MMU104 is a component used to manage memory 106; MMU104 is also called a memory management device. MMU104 can translate virtual addresses accessed by applications into physical addresses in memory 106, allowing access to physical addresses. For example, when processor core 101 is running an application, it sends the virtual address that the application wants to access to MMU104. MMU104 looks up the virtual page number for that virtual address in the page table entries cached in TLB103. If a PTE containing that virtual page number is found, a TLB hit occurs. If a PTE containing the virtual page number is not found in TLB103, a TLB miss occurs. MMU104 retrieves the PTE containing the virtual page number from the page table in memory 106. It then combines the physical page number from the retrieved PTE with the address offset from the virtual address to form a physical address, thus performing the virtual-to-physical address translation. Read and write access is then performed on the location indicated by this physical address in memory 106, enabling read and write access to the virtual address. During application execution, MMU104 migrates frequently accessed data from memory 106 to the last level cache (LLC) in the CPU. When space in the LLC is insufficient, the MMU can evict cached data from at least one cache line in the LLC back to memory 106. During the eviction process, a cache compression algorithm can be used to migrate cached data to memory 106.

[0061] When an application accesses a virtual page that has not been loaded into the memory page, a page fault is triggered. In response to the page fault, the operating system loads the virtual page into a memory page of memory 106. The loaded memory page is an empty memory page without any data. For this empty memory page, the memory filling device 105 pre-fills the memory page with first data before the application accesses the loaded virtual page. This way, when the application subsequently writes data to the virtual page, it can update the first data at the write location in the memory page with the data to be written. Optionally, before filling the memory page with the first data, the memory filling device 105 can also determine whether the application to which the memory page belongs has enabled the memory pre-filling function. If the memory pre-filling function is enabled, the first data is filled into the memory page; otherwise, the first data is not filled into the memory page. For example, the memory filling device 105 can enable the memory pre-filling function for the application based on PMU events monitored by the PMU 102 during application execution. This process will be described in detail later in conjunction with the method embodiments.

[0062] The memory filling device 105 can be implemented in software, hardware, or a combination of both. As an example of a software functional unit, the memory filling device 105 includes program code, and the processor core 101 implements the function of the memory filling device 105 by running the program code.

[0063] The memory filling device 105 is one example of a hardware functional unit. The memory filling device 105 may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0064] When the memory filling device 105 is used as a hardware functional unit, the memory filling device 105 is integrated into the MMU 104 or independent of the MMU 104. For example, the memory filling device 105 is located outside the MMU 104 in the CPU, or outside the CPU in the electronic device 100. Here, the location of the memory filling device 105 is not limited in this embodiment.

[0065] Optionally, such as Figure 1 As shown, the memory filling device 105 includes a judgment unit 51 and a filling unit 52. The judgment unit 51 is used to determine whether the application to which the memory page belongs has enabled the memory prefilling function, and is also used to enable the memory prefilling function for the application based on the PMU events monitored by the PMU 102 during the application's operation. The filling unit 52 is used to prefill the memory page with first data, or not prefill the memory page with the first data, based on the judgment result of the judgment unit 51. For any sub-unit of the judgment unit 51 and the filling unit 52, the sub-unit can be implemented by software, hardware, or a combination of software and hardware. Taking the judgment unit and the filling unit 52 as examples where both are implemented by hardware, such as... Figure 1 As shown, the filling unit 52 is integrated into the MMU 104, and the determination unit 51 is independent of the MMU 104. In other embodiments, both the filling unit 52 and the determination unit 51 are integrated into the MMU 104 or are independent of the MMU 104.

[0066] Next, combined Figure 2 The process of pre-filling the first data in a memory page by the memory filling device is described in detail.

[0067] Figure 2 This is a flowchart of a memory page processing method provided in an embodiment of this application. The method is applied to an electronic device, such as electronic device 100. The method is implemented by the operating system, memory filling device and MMU in the electronic device through interaction. The method includes the following steps.

[0068] 201. When a page fault is triggered by the first virtual address accessed by an application, the operating system allocates a first memory page for the first virtual address.

[0069] Here, the application is any application running on any processor core of any CPU in the electronic device. The application corresponds to a virtual address space. The first virtual address is any virtual address in the virtual address space. For ease of description, the virtual page number in the first virtual address is called the first virtual page number. The virtual page indicated by the first virtual page number is called the first virtual page. The first virtual page is the virtual page accessed by the application. Allocating a memory page for the first virtual address is equivalent to allocating a memory page for the first virtual page. This step 201 is that when the first virtual page accessed by the application triggers a page fault, the operating system allocates a memory page for the first virtual page. The first memory page is the memory page allocated by the operating system for the first virtual page.

[0070] In one possible implementation, if a page fault occurs during the execution of an application by the processing core in the electronic device due to accessing a first virtual address, the processing core notifies the operating system of the page fault. The operating system then allocates a memory page for the first virtual page and loads the first virtual page into the memory page, thus ending the page fault. Next, combining... Figure 3 The electronic device architecture diagram shown and Figure 4 The flowchart shown illustrates another method for handling memory pages, and the triggering and processing flow of a page fault are described below:

[0071] Step A1: During the execution of the application, the processor core sends a first read / write request to the MMU. The first read / write request includes a first virtual address to indicate that data should be read or written to the first virtual address.

[0072] In this context, reading and writing data to the first virtual address means accessing the first virtual address. The first read / write request can be either a write request or a read request. If the first read / write request is a write request, it also includes data to be written (referred to as second data). The first read / write request indicates that the second data is written to the first virtual address. If the first read / write request is a read request, it indicates that the data stored at the first virtual address is read.

[0073] For example, when the processor core executes any instruction in the application (referred to as the first instruction), if there is a need to access the first virtual address, the processor core sends a first read / write request to the MMU.

[0074] Step A2: The MMU receives the first read / write request and, based on the first read / write request, queries the PTE corresponding to the first virtual address (called the first PTE). The first PTE is the PTE in the page table that includes the first virtual page number.

[0075] like Figure 3 As shown, the MMU first requests the TLB to query the first PTE. If the TLB finds the first PTE in its local cache, it returns the first PTE to the MMU. If the first PTE is not found in the TLB, the MMU requests memory to query the first PTE in the page table. If memory finds the first PTE in the page table, it returns the first PTE to the MMU. In this way, the MMU can retrieve the first PTE from either the TLB or memory.

[0076] like Figure 3 As shown, if the TLB does not cache the first PTE but the page table includes the first PTE, the MMU can cache the first PTE from the page table to the TLB as the application runs, so that the application can retrieve the first PTE from the TLB when it accesses the first virtual page again. After the first PTE is cached in the TLB, the TLB may also remove the first PTE from the page table as the application runs.

[0077] After obtaining the first PTE, if the valid identifier in the first PTE is not 0, for example, if the valid identifier in the first PTE is 1, the MMU is triggered to execute the following steps A3 and A4. If the valid identifier in the first PTE is 0, the MMU jumps to execute the following step A5.

[0078] Step A3: If the valid identifier in the first PTE is not 0, the MMU constructs the first physical address to be accessed based on the first PTE and the first virtual address, and accesses the first physical address in memory.

[0079] The first physical address is the physical address corresponding to the first virtual address, that is, the physical address translated from the first virtual address. Accessing the first physical address is used to access the first virtual address.

[0080] For example, the MMU combines the memory page number in the first PTE (called the first memory page number) with the page offset in the first virtual address to obtain the first physical address. When the first read / write request is a read request, the MMU reads the data stored at the first physical address in the first memory page (called the fourth data) to access the first physical address. When the memory access request is a write request, the MMU writes the second data to the first physical address in the first memory page to access the first physical address.

[0081] Step A4: The MMU sends a read / write completion response to the processor core. This response indicates that the read / write operation on the first virtual address is complete, and the process of accessing the first virtual address ends at this point.

[0082] In the case where the first read / write request is a read request, the read / write completion response is a read completion response, indicating that data has been read from the first virtual address. At this time, the read / write completion response also includes fourth data read from the first physical address. In the case where the first read / write request is a write request, the read / write completion response is a write completion response, indicating that second data has been written to the first virtual address.

[0083] Step A5: If the valid identifier in the first PTE is 0, the MMU sends a read / write failure response to the processor core. This read / write failure response indicates that the read / write of the first virtual address failed due to the lack of a corresponding memory page.

[0084] Step A6: Based on the read / write failure response, the processor core suspends the first instruction, triggers a page fault, and sends a page fault notification message to the operating system. This page fault notification message indicates that a page fault occurred when the first virtual page was accessed.

[0085] The page fault notification message includes the first virtual page number.

[0086] Step A7: The operating system receives the page fault notification message and allocates a first memory page for the first virtual page based on the page fault notification message to perform page fault exception handling.

[0087] like Figure 4As shown, after receiving a page fault notification message, the operating system checks the memory pages allocated to the application to see if there are any unoccupied memory pages. The memory pages allocated to the application are the memory pages in the memory space allocated to the application by the operating system when the application requests memory. There are multiple memory pages allocated to the application. Unoccupied memory pages refer to memory pages that have not been loaded into the virtual page, that is, memory pages that have not established a valid mapping relationship with the virtual page in the page table.

[0088] If any of the memory pages allocated to the application are unused, the operating system will allocate any of the unused memory pages to the first virtual page. For example, such as... Figure 3 As shown, the operating system sends a first memory allocation request to the MMU, which includes a first virtual page number and the physical page number of the memory page, indicating that the memory page should be allocated to the first virtual page. Upon receiving the first memory allocation request, the MMU checks the page table for a valid PTE containing that physical page number. Since the memory page is not yet occupied, the MMU cannot find a valid PTE containing that physical page number. The MMU then continues to check the first PTE in the page table, such as... Figure 4 As shown, the MMU fills the physical page number of the memory page into the first PTE, sets the valid flag in the first PTE to 1, and makes the first PTE valid, so as to indicate that the memory page is allocated to the first virtual page, that is, the first virtual page is loaded into any memory page. At this time, the memory page is the first memory page.

[0089] If the application's allocated memory pages do not have any unoccupied pages, then all allocated memory pages are already occupied. The operating system, according to the memory page swapping mechanism, identifies a sacrifice page from the application's occupied memory pages and allocates it to the first virtual page. The sacrifice page is the memory page to be allocated to the first virtual page. For example, as... Figure 3 As shown, the operating system sends a second memory allocation request to the MMU. This second memory allocation request includes the first virtual page number and the physical page number of the sacrificed page, indicating that the sacrificed page should be allocated to the first virtual page. Upon receiving the second memory allocation request, the MMU checks the page table for a valid Page Entity (PTE) containing that physical page number. A valid PTE found is called the second PTE. Finding the second PTE indicates that the sacrificed page has already been allocated to another virtual page besides the first virtual page. To avoid data loss in this other virtual page, such as... Figure 3 and Figure 4As shown, the MMU checks whether the sacrificed page contains data. If it does, the data is written to the electronic device's disk, making the sacrificed page an empty memory page. If no data is stored in the sacrificed page, it remains an empty memory page. When the sacrificed page is empty, the MMU sets the valid flag in the second PTE to 0, invalidating the second PTE. It then looks up the first PTE in the page table, fills the first PTE with the physical page number of the sacrificed page, and sets the valid flag in the first PTE to 1, making the first PTE valid. This indicates that the sacrificed page should be allocated to the first virtual page, i.e., the first virtual page is loaded into the sacrificed page. At this point, the sacrificed page becomes the first memory page.

[0090] The above description uses the example of an invalid first PTE in the page table when an application accesses the first virtual page. In other embodiments, when an application accesses the first virtual page, the MMU may not be able to find the first PTE in the page table. In this case, the MMU still sends a read / write failure response to the processor core, triggering a page fault interrupt, which in turn triggers the operating system to allocate a first memory page for the first virtual page. In this case, after the MMU determines the first memory page to be allocated to the first virtual page (such as a sacrifice page or any unoccupied memory page), the MMU creates a valid first PTE in the page table based on the first virtual page number and the physical page number of the first memory page (called the first physical page number).

[0091] like Figure 3 As shown, after the first PTE is valid, the MMU sends an allocation notification message to the memory filling device. This allocation notification message is used to notify that the first memory page has been allocated to the first virtual page, that is, to notify of a page fault caused by the application accessing the first virtual address, and that the first memory page has been allocated to the first virtual address. After receiving the allocation notification message, the memory allocation unit performs the following step 202 based on the allocation notification message. The allocation notification message includes the first virtual page number and the first physical page number.

[0092] 202. The memory filling device fills the first memory page with first data, which is data in the data sequence corresponding to the cache compression mode. The cache compression mode is the data compression mode used when migrating data written by the application in the cache to the memory page.

[0093] The cache compression mode is a cache compression mode defined in the cache compression algorithm used by the MMU. For example, the cache compression algorithm is FPC or other cache compression techniques that rely on a cache compression mode. The cache compression algorithm defines at least one cache compression mode, the data sequence corresponding to each cache compression mode, and the data compression method. The data sequence corresponding to each cache compression mode is the data sequence required by each cache compression mode for the data to be compressed.

[0094] The first data is the data in the data sequence corresponding to any of the at least one cache compression modes. For example, the first data can be all the data in the data sequence (i.e., each piece of data in the data sequence), or it can be a portion of the data in the data sequence. Taking the first data as a portion of the data sequence as an example, assuming the data sequence includes N data points, the first data is the S most frequently occurring data points in the data sequence, where N is greater than 1, and S is greater than 0 and less than N. For example, if S = 1, taking the zero-run mode in FPC as an example, the hexadecimal value 0 is the most frequently occurring data point in the data sequence corresponding to the zero-run mode. Taking the 1-byte sign extension mode in FPC as another example, the most frequently occurring data point in the 1-byte sign extension mode is the hexadecimal value F. For yet another example, if S = 2, the data sequence is 0000FFFF, and the first data points are 0 and F. Alternatively, the first data is R consecutive data in the data sequence. For example, the first R data in the data sequence is the first data, or the middle R data is the first data, or the last R data is the first data. Here, R is greater than 0 and less than N. R and S may be the same or different. In this embodiment of the application, the values ​​of R and S are not limited.

[0095] In other embodiments, the first data is data from multiple data sequences required by multiple data compression modes defined by the cache compression algorithm. For example, the first data is the S data that appear most frequently in the multiple data sequences, or the first data is data shared by multiple data sequences.

[0096] like Figure 3 As shown, after receiving the allocation notification message from the MMU, the memory filling device, based on the first virtual page number and the first physical page number in the allocation notification message, learns that the MMU has allocated the first memory page to the first virtual page. At this time, the first memory page is an empty memory page, and the memory filling device fills the first memory page with the first data. For example, the first memory page can be filled completely with the first data, or a portion of the memory space of the first memory page can be filled with the first data, while the remaining space is not filled with the first data (i.e., the first memory page is not filled completely with the first data).

[0097] Taking filling the first memory page with the first data as an example, assuming the size of the first memory page is 64 bytes (64 bytes = 16 * 8 * 4 bits), if the size of the first data is 4 bits during storage, as shown in Table 1, the memory filling device fills the first memory page with 8 bits of the first data every 4 bytes (i.e., 8 * 4 bits) to fill the first memory page with the first data. Then, when the application writes data to the first virtual page subsequently, the MMU simply updates the first data at the location to be written in the first memory page with the data to be written.

[0098] Table 1

[0099]

[0100] like Figure 3 As shown, after the first memory page is filled with the first data, the memory filling device sends a fill completion response to the MMU, indicating that the first data has been filled into the first memory page. Upon receiving the fill completion response, the MMU sends an allocation completion response to the operating system, indicating that the first memory page has been allocated to the first virtual page. Upon receiving the allocation completion response, the operating system sends a page fault handling completion response to the processor core, indicating that the page fault caused by the first virtual page has been handled. Upon receiving this interrupt handling completion response, the processor core terminates the page fault handling process, releases the suspended first instruction, and resumes execution of the first instruction. Therefore, for the application, it can only perceive the occurrence of a page fault and is unaware of the pre-filling of the first memory page with the first data.

[0101] When the processor core executes the first instruction again, it sends the first read / write request to the MMU. After receiving the first read / write request again, the MMU accesses the first memory page based on the first virtual address in the first read / write request (i.e., step 203 below).

[0102] 203. The memory management unit accesses the filled first memory page based on the first virtual address.

[0103] For example, if the first read / write request received again is a write request, in order to distinguish it from other write requests in the following text, the first read / write request is referred to as the first write request. The MMU executes step A2 again to query the first PTE corresponding to the first virtual address. At this time, the valid identifier in the first PTE is 1, that is, the first PTE is a valid PTE. Then the MMU constructs the first physical address based on the first PTE and the first virtual address, and writes the second data to the position indicated by the first physical address in the first memory page (called the first position) to realize the writing of data to the corresponding position of the first virtual address in the first memory page. At this time, the first position may be filled with the first data or may not be filled with the first data. If the first position is not filled with the first data, the MMU writes the second data in the first position to complete the access to the first physical address and the first virtual address. If the first position has been pre-filled with the first data, when writing the second data to the first position, the first data at the first position is updated to the second data, wherein the storage space occupied by the second data is greater than or equal to the storage space occupied by the first data. For example, the MMU writes second data to the first location indicated by the first physical address in the first memory page in the form of an overwrite write, so that the first data at the first location is updated to the second data, thereby completing the access to the first physical address and the first virtual address.

[0104] Writing data to the first location means starting to write data from that first location. Taking Table 1 above as an example, assuming the page offset in the first physical address is 0, the first location indicated by the first physical address is the starting location of the first memory page. If the size of the second data is 4 bytes, as shown in Table 2, the MMU updates the first data stored in the first 4 bytes of the first memory page with the second data.

[0105] Table 2

[0106]

[0107] Assuming the first read / write request is a read request, since the first memory page is currently pre-filled with the first data, not the data the application needs to read, the data the application needs to read has not yet been loaded into the first memory page. Figure 3 As shown, in order for the application to read the required fourth data, the MMU first writes the fourth data stored on the disk to the first physical address of the first memory page, so as to update the first data at the first physical address to the fourth data. After that, the application reads the fourth data from the first physical address to complete the access to the first physical address and the first virtual address.

[0108] After completing the access to the first physical address, the access to the first memory page is also completed, and the MMU returns a read / write completion response to the processor core (i.e., step A4 above).

[0109] After the processing core receives the read / write completion response, it continues executing the first instruction or other instructions from the application (referred to as the second instruction). During the execution of the first or second instruction, the application may access the first virtual page or other virtual pages. When accessing the first virtual page, the application may access a virtual address other than the first virtual address within that page, or it may access the first virtual address again. The process of accessing other virtual addresses within the first virtual page is similar to the process of accessing the first virtual address and will not be elaborated here.

[0110] During the execution of an application on the processor core, the application may access the first virtual page multiple times. For any write access to any virtual address of the first virtual page by the application, the MMU updates the first data at the corresponding location of that virtual address in the first memory page with the data to be written. If the application frequently accesses at least one virtual address of the first virtual page during execution, the MMU migrates the data in the target memory space containing that at least one virtual address of the first memory page to a cache line (called the first cache line) in the cache (such as LLC). The at least one virtual address may or may not include the first virtual address. The size of the target memory space is the same as the size of the cache line. The size of the target memory space may be the same as or different from the size of the memory page. If the size of the target memory space is the same as the size of the memory page, the target memory space is the first memory page, and all data stored in the first memory page must be migrated to the first cache line.

[0111] For ease of description, the data in the target memory space (i.e., the data migrated to the cache) is referred to as the first migration data. As the application accesses the target memory space, the first migration data includes the first data and / or the data written by the application. Taking Table 2 as an example, assuming that the size of the cache line is the same as the size of the memory page, both being 64 bytes, and the application frequently accesses the first memory page shown in Table 2, then the first memory page is the target memory space. The second data stored in the first memory page and each piece of the first data constitute the first migration data. The MMU migrates the first migration data to the first cache line in the cache and caches the first PTE in the page table into the TLB.

[0112] After the first migration data is migrated to the first cache line, when the application performs a read access to the first virtual page, the MMU returns the data to be read in the first cache line to the application to enable read access to the first memory page and the first virtual page. When the application performs a write access to the first virtual page, the MMU writes data to the first cache line to enable write access to the first memory page and the first virtual page. At this time, the first migration data is updated, and the updated first migration data is called the second migration data.

[0113] Taking the application's access to the first virtual address as an example, the processor core sends a first read / write request to the MMU. Based on the first virtual address in the first read / write request, the MMU can query the first PTE from the TLB. It then constructs the first physical address based on the first PTE and the first virtual address, and performs a read or write access to the location corresponding to the first physical address in the first cache line. Taking a write access as an example, let's call the data to be written the fifth data. The MMU writes the fifth data to the location corresponding to the first physical address in the first cache line (called the second location) in an overwrite write manner, updating the data at the second location to the fifth data. This, in turn, updates the first migration data in the first cache line to the second migration data. The data at the second location may or may not be the first data. Again, taking the first migration data as shown in Table 2 as an example, assuming the second location is the first bit of the 9th byte of the first memory page, if the fifth data is 4 bytes, as shown in Table 3, after writing the fifth data to the first cache line, the fifth data can overwrite the eight first data bytes from the 9th to the 12th bytes of the first memory page in the first cache line. Assuming the second position is the first bit of the 13th byte of the first memory page, if the fifth data is 2 bytes, as shown in Table 3, after writing the fifth data into the first cache line, the fifth data can overwrite the four first data bytes of the 9th and 10th bytes of the first memory page in the first cache line.

[0114] Table 3

[0115]

[0116] Subsequently, if the cached data (first or second migrated data) in the first cache line meets the eviction condition, the MMU migrates the cached data to the first memory page. This eviction condition is the condition for evicting cached data from the cache line to memory. Assuming the data sequence length required by the cache compression mode is M*N bits, and the storage space size of the first cache line is K bits, where K is greater than M*N, then the first cache line stores K / (M*N) pieces of data to be migrated. Taking Table 3 as an example, if K = 64 bytes and M*N = 4 bytes, then the first cache line stores 16 pieces of data to be migrated. For example, one piece of data is the second data, one piece of data is 8 pieces of the first data, one piece of data is 4 bytes of the fifth data, and one piece of data is 2 bytes of the fifth data and 4 pieces of the first data.

[0117] When migrating cached data from the first cache line to the first memory page, for each piece of data to be migrated, the MMU matches it with the data sequence required by at least one cache compression mode. If the data sequence required by any cache compression mode is the same, then the data to be migrated matches the data sequence and the cache compression mode; otherwise, the data to be migrated does not match the cache compression mode. If the data to be migrated matches any cache compression mode, the MMU uses the data compression method corresponding to that cache compression mode to compress the data to be migrated, obtaining compressed data, and writes the compressed data to the first memory page to achieve the migration of the data to be migrated to the first memory page. If the data to be migrated does not match any cache compression mode, the MMU writes the data to be migrated to the first memory page to achieve the migration of the data to be migrated to the first memory page.

[0118] As shown in Table 3, the data to be migrated may be the first data, a combination of the fifth data and part of the first data (referred to as combined data), or simply the fifth data. If the first data is data within a specific cache compression mode in the cache compression algorithm, then, when the data to be migrated is the first data or combined data, it is more likely to match that cache compression mode than random data. This increases the probability of the data to be migrated being compressed, thereby improving the compression rate of cached data when evicting data from the cache to memory. For example, if the first data is the hexadecimal value 0, the data to be migrated consists of eight zeros, and the cache compression mode is the zero-run mode in FPC, then, compared to random data, the data to be migrated will definitely match the zero-run mode. If the first data is data from multiple data sequences within multiple cache compression modes defined by the cache compression algorithm, such as the S most frequently occurring data in multiple data sequences or data common to multiple data sequences, then when the data to be migrated is the first data or a combination of data, compared to random data, the data to be migrated is more likely to match one of these cache compression modes. This further increases the probability that the data to be migrated will match a cache compression mode, further increasing the probability that the data to be migrated will be compressed, and further improving the compression rate of cached data when evicting data from the cache to memory. Taking the first data as the hexadecimal value 0, the data sequences corresponding to multiple data caching modes in FPC, such as the zero-run mode, the 4-bit sign extension mode, the half-character extension mode, and the half-word mode filled with 0 half-words, all contain the value 0. If the data to be migrated consists of 8 values ​​of 0, it can match the zero-run mode. If the data to be migrated is a combination of multiple 0 values ​​and other values, it may match the 4-bit sign extension mode, the half-character extension mode, or the half-word mode filled with 0 half-words.

[0119] The method provided in this application, after allocating memory pages for the virtual address that triggers a page fault, pre-fills the allocated memory pages with first data. Then, it accesses the memory pages filled with the first data. If the data in the memory pages is subsequently migrated to the cache, the first data filled in the memory pages will also be migrated to the cache. If the data of the memory page in the cache is evicted to memory, the evicted cache data may also include the first data. Since the first data is the data in the data sequence corresponding to the cache compression mode, when cache data including the first data is evicted back to memory, the probability of cache data matching the cache compression mode can be increased, thereby increasing the compression ratio of cache data and reducing the overhead of transferring cache data from the cache to memory.

[0120] Figure 2The illustrated embodiment is based on the example where the memory filling device fills the first memory page with first data after the operating system has allocated the first memory page for the first virtual page. In another possible implementation, such as... Figure 4 As shown, before filling the first data into the first memory page, the memory filling device first determines whether the application accessing the first virtual page has enabled the memory prefilling function. If the application has not enabled the memory prefilling function, the memory filling device does not perform the step of filling the first data into the first memory page and returns a filling failure response to the MMU to indicate that the first data was not filled into the first memory page. Figure 4 In step A8, the application enables memory prefilling. The memory filling device fills the first data in the first memory page allocated to the virtual address and returns a fill completion response to the MMU. Thus, after sending the allocation notification message to the memory filling device, the MMU receives either a fill failure response or a fill completion response from the memory filling device, and then returns an allocation completion response to the operating system. This allows the operating system to send a page fault handling completion response to the processor core, causing the processor core to execute step A1 again. In some embodiments, the memory filling device may not return a fill failure response to the MMU if the first data is not filled into the first memory page, nor may it return a fill completion response if the first data is filled into the first memory page. In such cases, after sending the allocation notification message to the memory filling device, the MMU waits a certain amount of time before returning an interrupt handling completion response to the operating system, reserving time for the memory filling device to fill the first data.

[0121] against Figure 4 In the aforementioned implementation, the memory filling device will only prefill the first data for the memory pages allocated to the application when the application enables the memory prefilling function. This eliminates the need to prefill the first data for the memory pages allocated to each application running on the electronic device, thus reducing the workload of the memory filling device.

[0122] The following describes how to determine whether an application has enabled memory prefilling functionality.

[0123] In one possible approach, the memory filling device enables memory prefilling for the application via either enable mode 1 or enable mode 2.

[0124] Enabling Method 1: When the application type is target type, the memory filling device enables memory prefilling for the application.

[0125] Cache compression mode is suitable for target-type applications, such as compilers, applications for simulating discrete events, and applications for processing large amounts of data. Cache compression mode is not suitable for non-target-type applications, such as compression applications for compressing data and applications for scientific computing.

[0126] Before or during application execution, the memory prefilling device queries the application's configuration information in the operating system to determine the application's program type. If the application's program type matches the target type, the memory prefilling device enables the memory prefilling function for that application. If the application's program type does not match the target type, the memory prefilling device does not enable the memory prefilling function. Enabling this function can be achieved by adding a preset function enable flag to the configuration information; this flag indicates that the application has enabled the memory prefilling function.

[0127] In another possible implementation, the memory filling device is not responsible for enabling memory prefilling for the application. The operating system enables memory prefilling for the target type of application in a similar manner. Alternatively, neither the memory filling device nor the operating system actively enables memory prefilling for the application. Only when the user issues an instruction to enable memory prefilling for the application will the operating system add a preset function enable flag to the application's configuration information according to the user's instruction, thereby enabling memory prefilling for the application.

[0128] Regarding the aforementioned activation method 1, before filling any memory page with the first data, the memory filling device determines whether the application accessing that memory page has enabled the memory pre-filling function by querying its configuration information to see if it includes a preset function activation identifier. Figure 5Taking the illustrated diagram of application memory access as an example, assume the processing core is running process 1 and process 2, with process IDs (PIDs) of 11111 and 22222 respectively. Process 1 and process 2 correspond to application 1 and application 2, respectively. Application 1 is a big data application, suitable for cache compression mode, and has memory prefilling enabled. Application 2 is a compressed application, not suitable for cache compression mode, and has not enabled memory prefilling. The processor core runs application 1 and application 2 by running process 1 and process 2. Assuming that virtual page 1 accessed by process 1 and virtual page 2 accessed by process 2 both trigger page faults, after the MMU creates valid PTEs for virtual pages 1 and 2, it notifies the filling unit in the memory filling device that memory pages have been allocated for virtual pages 1 and 2. Based on the MMU's notification, the memory filling device sends a judgment request to the judgment unit to determine whether the application corresponding to process 1 and process 2 has enabled memory prefilling. After receiving the judgment request, the judgment unit queries the configuration information of application 1 and application 2. It then finds the preset function enable identifier in the configuration information of application 2. If the preset function enable identifier in the configuration information of application 1 corresponds to PID1 of process 1, it returns a judgment response to the filling unit, indicating that application 2 corresponding to process 2 has not enabled the memory pre-filling function, while application 1 corresponding to process 1 has enabled the memory pre-filling function. Upon receiving the judgment response, the memory pre-filling module, according to the indication of the judgment response, fills the memory page allocated for virtual page 1 with the first data, but does not fill the memory page allocated for virtual page 2 with the first data.

[0129] Given that even if the memory pages allocated by the application that does not apply to this cache compression mode are pre-filled with the first data, the data of the application cannot be well matched with the cache compression mode when it is migrated from the cache to memory, the memory filling device will enable the memory pre-filling function for the application only when the application applies to this cache compression mode, so as to improve the compression efficiency of the application's data when it is migrated from the cache to memory by pre-filling the memory pages of the application during the application's operation, and also avoid filling the memory pages of applications that do not apply to this cache compression mode with the first data, thus reducing the workload of the memory filling device.

[0130] Activation Method 2: During application operation, the memory filling device periodically enables the memory pre-filling function for the application based on the application's running status.

[0131] The application's running status is reflected by the first PMU event and / or the second PMU event triggered during the application's operation. The first PMU event is the execution of floating-point arithmetic instructions when the application is running. Floating-point arithmetic instructions refer to instructions used for floating-point operations.

[0132] Secondary PMU events refer to PMU events related to data exchange between cache and memory. Secondary PMU events can reflect the data exchange between cache and memory during application operation. There is at least one secondary PMU event, such as cache miss event, TLB miss event, and pipeline pause (core_pipeline_stall_due_to_cache_miss) event caused by the number of L1 / L2 cache misses.

[0133] In one possible implementation, during application execution, after each time period, the memory filling device predicts whether the cache compression mode is suitable for the application in the next time period based on the application's performance during that time period. If suitable, the memory prefilling function for the next time period is enabled; otherwise, the step of enabling the memory prefilling function for the next time period is not executed. The duration of the current time period is the same as the duration of the next time period, which is the unit duration for enabling the memory prefilling function.

[0134] by Figure 5 For example, during the application's execution, the processor core's PMU records and statistically analyzes the first PMU event and / or the second PMU event triggered by the application. The judgment unit in the memory filling device obtains statistical information of the first PMU event and / or the second PMU event during each time period from the PMU. Based on this statistical information, it predicts whether the cache compression mode is suitable for the application's next time period.

[0135] For example, taking the acquisition of statistical information of the first PMU event in the time period as an example, the statistical information of the first PMU event in the time period is the number of floating-point arithmetic instructions executed in the time period. The judgment unit also obtains the total number of instructions of the application running in the time period from the PMU. Based on the number of floating-point arithmetic instructions and the total number of instructions, it obtains the proportion of floating-point arithmetic instructions among the application instructions running in the time period. This proportion is the ratio between the number of floating-point arithmetic instructions and the total number of instructions. The cache compression mode is applicable to non-floating-point data (such as integer data) and not applicable to floating-point data. If the proportion is less than or equal to the proportion threshold, it means that the application is applicable to the cache compression mode, and the judgment unit enables the memory prefilling function for the next time period for the application. If the proportion is greater than the proportion threshold, it means that the application is not applicable to the cache compression mode, and the judgment unit does not enable the memory prefilling function for the application for the time being.

[0136] Taking the acquisition of statistics for the second PMU event as an example, assuming that at least one of the following events—cache miss, TLB miss, and pipeline pause events caused by L1 / L2 cache misses—is a second PMU event, the statistics for cache miss events during this time period are the number of times a cache miss event occurs (referred to as the first occurrence count). If the first occurrence count is greater than or equal to the first threshold, it indicates that data is frequently exchanged between the cache and memory during this time period. If the first occurrence count is less than the first threshold, it indicates that there is no frequent data exchange between the cache and memory during this time period. Similarly, the statistics for TLB miss events during this time period are the number of times a TLB miss event occurs (referred to as the second occurrence count). If the second occurrence count is greater than or equal to the second threshold, it indicates that data is frequently exchanged between the cache and memory during this time period. If the second occurrence count is less than the first threshold, it indicates that there is no frequent data exchange between the cache and memory during this time period. The statistics for pipeline pause events during this time period are as follows: the total pipeline stall duration caused by these pause events. If the pipeline stall is greater than or equal to the duration threshold, it indicates frequent data exchange between the cache and memory during this time period. If the pipeline stall is less than the duration threshold, it indicates that there was no frequent data exchange between the cache and memory during this time period. If there was frequent data exchange between the cache and memory during this time period, it indicates that the application used this cache compression mode during this time period, and the application may also use this cache compression mode during the next time period. If there was no frequent data exchange between the cache and memory during this time period, it indicates that the application did not use this cache compression mode during this time period, and the application may also not use this cache compression mode during the next time period. Based on this, if the first occurrence count is less than the first number threshold, the second occurrence count is less than the second number threshold, and the pipeline stall is less than the duration threshold, the application will not be subject to the cache compression mode when running in the next time period, and the determination unit will not enable the memory prefilling function for the application. If the first number of transmissions, the second number of occurrences, and the pipeline stall satisfy at least one of the following: the first number of occurrences is greater than or equal to the first number threshold, the second number of occurrences is greater than or equal to the second number threshold, and the pipeline stall is greater than or equal to the duration threshold, the application will be subject to the cache compression mode when running in the next time period, and the determination unit will enable the memory prefilling function for the application in the next time period.

[0137] In other embodiments, the preset submodule does not obtain the statistical information of the first PMU event in the time period, but obtains the statistical information of the second PMU event, and determines whether the memory prefilling function for the next time period needs to be enabled for the application based only on the statistical information of the second PMU event.

[0138] In other embodiments, the judgment unit may also input the statistical information of the first PMU event in the time period and / or the statistical information of the first PMU event into an artificial intelligence (AI) model. The AI ​​model, based on the statistical information of the first PMU event in the time period and / or the statistical information of the first PMU event, outputs a judgment result indicating whether the memory pre-filling function for the next time period needs to be enabled for the application. The threshold judgment submodule, based on the indication of the judgment result, enables the memory pre-filling function for the next time period for the application, or temporarily disables it. The AI ​​model is trained based on statistical information from multiple first training data sets and multiple second training data sets. The first training data sets are statistical information from the first PMU event and / or the second PMU event triggered during the operation of the target type application, and the second training data sets are statistical information from the first PMU event and / or the second PMU event triggered during the operation of non-target type applications. This allows the AI ​​model to learn the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and whether the memory pre-filling function for the next time period needs to be enabled for the application during training. The AI ​​model may be a decision tree model or other types of AI models.

[0139] Taking the acquisition of statistical information of the first PMU event and the second PMU event during the time period as an example, if the statistical information of the first PMU event determines that the application will not be suitable for the cache compression mode when running in the next time period, the judgment unit then determines whether to enable the memory prefilling function for the application in the next time period based on the statistical information of the second PMU event. If the statistical information of the first PMU event determines that the application is suitable for the cache compression mode when running in the next time period, the judgment unit does not need the statistical information of the second PMU event for further judgment. In some embodiments, this judgment logic is implemented using a decision tree. In use, the judgment unit can input the statistical information of the first PMU event and the second PMU event during the time period into the decision tree, and the decision tree outputs a judgment result according to the above judgment logic. This judgment result indicates whether to enable the memory prefilling function for the application in the next time period.

[0140] In other embodiments, the judgment unit may also input the statistical information of the first PMU event during the time period and / or the statistical information of the first PMU event into an artificial intelligence (AI) model. The AI ​​model then outputs the judgment result based on the statistical information of the first PMU event during the time period. This AI model is trained based on statistical information from multiple first training data sets and multiple second training data sets. The first training data sets are statistical information of the first PMU event and / or the second PMU event triggered during the operation of a target type application, and the second training data sets are statistical information of the first PMU event and / or the second PMU event triggered during the operation of a non-target type application. Through training, the AI ​​model learns the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and the judgment result. This AI model is, for example, a neural network model.

[0141] If the determination unit determines that the memory prefilling function is enabled for the application in the next time period, it queries the application's configuration information in the operating system to see if it includes a preset function enable identifier. If the preset function enable identifier is not included, it adds it to the configuration information; otherwise, it does not need to be added. In this way, in the next time period, the determination unit can determine that the application has enabled the memory prefilling function in the next time period based on the preset function enable identifier in the configuration information.

[0142] If the determination unit determines that the memory prefilling function will not be enabled for the application in the next time period, it queries the application's configuration information in the operating system to see if a preset function enable flag is included. If a preset function enable flag is included, it deletes the preset function enable flag from the configuration information. Thus, in the next time period, the determination unit will not be able to find the preset function enable flag in the configuration information, thereby confirming that the application will not enable the memory prefilling function in the next time period.

[0143] Figure 5 The illustrated embodiment is based on the memory filling device including a judgment unit and a filling unit. In other embodiments, the memory filling device is not divided into sub-units. In this case, the steps performed by the judgment unit and the filling unit are implemented by the memory filling device.

[0144] Based on the above-mentioned activation method 2, the memory prefilling function can be periodically enabled for the application during its operation, thereby enabling more granular control over whether the application enables the memory prefilling function. During periods when the memory prefilling function is not enabled, there is no need to fill the empty memory pages loaded into the virtual page with the first data, further reducing the workload of the memory filling device.

[0145] In some other embodiments, the memory prefilling unit does not have the ability to enable the memory prefilling function for the application. In this case, the operating system or other units can enable the memory prefilling function for the application according to the above-described enabling method 1 or enabling method 2.

[0146] Figures 2-5 The embodiments described above are all illustrated using the example of an application accessing a virtual page. In other embodiments, a certain computing task of the application may correspond to multiple virtual pages, and these multiple virtual pages are consecutive. The multiple memory pages corresponding to these multiple virtual pages are used to store the task data of the computing task, which is the data generated by the application during the execution of the computing task.

[0147] When the application writes task data, it may write the task data to all virtual pages among the multiple virtual pages, or it may write the task data to some virtual pages among the multiple virtual pages. When writing data to some virtual pages, the virtual pages to which the task data is written may be adjacent or not. For example, the calculation task corresponds to virtual pages 1-3, and virtual pages 1-3 are consecutive. Assume that when the calculation task meets condition 1, the application writes the task data of the calculation task to virtual page 1; when the calculation task meets condition 2, it writes the task data of the calculation task to virtual page 2; and when the calculation task meets condition 3, it writes the task data of the calculation task to virtual page 3. When the application executes the computation task, the task may not meet one of the conditions 1-3, causing the application to not fill some virtual pages in virtual pages 1-3 with task data. For example, if the computation task only meets conditions 1 and 3 but not condition 2, the application will write task data to virtual pages 1 and 3, but not virtual page 2. In related technologies, the MMU writes task data to memory pages 1 and 3 corresponding to virtual pages 1 and 3 to achieve the writing of task data to virtual pages 1 and 3. Since the application does not write task data to virtual page 2, the MMU will fill the inner page 2 corresponding to virtual page 2 with random values. Once the data in memory pages 1-3 is migrated to the cache, the random values ​​filled in memory page 2 will also be migrated to the cache. When the cached data in memory pages 1-3 in the cache is evicted back to the memory page, the random values ​​in the cached data in memory page 2 make it difficult for the cached data to match the cache compression mode, resulting in a low cache compression rate.

[0148] This application uses a memory filling unit to fill each empty memory page of the application with first data. If the task data of the computation task executed by the application is not filled into the corresponding memory page, the MMU will not continue to fill the memory page with random values ​​since the memory page has already been filled with the first data. This can avoid the problem of low cache compression rate caused by filling random values.

[0149] For example, taking a computational task of an application as an example where multiple virtual pages (referred to as second virtual pages) correspond to a certain virtual page, the memory page corresponding to the second virtual page is referred to as a second memory page. Multiple second memory pages are used to store the task data of that computational task of the application. Following the processing flow of filling the first memory page with first data... Figure 2 or Figure 4 When the corresponding second virtual page is loaded into each second memory page, the memory filling unit fills the second memory page with the first data, thereby enabling the application to pre-fill the first data for each second memory page before writing task data to each second memory page.

[0150] During the execution of the application's computational task by the processor core, when the application writes task data to any virtual address (referred to as the second virtual address) among multiple second virtual pages, the processor core is triggered to send a second write request from the application to the memory management device. This second write request instructs the writing of task data to the second virtual address. Upon receiving the second write request, the memory management device translates the second virtual address in the second write request into a physical address (referred to as the second physical address). The address translation process can be referenced to the process of translating a first virtual address into a first physical address. The memory management device then updates the task data to be written with the first data at the second physical address in the multiple second memory pages, thereby updating the first data at the corresponding location of the second virtual address in the multiple second memory pages to the task data. In this system, the second memory page containing the second physical address is referred to as the third memory page. When writing task data to the second physical address in the third memory page, if the data in the third memory page has not yet been migrated to the cache line (referred to as the second cache line), the memory management device writes the task data to the second physical address in the third memory page. If the data in the third memory page has already been migrated to the second cache line, the memory management device writes the task data to the position corresponding to the second physical address in the second cache line, thus overwriting the first data at that position. Subsequently, if the cached data from the third memory page in the second cache line is evicted back to the third memory page, since the cached data includes the first data, it is easier for the cached data to match the cache compression mode, thereby improving the cache compression ratio.

[0151] After migrating data from multiple second memory pages to the cache, the initial data and / or task data written by the application to these second memory pages are also migrated to the cache. For any memory page other than the third memory page (referred to as the fourth memory page), before writing task data to the fourth memory page, the data in the fourth memory page is the initial data, and the cached data of the fourth memory page in the cache is the second data. If the application does not write task data to the fourth memory page during the execution of the computation task, the cached data of the fourth memory page in the cache will always be the initial data, not a random value. When the cached data of the fourth memory page is subsequently evicted back to the fourth memory page, the cached data is more likely to match the cache compression mode, thereby improving the cache compression ratio. If the application subsequently writes task data to the fourth memory page, this task data will be written to the cached data of the fourth memory page in the cache to overwrite some or all of the initial data in the cached data. When the cached data of the fourth memory page is subsequently evicted back to the fourth memory page, if the cached data of the fourth memory page still contains initial data, this cached data is more likely to match the cache compression mode, thereby improving the cache compression ratio.

[0152] The methods of the embodiments of this application have been described above. The apparatus and devices of the embodiments of this application will be described below. It should be understood that the apparatus and devices described below have the same inventive concept as the methods described above and can achieve the beneficial effects that the methods described above can achieve. The following will be combined with… Figures 6 to 8 The apparatus and device described in this application are described below. It should be understood that the technical features described in the method embodiments are also applicable to the following apparatus and device embodiments.

[0153] Figure 6 This is a schematic diagram of the structure of a memory page processing device provided in an embodiment of this application. Figure 6 The device 600 shown can be an electronic device, such as a terminal, server, or network device; the type of device 600 is not limited here. Figure 6 As shown, device 600 includes:

[0154] The running device 601 is used to allocate a first memory page for the first virtual address by running an operating system when a page fault is triggered by a first virtual address accessed by an application. The running device 601 is a module in the device 600 that runs the operating system.

[0155] The memory filling device 602 is used to fill the first memory page with first data, the first data being data in the data sequence corresponding to the cache compression mode, the cache compression mode being the data compression mode used when migrating the data written by the application in the cache to the memory page;

[0156] The memory management device 603 is used to access the filled first memory page based on the first virtual address.

[0157] In one possible implementation, the memory filling device 602 is further configured to:

[0158] When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

[0159] In one possible implementation, the memory filling device 602 is further configured to:

[0160] The memory filling device periodically enables the memory prefilling function for the application based on the application's running status; otherwise, it does not perform the step of enabling the memory prefilling function for the application.

[0161] In one possible implementation, the memory filling device 602 is further configured to:

[0162] If the application type is the target type, enable the memory prefilling function for the application, and apply the cache compression mode to the target type application.

[0163] In one possible implementation, the memory management device 603 is used for:

[0164] Receive a first write request from the application, the first write request instructing the writing of second data to the first virtual address;

[0165] Update the first data at the location corresponding to the first virtual address in the first memory page to the second data.

[0166] In one possible implementation, multiple second memory pages are all used to store task data for the same computational task of the application, and the multiple second memory pages are all filled with the first data. The memory management device 603 is further used to:

[0167] Receive a second write request from the application, the second write request instructing the task data to be written to a second virtual address;

[0168] The first data at the location corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

[0169] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0170] In one possible implementation, the first data is the S most frequently occurring data in a plurality of data sequences, the plurality of data sequences corresponding to different cache compression modes, and S is greater than 0; or, the first data is data common to the plurality of data sequences.

[0171] When processing memory pages, device 600 is only illustrated using the above-described division of functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of device 600 can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device 600 provided in the above embodiments and the above method embodiments belong to the same concept, and its specific implementation process is detailed in the above method embodiments, and will not be repeated here.

[0172] Figure 7 This is a schematic diagram of the structure of a memory filling device provided in an embodiment of this application, as shown below. Figure 7 As shown, the device 700 includes:

[0173] The acquisition unit 701 is used to acquire an allocation notification message, which is used to notify that a first memory page has been allocated to the first virtual address in response to a page fault caused by the application accessing the first virtual address.

[0174] The filling unit 702 is used to fill the first memory page with first data, the first data being data in the data sequence corresponding to the cache compression mode, the cache compression mode being the data compression mode used when migrating data written by the application in the cache to the memory page.

[0175] In one possible implementation, the filling unit 702 is further used for:

[0176] When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

[0177] In one possible implementation, the device 700 further includes:

[0178] The activation unit is used to periodically enable the memory prefilling function for the application based on the application's running status.

[0179] In one possible implementation, the device 700 further includes:

[0180] An enabling unit is used to enable the memory prefilling function for the application when the application type is a target type, wherein the application of the target type is subject to the cache compression mode.

[0181] The enabling unit involved in the above two implementation methods can be the judgment unit in the memory filling device described in the above embodiments.

[0182] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0183] In one possible implementation, the first data is the S most frequently occurring data in a plurality of data sequences, the plurality of data sequences corresponding to different cache compression modes, and S is greater than 0; or, the first data is data common to the plurality of data sequences.

[0184] It should be understood that when processing memory pages, the device 700 is only illustrating the division of the above-described functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device 700 can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device 700 provided in the above embodiments and the above method embodiments belong to the same concept, and its specific implementation process is detailed in the above method embodiments, and will not be repeated here.

[0185] Figure 8 This is a schematic diagram of another memory filling device provided in an embodiment of this application, as shown below. Figure 8 As shown, the memory filling device 800 includes: a bus 802, a processor 804, a memory 806, and a communication interface 808. The processor 804, memory 806, and communication interface 808 communicate via the bus 802. The memory filling device 800 can be a server or a client. It should be understood that this application does not limit the number of processors and memories in the memory filling device 800. The bus 802 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 8The bus 802 is represented by a single line, but this does not imply that there is only one bus or one type of bus. The bus 802 may include a path for transmitting information between various components of the memory filling device 800 (e.g., memory 806, processor 804, communication interface 808). The processor 804 may include any one or more processors such as a central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP). The memory 806 may include volatile memory, such as random access memory (RAM). The memory 806 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD). The memory 806 stores executable program code, which the processor 804 executes to enable the memory filling device 800 to implement a method for processing memory pages. In one possible implementation, the memory filling device 800 is a chip.

[0186] In an exemplary embodiment, an electronic device is also provided, which includes a processor for executing program code to cause the electronic device to perform operations performed by a processing method applied to memory pages of the electronic device. Exemplarily, the hardware structure of the electronic device can be referenced to a memory filling device 800, except that the program code stored in the memory of the electronic device is used to implement the processing method applied to memory pages of the electronic device.

[0187] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code, which can be executed by the processor of the memory filling device 800 to complete the memory page processing method in the above embodiments. Alternatively, the program code can be executed by the processor of an electronic device to complete the memory page processing method applied to the electronic device in the above embodiments. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device.

[0188] This application also provides a computer program product or computer program, which includes program code. The computer instructions are stored in a computer-readable storage medium. The processor of the memory filling device reads the program code from the computer-readable storage medium and executes the program code, causing the memory filling device to perform the memory page processing method in the above embodiments. Alternatively, the processor of an electronic device reads the program code from the computer-readable storage medium and executes the program code, causing the electronic device to perform the memory page processing method in the above embodiments.

[0189] In this embodiment, the apparatus, device, computer-readable storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0190] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0191] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0192] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0193] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0194] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0195] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0196] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data written to memory pages involved in this application was obtained under fully authorized conditions.

[0197] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0198] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for processing memory pages, characterized in that, The method includes: If a page fault is triggered by the first virtual address accessed by the application, a first memory page is allocated to the first virtual address. First data is filled into the first memory page. The first data is data in the data sequence corresponding to the cache compression mode. The cache compression mode is the data compression mode used when migrating the data written by the application in the cache to the memory page. Based on the first virtual address, the first memory page after being filled is accessed.

2. The method according to claim 1, characterized in that, The step of filling the first memory page with the first data includes: When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

3. The method according to claim 2, characterized in that, When the application enables memory prefilling, before filling the first data into the first memory page, the method further includes: Based on the application's running status, the memory prefilling function is periodically enabled for the application.

4. The method according to claim 2, characterized in that, When the application enables memory prefilling, before filling the first data into the first memory page, the method further includes: If the application type is the target type, enable the memory prefilling function for the application, and apply the cache compression mode to the target type application.

5. The method according to any one of claims 1-4, characterized in that, The access to the padded first memory page based on the first virtual address includes: Receive a first write request from the application, the first write request instructing the writing of second data to the first virtual address; Update the first data at the location corresponding to the first virtual address in the first memory page to the second data.

6. The method according to any one of claims 1-4, characterized in that, Multiple second memory pages are used to store task data for the same computational task of the application, and the multiple second memory pages are all filled with the first data. The method further includes: Receive a second write request from the application, the second write request instructing the task data to be written to a second virtual address; The first data at the location corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

7. The method according to any one of claims 1-4, characterized in that, The first data is each piece of data in the data sequence; Alternatively, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; Alternatively, the first data is R consecutive data points in the data sequence, where R is greater than 0.

8. The method according to any one of claims 1-4, characterized in that, The first data consists of the S most frequently occurring data sequences from a plurality of data sequences, wherein the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data may be data shared by the multiple data sequences.

9. A method for processing memory pages, characterized in that, The method includes: Obtain an allocation notification message, which is used to notify that a first memory page has been allocated to the first virtual address in response to a page fault caused by the application accessing the first virtual address; The first memory page is filled with first data, which is data in the data sequence corresponding to the cache compression mode. The cache compression mode is the data compression mode used when migrating the data written by the application in the cache to the memory page.

10. The method according to claim 9, characterized in that, The step of filling the first memory page with the first data includes: When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

11. The method according to claim 10, characterized in that, When the application enables memory prefilling, before filling the first data into the first memory page, the method further includes: Based on the application's running status, the memory prefilling function is periodically enabled for the application.

12. The method according to claim 10, characterized in that, When the application enables memory prefilling, before filling the first data into the first memory page, the method further includes: If the application type is the target type, enable the memory prefilling function for the application, and apply the cache compression mode to the target type application.

13. A memory page processing device, characterized in that, The device includes: The running device is configured to allocate a first memory page for the first virtual address by running an operating system when a page fault is triggered by a first virtual address accessed by an application. A memory filling device is used to fill the first memory page with first data, the first data being data in a data sequence corresponding to a cache compression mode, the cache compression mode being a data compression mode used when migrating data written by the application in the cache to a memory page; A memory management device for accessing the filled first memory page based on the first virtual address.

14. The device according to claim 13, characterized in that, The memory filling device is also used for: When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

15. The device according to claim 14, characterized in that, The memory filling device is also used for: Based on the application's running status, the memory prefilling function is periodically enabled for the application.

16. The device according to claim 14, characterized in that, The memory filling device is also used for: If the application type is the target type, enable the memory prefilling function for the application, and apply the cache compression mode to the target type application.

17. The device according to any one of claims 13-16, characterized in that, The memory management device is used for: Receive a first write request from the application, the first write request instructing the writing of second data to the first virtual address; Update the first data at the location corresponding to the first virtual address in the first memory page to the second data.

18. The device according to any one of claims 13-16, characterized in that, Multiple second memory pages are used to store task data for the same computational task of the application, and the multiple second memory pages are all filled with the first data. The memory management device is further used to: Receive a second write request from the application, the second write request instructing the task data to be written to a second virtual address; The first data at the location corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

19. The device according to any one of claims 13-16, characterized in that, The first data is each piece of data in the data sequence; Alternatively, the first data is the S data that appear most frequently in the data sequence, where S is greater than 0; Alternatively, the first data is R consecutive data points in the data sequence, where R is greater than 0 and the first data is a hexadecimal value of 0 or a value of F.

20. The device according to any one of claims 13-16, characterized in that, The first data consists of the S most frequently occurring data sequences from a plurality of data sequences, wherein the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data may be data shared by the multiple data sequences.

21. A memory filling device, characterized in that, The device includes: The acquisition unit is used to acquire an allocation notification message, which is used to notify that a first memory page has been allocated to the first virtual address in response to a page fault caused by the application accessing the first virtual address. A filling unit is used to fill the first memory page with first data, the first data being data in the data sequence corresponding to the cache compression mode, the cache compression mode being the data compression mode used when migrating data written by the application in the cache to the memory page.

22. The apparatus according to claim 21, characterized in that, The filling unit is also used for: When the application has memory prefilling enabled, the first data is filled into the first memory page. The memory prefilling function indicates that the first data is filled into the empty memory page before the application accesses the empty memory page.

23. An electronic device, characterized in that, The electronic device includes a processor for executing program code that causes the electronic device to perform the method as claimed in any one of claims 1 to 8.

24. A memory filling device, characterized in that, The memory filling device includes a processor for executing program code that causes the memory filling device to perform the method as described in any one of claims 9 to 12.

25. A computer-readable storage medium, characterized in that, The storage medium stores at least one piece of program code, which is read by a processor to execute the method as described in any one of claims 1 to 12.

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