Programmable circuit single-precision floating-point number square extraction method
The programmable circuit single-precision floating-point number square root method addresses precision and speed issues by using IEEE 754 format adjustments and Cordic algorithm corrections, enhancing operation efficiency and accuracy for decimal operations.
Patent Information
- Application Number
- CN202411240488.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2024-12-20
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing programmable circuits face challenges in performing accurate fixed-point decimal operations, particularly in handling negative numbers and achieving high precision and speed for square root calculations, as current methods discard decimal parts and require lengthy cycles.
A programmable circuit single-precision floating-point number square root method that utilizes the Cordic algorithm with IEEE 754 format adjustments, including coefficient correction and exponent normalization, to enhance precision and speed, allowing for correct handling of negative numbers.
The method significantly improves operation speed by 18 to 33 times and precision by 1 to 3 orders of magnitude, enabling efficient handling of negative numbers and reducing calculation time to one clock cycle.
Smart Images
Figure CN119166942A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of electronic information technology, and in particular to a programmable circuit single-precision floating point number square root method. Background Art
[0002] At present, in the field of CPLD / FPGA application development, only integer operations can be performed directly. It is difficult to perform fixed-point decimal operations. If fixed-point decimal operations are required, the method used is to enlarge 2 n The calculation is performed in a multiple-fold manner, and the result obtained after the calculation is completed is then reduced and restored accordingly.
[0003] In the prior art, the Cordic IP core in Vivado comes with a Cordic square root algorithm, which can be used for integer square root operations.
[0004] However, in the prior art, the decimal part of the calculated result is automatically discarded, the accuracy is extremely low, and the operation speed is very slow and the cycle is long, and the problem that negative numbers cannot be squared cannot be correctly handled. Summary of the invention
[0005] The purpose of the present invention is to provide a single-precision floating-point number square root method of a programmable circuit, aiming to solve the technical problems in the prior art that the decimal part of the calculated result is automatically discarded, the precision is extremely low, the operation speed is very slow, the cycle is long, and the negative number cannot be correctly processed and the square root cannot be taken.
[0006] To achieve the above object, the present invention adopts a programmable circuit single-precision floating-point number square root method, which comprises the following steps:
[0007] Define coefficient constants and initialize variables;
[0008] Input parameter V, judge the positive or negative of parameter V, and determine whether parameter V is 0 or 1;
[0009] Extract the mantissa and exponent of parameter V, and determine whether the exponent is greater than or equal to 127;
[0010] Adjust the mantissa and exponent in the direction that the exponent is non-negative;
[0011] Set variables x and y, x = pure decimal after shift adjustment + 0.25, y = pure decimal after shift adjustment - 0.25;
[0012] Calculate according to the Cordic floating point square root algorithm;
[0013] Result mantissa = x[32:0]*coefficient mantissa;
[0014] Adjust the mantissa and exponent, and combine the exponent and mantissa to get the result;
[0015] Output the operation result and end the operation.
[0016] Among them, the input parameter result uses the 32-bit IEEE 754 single-precision floating point format;
[0017] Define constant IEEE 754 single-precision 32-bit floating-point coefficient localparam m = 32'H3F9A8F4E; / / 1.2074983 This coefficient is the 32-bit single-precision floating-point correction coefficient for the Cordic square root operation, which can be calculated by a special tool. The result of the Cordic square root operation needs to be multiplied by this coefficient for correction to obtain the correct square root result.
[0018] Among them, in the IEEE 754 single-precision format, the highest bit is the sign bit, and the subsequent 8 bits are the exponent bits. The exponent is represented by shift code. The exponent obtained by subtracting 127 from the exponent is the actual exponent. After normalization, the mantissa represents a decimal in the range of 1.0 to 2.0, which is actually 24 bits. The highest bit of the mantissa defaults to 1 and is omitted in the data representation. The remaining 23 mantissa bits are pure decimal bits.
[0019] The parameter V only needs to check the highest bit of the data to determine whether it is positive or negative. When V
[31] =1, it indicates a negative number. Negative numbers cannot be squared in the real number range, so the input is an illegal value. After the program operation, the result output is in a high-impedance state. Otherwise, it is a non-negative number and the square root operation can be performed.
[0020] Among them, for other input data, the exponent and mantissa of the input data are directly extracted. If the exponent is greater than or equal to 127, it means that the exponent is a non-negative exponent, and the exponent minus 127 is the actual exponent; when the exponent is less than 127, it means that the exponent is a negative exponent, and the data obtained by subtracting the exponent from 127 is the actual exponent.
[0021] Among them, 0.25 in the variable x and the variable y can be expressed as an IEEE 754 format floating point number, and the mantissa of 0.25 in the IEEE 754 format also needs to be adjusted to a pure decimal, with an exponent of -2.
[0022] The beneficial effects of the programmable circuit single-precision floating-point number square root method of the present invention are as follows: compared with the traditional square root algorithm, the operation speed is increased by 18 to 33 times, the data square root operation speed is greatly improved, the system calculation efficiency is improved, and the operation precision is improved. The 32-bit single-precision floating-point number Cordic square root algorithm of IEEE 754 is used to complete a square root operation, which only requires one clock cycle, and the calculated result precision is 1 to 3 orders of magnitude higher, the timing matching of multiple modules is more convenient, the system calculation efficiency is greatly improved, and the problem that negative numbers cannot take square roots can be correctly handled through program correction. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 The invention discloses a flow chart of the steps of a programmable circuit single-precision floating-point number square root method. DETAILED DESCRIPTION
[0025] See also Figure 1 The present invention provides a programmable circuit single-precision floating-point number square root method, comprising the following steps:
[0026] Define coefficient constants and initialize variables;
[0027] Input parameter V, judge the positive or negative of parameter V, and determine whether parameter V is 0 or 1;
[0028] Extract the mantissa and exponent of parameter V, and determine whether the exponent is greater than or equal to 127;
[0029] Adjust the mantissa and exponent in the direction that the exponent is non-negative;
[0030] Set variables x and y, x = pure decimal after shift adjustment + 0.25, y = pure decimal after shift adjustment - 0.25;
[0031] Calculate according to the Cordic floating point square root algorithm;
[0032] Result mantissa = x[32:0]*coefficient mantissa;
[0033] Adjust the mantissa and exponent, and combine the exponent and mantissa to get the result;
[0034] Output the operation result and end the operation.
[0035] Furthermore, the input parameter result is in 32-bit IEEE 754 single-precision floating point format;
[0036] Define constant IEEE 754 single-precision 32-bit floating-point coefficient localparam m = 32'H3F9A8F4E; / / 1.2074983 This coefficient is the 32-bit single-precision floating-point correction coefficient for the Cordic square root operation, which can be calculated by a special tool. The result of the Cordic square root operation needs to be multiplied by this coefficient for correction to obtain the correct square root result.
[0037] Furthermore, in the IEEE 754 single-precision format, the highest bit is the sign bit, and the subsequent 8 bits are the exponent bits. The exponent is represented by shifting code, and the exponent obtained by subtracting 127 from the exponent is the actual exponent. After normalization, the mantissa represents a decimal in the range of 1.0 to 2.0, which is actually 24 bits, of which the highest bit of the mantissa defaults to 1 and is omitted in the data representation, and the remaining 23 mantissa bits are pure decimal bits.
[0038] Furthermore, the positive or negative value of parameter V only needs to check the highest bit of the data. When V
[31] =1, it means it is a negative number. Negative numbers cannot be squared in the real number range. Therefore, the input is an illegal value. After the program operation, the result output is in a high-impedance state. Otherwise, it is a non-negative number and the square root operation can be performed.
[0039] Furthermore, for other input data, the exponent and mantissa of the input data are directly extracted. If the exponent is greater than or equal to 127, it means that the exponent is a non-negative exponent, and the exponent minus 127 is the actual exponent; when the exponent is less than 127, it means that the exponent is a negative exponent, and the data obtained by subtracting the exponent from 127 is the actual exponent.
[0040] Furthermore, 0.25 in the variables x and y can be expressed as IEEE 754 format floating point numbers, and the mantissa of 0.25 in IEEE 754 format also needs to be adjusted to a pure decimal, with an exponent of -2.
[0041] In this embodiment, compared with the traditional square root algorithm, the operation speed is increased by 18 to 33 times, which greatly improves the data square root operation speed, improves the system calculation efficiency, and improves the calculation accuracy. The IEEE 754 32-bit single-precision floating point number Cordic square root algorithm is used to complete a square root operation, which only requires 1 clock cycle. The calculated result is 1 to 3 orders of magnitude higher in accuracy, and the timing of multiple modules is more convenient to match. The system calculation efficiency is greatly improved. Through program correction, the problem that negative numbers cannot take square roots can be correctly handled.
[0042] Extract the mantissa of 0.25 as a 32-bit floating point number and use it as the offset for the Cordic square root calculation. The calculation formula is as follows:
[0043] x=mantiss+mantiss2; / / The mantissa of +0.25, 0x3E800000, has been adjusted to a pure decimal. The exponent of -2 is equivalent to the decimal points being aligned. In the calculation process, there is no need to consider the problem of mixed operations of integers and decimals. Only pure decimal calculations are considered. After this special processing, the mantissa of the original non-pure decimal is turned into a pure decimal, which greatly simplifies the calculation process, saves hardware resources, greatly reduces the calculation time, and improves the data calculation accuracy.
[0044] The Cordic square root algorithm for pure decimals is as follows:
[0045] The initial state is:
[0046] xtmp=x>>>(idx);
[0047] ytmp=y>>>(idx);
[0048] Where idx is the number of iterations. A 32-bit single-precision floating point number has a 23-bit mantissa. In actual calculations, 23 iterations are required, and the iterative calculations are repeated from idx = 1 to idx = 23. If y < 0, use:
[0049] x=x+ytmp;
[0050] y=y+xtmp;iterate, otherwise use the following formula:
[0051] x = x-ytmp;
[0052] y=y-xtmp; iterate.
[0053] It should be noted that if idx=4, 13, one more iteration is required.
[0054] The number of clocks for the square root operation is greatly reduced, which is the key to quickly completing the square root operation. After 23 iterations, take x[23:0] as the temporary mantissa after the square root and then multiply it by the correction coefficient mantissa to get mantissa_result_tmp. According to the result of the mantissa product mantissa_result_tmp[46:45], readjust the mantissa and exponent calculation to get the actual result of the square root.
[0055] The square root of IEEE 754 single-precision floating-point numbers based on the Cordic algorithm is used to calculate the square root in the Vivado simulation environment. One clock can calculate one square root. The calculation process is as follows:
[0056] (1) When v = 32'HBF800000; / / that is, v = -1;
[0057] v
[31] >0; / / input a negative number, cannot square root
[0058] result=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; / / return to high impedance state
[0059] (2) When v = 32'H3F800000; / / that is, v = 1;
[0060] result=32'H3F800000; / / result=1; return result and exit
[0061] (3) When v = 32'H3F4F5C29; / / v = 0.81, for ease of understanding, this calculation is a detailed calculation process example
[0062] localparam m = 32'H3F9A8F4E; / / define the correction coefficient 1.2074983 single precision floating point number
[0063] v
[31] =0; / / Non-negative number, not 0 or 1, can be square rooted.
[0064] exponent = v[30:23]; / / extract exponent
[0065] mantiss = {1'b1, v[22:0]}; / / extract mantissa
[0066] exponent<8'd127
[0067] normBitsVal = 8'd127-exponent; / / Calculate the effective exponent
[0068] direction = 1'b1; / / Set the exponential calculation direction flag
[0069] normBitsVal = normBitsVal-1'b1; / / adjust index
[0070] mantiss = mantiss>>>1; / / Adjust the mantissa to a pure decimal
[0071] normBitsDivTwo = normBitsVal>>1; / / Preliminary calculation of the exponent after square root
[0072] mantiss2 = 32'h00200000; / / Calculate and extract the adjusted 0.25 mantissa, at this time the exponent is exactly 0
[0073] mantissm = {9'd1, m[22:0]}; / / Extract the adjusted mantissa of the correction coefficient m
[0074] x = mantiss + mantiss2; / / +0.25 mantissa 0x3E800000, exponent is -2
[0075] y = mantiss-mantiss2; / / -0.25 mantissa
[0076] / / Enter the Cordic floating point arithmetic iteration algorithm
[0077] mantissa_a = x[23:0]; / / extract 24-bit mantissa
[0078] mantissa_result_tmp = mantissa_a*mantissm; / / Calculate the mantissa of the product
[0079] / / Adjust the mantissa and exponent
[0080] exponent_result = 8'd126-normBitsDivTwo+cex; / / Adjust the index according to the direction sign / / cex is the adjusted index during the period.
[0081] result = {1'b0, exponent_result, mantissa_result[22:0]}; / / Calculate the result.
[0082] / / Calculate result = 0.9000000357;
[0083] (4), v = 7; result = 2.6457531452; / / The calculation process is the same as (3).
[0084] (5), v = 8.1; result = 2.8460514545; / / The calculation process is the same as (3).
[0085] (6), v = 89; result = 9.4339809417; / / The calculation process is the same as (3).
[0086] In the same environment, Vivado's Cordic IP core is used to calculate square roots in an unsigned fixed-point decimal format. Each square root operation of a number actually requires 33 clock cycles. Considering the data size range and precision, a 16-bit integer and 15-bit decimal fixed-point format is used without loss of generality. The highest bit is the sign bit, and the square root is magnified by 2. 15 , and then perform the corresponding reduction processing after taking the square root. The calculation results are as follows:
[0087] (1) When v = -32768; / / -1*2^15; -1 enlarges 2 15 times
[0088] result = -1257978382; / / The actual value is: -1258152166 / 2^23 = -149.962709188461, reduced by 2 23 / / This algorithm cannot correctly handle the problem that negative numbers cannot be squared in the real number range.
[0089] (2) When v = 32768; / / 1*2^15; 1 enlarges 2 15 times
[0090] result = 8388608; / / The actual value is: 8388608 / 2^23 = 1.0, reduced by 2 23
[0091] (3) When v = 26542; / / 0.81*2^15;
[0092] result = 7549735; / / The actual value is: 7549735 / 2^23 = 0.899998545646667, reduced by 2 23
[0093] (4) When v = 229376; / / 7*2^15
[0094] result = 22194170; / / The actual value is: 22194170 / 2^23 = 2.64575123786926, reduced by 2 23
[0095] (5) When v = 265421; / / 8.1 * 2^15
[0096] result = 23874405; / / The actual value is: 23874405 / 2^23 = 2.84605085849762, reduced by 2 23
[0097] (6), v=2916352; / / 89*2^15;
[0098] result = 79137969; / / 79137969 / 2^23 = 9.43398106098175, reduced by 2 23
[0099] In order to verify the accuracy of this algorithm, we can refer to the square root calculation results of Matlab for comparison as follows:
[0100] vpa(sqrt(-1),20)=1.0i; / / 20 digits, because MATLAB supports complex number operations
[0101] vpa(sqrt(1),20)=1.0; / / 20 digits
[0102] vpa(sqrt(0.81),20)=0.900000000000000022; / / 20 digits
[0103] vpa(sqrt(7),20)=2.64575131106459072; / / 20 digits
[0104] vpa(sqrt(8.1),20)=2.84604989415154153; / / 20 digits
[0105] vpa(sqrt(89),20)=9.43398113205660316; / / 20 digits
[0106] Through verification, it was found that the calculation accuracy of the CordicIP square root extraction algorithm that comes with Vivado can reach an accuracy of one ten-thousandth to one hundred-thousandth, and the algorithm needs to consume 33 clock cycles to calculate the square root of a number; the data calculation accuracy is greatly affected by the size of the input data, the accuracy of the data result is unstable, the problem of negative square root cannot be correctly handled, and the timing matching of multi-module cascade is difficult, affecting the calculation efficiency of the entire system; while the calculation accuracy of the IEEE 754 single-precision floating-point Cordic square root extraction algorithm can reach one hundred thousandth to one millionth, and each calculation of a square root only requires one clock, which is 33 times the speed of the CordicIP core unsigned decimal square root extraction algorithm that comes with Vivado, and the accuracy of the square root extraction is one order of magnitude higher, which can correctly handle the problem of negative square root extraction.
[0107] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.
Claims
1. A method for square rooting single-precision floating-point numbers using a programmable circuit, characterized in that: The steps include: Define coefficient constants and initialize variables; Input parameter V, judge the positive or negative of parameter V, and determine whether parameter V is 0 or 1; Extract the mantissa and exponent of parameter V, and determine whether the exponent is greater than or equal to 127; Adjust the mantissa and exponent in the direction that the exponent is non-negative; Set variables x and y, x = pure decimal after shift adjustment + 0.25, y = pure decimal after shift adjustment - 0.25; Calculate according to the Cordic floating point square root algorithm; Result mantissa = x[32:0]*coefficient mantissa; Adjust the mantissa and exponent, and combine the exponent and mantissa to get the result; Output the operation result and end the operation.
2. A programmable circuit single-precision floating-point number square root method as claimed in claim 1, characterized in that: The input parameter result is in 32-bit IEEE 754 single-precision floating point format; Define constant IEEE 754 single-precision 32-bit floating-point coefficient localparam m = 32'H3F9A8F4E; / / 1.2074983 This coefficient is the 32-bit single-precision floating-point correction coefficient for the Cordic square root operation, which can be calculated by a special tool. The result of the Cordic square root operation needs to be multiplied by this coefficient for correction to obtain the correct square root result.
3. A programmable circuit single-precision floating-point number square root method as claimed in claim 1, characterized in that: In the IEEE 754 single-precision format, the highest bit is the sign bit, and the subsequent 8 bits are the exponent bits. The exponent is represented by shift code. The exponent obtained by subtracting 127 from the exponent is the actual exponent. After normalization, the mantissa represents a decimal in the range of 1.0 to 2.0, which is actually 24 bits. The highest bit of the mantissa defaults to 1 and is omitted in the data representation. The remaining 23 mantissa bits are pure decimal bits.
4. A programmable circuit single-precision floating-point number square root method as claimed in claim 1, characterized in that: The positive or negative of parameter V only needs to check the highest bit of the data. When V[31]=1, it means it is a negative number. Negative numbers cannot be squared in the real number range. Therefore, the input is an illegal value. After the program operation, the result output is in a high-impedance state. Otherwise, it is a non-negative number and the square root operation can be performed.
5. A programmable circuit single-precision floating-point number square root method as claimed in claim 1, characterized in that: For other input data, the exponent and mantissa of the input data are directly extracted. If the exponent is greater than or equal to 127, it means that the exponent is a non-negative exponent, and the exponent minus 127 is the actual exponent. When the exponent is less than 127, it means that the exponent is a negative exponent, and the data obtained by subtracting the exponent from 127 is the actual exponent.
6. A programmable circuit single-precision floating-point number square root method as claimed in claim 1, characterized in that: The 0.25 in the variables x and y can be expressed as an IEEE 754 format floating point number. The mantissa of 0.25 in the IEEE 754 format also needs to be adjusted to a pure decimal, with an exponent of -2.