Simulation analysis method and device applied to DDR system, equipment, storage medium and product
By extracting target parameters and simulating a sample DDR channel to determine the worst channel, the method efficiently analyzes DDR systems, reducing simulation time from months to weeks, addressing the inefficiencies of traditional DDR system simulation.
Patent Information
- Application Number
- CN202411198285.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-20
AI Technical Summary
The existing simulation analysis methods for DDR systems are laborious and time-consuming, particularly in constructing electromagnetic models, which require extensive modeling and simulation of all channels, taking months to complete a round of simulation, especially when considering process variations and different scenarios.
A method and device for DDR systems that involve extracting target parameters from design files, simulating a sample DDR channel to obtain eye diagram data, constructing an eye diagram data calculation formula, and determining the worst DDR channel, allowing for efficient simulation and analysis by focusing on this channel to meet time domain eye diagram indicators.
This approach significantly reduces simulation time from months to weeks, improving efficiency by 1/6, as it only analyzes the worst DDR channel, thus addressing the inefficiencies of traditional methods.
Smart Images
Figure CN119167843A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of simulation analysis technology, and in particular to a simulation analysis method, device, equipment, storage medium and product applied to a DDR system. Background Art
[0002] Due to the high signal density and fast read and write speed, the DDR (Double Data Rate Synchronous Dynamic Random Access Memory) system will face signal integrity problems such as reflection, crosstalk, and insufficient timing margin. How to solve these problems is the key to the success of the entire DDR system design. Therefore, when performing chip, package and system-level design, it is necessary to perform system-level signal integrity simulation on DDR to verify the quality of its signal.
[0003] At present, the simulation of DDR is to import the design files of package and PCB into the simulation platform, model each channel through 2.5D or full-wave 3D electromagnetic modeling, analyze the simulation data in the frequency domain to obtain the channel characteristics, and finally simulate the eye diagram through timing, and compare it with the eye diagram indicators to draw the conclusion of pass and fail. Since the latest DDR rate has reached 10Gb / s+, the fast 2.5D modeling is no longer applicable, and only 3D modeling can be used. However, for a server system with 8 DDR channels, there are at least 960 networks for DDR data and its clock signal. It is very laborious and time-consuming to directly extract the passive parameter models of all channels and then cascade them for time domain simulation. It takes at least 3-4 weeks just to extract the model. If you want to traverse each PVT corner (Process Voltage Temperature corner), consider the impact of processing deviations, and support different simulation scenarios, it will take more than 3 months to complete a round of simulation of these channels. Summary of the invention
[0004] The main purpose of the present application is to provide a simulation analysis method, device, equipment, storage medium and product applied to a DDR system, aiming to solve the technical problem that the existing simulation analysis method has a long simulation time for the DDR system.
[0005] To achieve the above object, the present application provides a simulation analysis method applied to a DDR system, the method comprising the following steps:
[0006] When receiving a simulation instruction, exporting target routing information from a design file, and extracting target parameters from the target routing information;
[0007] Simulating a sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to a sample DDR signal in the sample DDR channel;
[0008] constructing an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determining the worst DDR channel in the DDR system according to the eye diagram data calculation formula;
[0009] The DDR system is simulated and analyzed based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain.
[0010] In one embodiment, the design file includes a package design file and a PCB design file, the target parameters include package target parameters and PCB target parameters, and when a simulation instruction is received, the step of deriving target routing information from the design file and extracting target parameters from the target routing information includes:
[0011] When receiving a simulation instruction, exporting package routing information from a package design file, and extracting package target parameters from the package routing information;
[0012] PCB routing information is exported from a PCB design file, and PCB target parameters are extracted from the PCB routing information.
[0013] In one embodiment, the package target parameters include the total package length, the package fanout area line length and the package breakout area line length, and the PCB target parameters include the total PCB length, the PCB breakout area line length and the PCB routing layer.
[0014] In one embodiment, the sample DDR channels include the channel with the longest total routing in the package, the channel with the longest routing in the neck area of the package, and the channel with the longest routing in each layer of the PCB.
[0015] In one embodiment, the step of constructing an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determining the worst DDR channel in the DDR system according to the eye diagram data calculation formula includes:
[0016] Performing weighted fitting on the target parameters according to the error between the sample eye diagram data and the design target to obtain an eye diagram data calculation formula;
[0017] The eye diagram data corresponding to all DDR channels in the DDR system are calculated according to the eye diagram data calculation formula, and the DDR channel with the smallest eye diagram data in the DDR system is determined as the worst DDR channel.
[0018] In one embodiment, the step of performing simulation analysis on the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram indicator in the time domain includes:
[0019] If the worst DDR channel meets the design target, it is determined that the DDR system meets the eye diagram indicator in the time domain;
[0020] If the worst DDR channel does not meet the design target, it is determined that the DDR system does not meet the eye diagram indicator in the time domain.
[0021] In addition, to achieve the above-mentioned purpose, the present application also proposes a simulation analysis device applied to a DDR system, and the simulation analysis device applied to a DDR system comprises:
[0022] A parameter extraction module, used for deriving target routing information from a design file and extracting target parameters from the target routing information when receiving a simulation instruction;
[0023] A sample simulation module, used for simulating a sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to a sample DDR signal in the sample DDR channel;
[0024] A data calculation module, configured to construct an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determine the worst DDR channel in the DDR system according to the eye diagram data calculation formula;
[0025] The simulation analysis module is used to perform simulation analysis on the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain.
[0026] In addition, to achieve the above-mentioned purpose, the present application also proposes a simulation and analysis device applied to a DDR system, wherein the device includes: a memory, a processor, and a simulation and analysis program applied to a DDR system stored in the memory and executable on the processor, wherein the simulation and analysis program applied to a DDR system is configured to implement the steps of the simulation and analysis method applied to a DDR system as described above.
[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and stores a simulation analysis program applied to the DDR system. When the simulation analysis program applied to the DDR system is executed by a processor, the steps of the simulation analysis method applied to the DDR system as described above are implemented.
[0028] In addition, to achieve the above-mentioned purpose, the present invention also provides a computer program product, which includes a simulation analysis program applied to a DDR system, and when the simulation analysis program applied to a DDR system is executed by a processor, it implements the steps of the simulation analysis method applied to a DDR system as described above.
[0029] The present application, when receiving a simulation instruction, exports the target routing information from the design file, and extracts the target parameters from the target routing information; simulates the sample DDR channel selected from the DDR system to obtain the sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel; constructs an eye diagram data calculation formula based on the target parameters and the sample eye diagram data, and determines the worst DDR channel in the DDR system according to the eye diagram data calculation formula; simulates and analyzes the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram indicators in the time domain. Compared with the traditional DDR system simulation and analysis method, the above method of the present application determines the worst DDR channel in the DDR system by constructing the eye diagram data calculation formula corresponding to the obtained DDR system, and then only simulates and analyzes the worst DDR channel, so as to determine whether the DDR system meets the eye diagram indicators in the time domain, thereby avoiding the technical drawback of the prior art that a lot of time is required to simulate and analyze the entire DDR system, thereby improving the simulation and analysis efficiency of the DDR system. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of the structure of a simulation analysis device applied to a DDR system in a hardware operating environment involved in an embodiment of the present application;
[0031] Figure 2 This is a flow chart of a first embodiment of a simulation analysis method for a DDR system according to the present application;
[0032] Figure 3 This is a flow chart of a second embodiment of the simulation analysis method of the present application applied to a DDR system;
[0033] Figure 4 This is a flow chart of a third embodiment of the simulation analysis method of the present application applied to a DDR system;
[0034] Figure 5 This is a structural block diagram of the first embodiment of the simulation analysis device applied to the DDR system of the present application.
[0035] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0036] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0037] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a simulation analysis device applied to a DDR system in the hardware operating environment involved in the embodiment of the present application.
[0038] like Figure 1 As shown, the simulation and analysis device applied to the DDR system may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM), or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0039] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the simulation analysis device applied to the DDR system, and may include more or less components than those shown in the figure, or combine certain components, or arrange the components differently.
[0040] like Figure 1 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a simulation analysis program applied to the DDR system.
[0041] exist Figure 1In the simulation and analysis device applied to the DDR system shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the simulation and analysis device applied to the DDR system of the present application can be set in the simulation and analysis device applied to the DDR system, and the simulation and analysis device applied to the DDR system calls the simulation and analysis program applied to the DDR system stored in the memory 1005 through the processor 1001, and executes the simulation and analysis method applied to the DDR system provided in the embodiment of the present application.
[0042] The present application embodiment provides a simulation analysis method applied to a DDR system. Figure 2 , Figure 2 FIG. 1 is a flow chart of a first embodiment of a simulation analysis method for a DDR system according to the present invention.
[0043] In this embodiment, the simulation analysis method applied to the DDR system includes the following steps:
[0044] Step S10: when a simulation instruction is received, target routing information is exported from the design file, and target parameters are extracted from the target routing information.
[0045] It should be noted that the execution subject of the method of this embodiment can be a terminal device with simulation analysis, data processing and program running functions, such as a smart phone, a computer, etc., or an electronic device with the same or similar functions, such as the above-mentioned simulation analysis device applied to the DDR system. The following takes the simulation analysis device applied to the DDR system (hereinafter referred to as the analysis device) as an example to illustrate this embodiment and the following embodiments.
[0046] It is understandable that the above-mentioned design files may include package design files and PCB (Printed Circuit Board) design files. Among them, the target routing information of the package design file may include but is not limited to the total length of the package, the line length of a single area of the package, the pin arrangement and spacing, the size and shape of the pad, etc., and the target routing information of the PCB design file may include the total length of the PCB, the line length of a single area of the PCB, the line width and line spacing, the minimum gap between copper foil lines, the distance between the copper foil line and the edge of the PCB board, etc. This embodiment does not limit the target routing information respectively contained in the package design file and the PCB design file.
[0047] It should be understood that the above target parameters may refer to parameters required for simulation.
[0048] Step S20: simulating the sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel.
[0049] It should be noted that the sample DDR channel may be a representative DDR channel in a DDR system, for example, a channel with the longest routing.
[0050] It should be understood that simulating a sample DDR channel to obtain the eye diagram data of the DDR signal is an important step in signal integrity analysis. The eye diagram can intuitively display the signal quality, jitter, noise and other characteristics.
[0051] In a specific implementation, the sample DDR channel selected from the DDR system can be simulated based on the following steps to obtain sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel. The first step is to define the transmitter and receiver of the DDR signal in the simulation tool, and set the channel model based on the operating frequency and signal integrity parameters of the DDR signal (such as the impedance of the transmitter and receiver, the total wiring length and routing design in the channel, power supply noise, wiring coupling, etc.). The second step is to select a suitable simulation tool and perform DDR signal simulation in the selected simulation tool. Configure the necessary excitation signals (such as square waves, pulses, etc.) and run domain simulation. The third step is to obtain the eye diagram data under the specified BER through simulation.
[0052] Step S30: constructing an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determining the worst DDR channel in the DDR system according to the eye diagram data calculation formula.
[0053] It should be understood that the eye diagram data corresponding to all DDR channels in the above DDR system can be calculated according to the above eye diagram data calculation formula, and then the DDR channel with the worst eye diagram data (for example, the smallest eye height value or the smallest eye width value) is selected as the worst DDR channel.
[0054] Step S40: performing simulation analysis on the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain.
[0055] In the specific implementation, it is only necessary to analyze the worst DDR channel under various PVT conditions, consider the impact of processing deviation, and determine whether it meets the design goals for different simulation scenarios. With this method, it only takes 2-3 weeks to complete a round of post-DDR simulation. The simulation cycle is shortened to 1 / 6 of the original, greatly improving work efficiency.
[0056] This embodiment, when receiving a simulation instruction, exports the target routing information from the design file, and extracts the target parameters from the target routing information; simulates the sample DDR channel selected from the DDR system to obtain the sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel; constructs an eye diagram data calculation formula based on the target parameters and the sample eye diagram data, and determines the worst DDR channel in the DDR system according to the eye diagram data calculation formula; simulates and analyzes the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain. Compared with the traditional DDR system simulation and analysis method, the above method of this embodiment determines the worst DDR channel in the DDR system by constructing the eye diagram data calculation formula corresponding to the obtained DDR system, and then only simulates and analyzes the worst DDR channel, so as to determine whether the DDR system meets the eye diagram index in the time domain, thereby avoiding the technical disadvantage of the prior art that a lot of time is required to simulate and analyze the entire DDR system, thereby improving the simulation and analysis efficiency of the DDR system.
[0057] refer to Figure 3 , Figure 3 FIG. 1 is a flow chart of a second embodiment of a simulation analysis method for a DDR system according to the present invention.
[0058] In a feasible implementation manner, the design file includes a package design file and a PCB design file, the target parameters include package target parameters and PCB target parameters, and the step S10 may include:
[0059] Step S101: when a simulation instruction is received, package routing information is exported from a package design file, and package target parameters are extracted from the package routing information.
[0060] Step S102: exporting PCB routing information from a PCB design file, and extracting PCB target parameters from the PCB routing information.
[0061] In a feasible implementation, the package target parameters include the total package length, the package fanout area line length and the package breakout area line length, and the PCB target parameters include the total PCB length, the PCB breakout area line length and the PCB routing layer.
[0062] It is understandable that the above-mentioned packaging refers to the chip (Die) being installed on a larger carrier (large-size panel), and then the chip bump is redistributed to a larger-sized BGA. The above-mentioned package fanout area refers to the area where the signal cannot be routed according to the conventional 40-50ohm impedance design routing width and the line spacing that meets the signal integrity crosstalk index from the bump area of the Die. The fanout area is generally routed with the line width and line spacing of the factory's minimum processing capacity. The breakout area refers to the area that can be routed according to the designed line width after passing through the fanout area from the bump, but still cannot be routed according to the normal line spacing. After passing through the package breakout area, it is the regular routing area. The definition of the breakout area of the PCB is similar to that of the package breakout area. It is an area where the line width and line spacing cannot be designed from the BGA. The line width and line spacing of this area are related to the factory's processing capabilities and the pitch of the BGA array. The above-mentioned package fanout, breakout and PCB breakout areas are important parts in package and PCB design. Their main function is to provide sufficient wiring space and transition for the pins of the die and package so as to connect the pins to other locations on the package and PCB to achieve signal transmission and function realization. Specifically, the number of pins of the die (such as bump) and the package (such as BGA, LGA, etc.) is large and the spacing is small. Direct wiring on the package and PCB may be challenged by space limitations and signal integrity. Therefore, setting a specific area around the pins allows designers to perform flexible wiring design in this area to meet the needs of signal transmission and package and PCB layout.
[0063] In a feasible implementation manner, the sample DDR channels include the channel with the longest total routing in the package, the channel with the longest routing in the neck area of the package, and the channel with the longest routing in each layer of the PCB.
[0064] In a specific implementation, the value space of the above-mentioned package target parameters and the above-mentioned PCB target parameters can be defined by the sorted target routing information, as shown in Table 1 below, where t1 represents the total length of the above-mentioned package, t2 represents the line length of the above-mentioned package fanout area, t3 represents the line length of the above-mentioned package breakout area, t4 represents the total length of the above-mentioned PCB, t5 represents the line length of the above-mentioned PCB breakout area, and t6 represents the above-mentioned PCB routing layer.
[0065] Table 1
[0066]
[0067] This embodiment, when receiving a simulation instruction, exports package routing information from a package design file, and extracts package target parameters from the package routing information; exports PCB routing information from a PCB design file, and extracts PCB target parameters from the PCB routing information; the package target parameters include the total package length, the package fanout area line length, and the package breakout area line length, and the PCB target parameters include the total PCB length, the PCB breakout area line length, and the PCB routing layer; the sample DDR channel includes the longest total package routing channel, the longest routing channel in the package neck area (including the fanout and breakout areas), and the longest routing channel in each layer of the PCB. Compared with the traditional DDR system simulation and analysis method, the above method of this embodiment selects the longest total package routing channel, the longest routing channel in the package neck area, and the longest routing channel in each layer of the PCB as the sample DDR channel for simulation, which solves the technical problem of long simulation cycle caused by the need to simulate multiple DDR channels.
[0068] refer to Figure 4 , Figure 4 FIG. 1 is a flow chart of a third embodiment of a simulation analysis method for a DDR system according to the present invention.
[0069] In a feasible implementation manner, the step S30 may include:
[0070] Step S301: performing weighted fitting on the target parameters according to the error between the sample eye diagram data and the design target to obtain an eye diagram data calculation formula.
[0071] Step S302: calculating the eye diagram data corresponding to all DDR channels in the DDR system according to the eye diagram data calculation formula, and determining the DDR channel with the smallest eye diagram data in the DDR system as the worst DDR channel.
[0072] In the specific implementation, eye height or eye width can be used as the fitting target, and the least squares fitting algorithm can be used to weight the parameters t1, t2, t3, t4, t5, and t6 to fit the formula of eye height or eye width. The fitting result and the simulated data of the sample are analyzed for error. If the error meets the requirements, the fitting algorithm ends. If the error does not meet the requirements, the fitting algorithm is repeated.
[0073] For example, the fitted eye height calculation formula may be:
[0074] Y=137.2-0.72t1-1.453t2-0.58t3-6.88t4-9.75t5+match(t6)
[0075] in,
[0076] In a feasible implementation manner, the step S40 may include:
[0077] Step S401: If the worst DDR channel meets the design target, it is determined that the DDR system meets the eye diagram indicator in the time domain.
[0078] Step S402: If the worst DDR channel does not meet the design target, it is determined that the DDR system does not meet the eye diagram indicator in the time domain.
[0079] In the specific implementation, after finding the worst DDR channel, we only need to analyze this channel under various PVT conditions, consider the impact of processing deviations, and determine whether it meets the design goals for different simulation scenarios. With this method, it only takes 2-3 weeks to complete a round of simulation, shortening the simulation cycle to 1 / 6 of the original, greatly improving work efficiency.
[0080] This embodiment performs weighted fitting on the target parameters according to the error between the sample eye diagram data and the design target to obtain an eye diagram data calculation formula; the eye diagram data corresponding to all DDR channels in the DDR system are calculated according to the eye diagram data calculation formula, and the DDR channel with the smallest eye diagram data in the DDR system is determined as the worst DDR channel; if the worst DDR channel meets the design target, it is determined that the DDR system meets the eye diagram index in the time domain; if the worst DDR channel does not meet the design target, it is determined that the DDR system does not meet the eye diagram index in the time domain. Compared with the traditional DDR system simulation and analysis method, the above method of this embodiment simulates and analyzes the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain, avoiding the technical drawback of the prior art that it takes a lot of time to simulate and analyze the entire DDR system, thereby improving the simulation and analysis efficiency of the DDR system.
[0081] In addition, an embodiment of the present application further proposes a storage medium, on which a simulation analysis program applied to a DDR system is stored. When the simulation analysis program applied to a DDR system is executed by a processor, the steps of the simulation analysis method applied to a DDR system as described above are implemented.
[0082] Reference Figure 5 , Figure 5 This is a structural block diagram of the first embodiment of the simulation analysis device applied to the DDR system of the present application.
[0083] like Figure 5 As shown, the simulation analysis device applied to the DDR system proposed in the embodiment of the present application includes:
[0084] A parameter extraction module 501 is used to derive target routing information from a design file and extract target parameters from the target routing information when a simulation instruction is received;
[0085] The sample simulation module 502 is used to simulate the sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel;
[0086] A data calculation module 503, configured to construct an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determine the worst DDR channel in the DDR system according to the eye diagram data calculation formula;
[0087] The simulation analysis module 504 is used to perform simulation analysis on the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram indicator in the time domain.
[0088] This embodiment, when receiving a simulation instruction, exports the target routing information from the design file, and extracts the target parameters from the target routing information; simulates the sample DDR channel selected from the DDR system to obtain the sample eye diagram data corresponding to the sample DDR signal in the sample DDR channel; constructs an eye diagram data calculation formula based on the target parameters and the sample eye diagram data, and determines the worst DDR channel in the DDR system according to the eye diagram data calculation formula; simulates and analyzes the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain. Compared with the traditional DDR system simulation and analysis method, the above method of this embodiment determines the worst DDR channel in the DDR system by constructing the eye diagram data calculation formula corresponding to the obtained DDR system, and then only simulates and analyzes the worst DDR channel, so as to determine whether the DDR system meets the eye diagram index in the time domain, thereby avoiding the technical disadvantage of the prior art that a lot of time is required to simulate and analyze the entire DDR system, thereby improving the simulation and analysis efficiency of the DDR system.
[0089] Based on the first embodiment of the simulation and analysis device applied to the DDR system of the present application, a second embodiment of the simulation and analysis device applied to the DDR system of the present application is proposed.
[0090] In this embodiment, the parameter extraction module 501 is also used to export package routing information from a package design file and extract package target parameters from the package routing information when a simulation instruction is received; export PCB routing information from a PCB design file and extract PCB target parameters from the PCB routing information.
[0091] Furthermore, in the parameter extraction module 501, the package target parameters include the total package length, the package fanout area line length and the package breakout area line length, and the PCB target parameters include the total PCB length, the PCB breakout area line length and the PCB routing layer.
[0092] Furthermore, in the sample simulation module 502, the sample DDR channels include the channel with the longest total routing of the package, the channel with the longest routing in the neck area of the package, and the channel with the longest routing in each layer of the PCB.
[0093] Furthermore, the data calculation module 503 is also used to perform weighted fitting on the target parameters according to the error between the sample eye diagram data and the design target to obtain an eye diagram data calculation formula; calculate the eye diagram data corresponding to all DDR channels in the DDR system according to the eye diagram data calculation formula, and determine the DDR channel with the smallest eye diagram data in the DDR system as the worst DDR channel.
[0094] Furthermore, the simulation analysis module 504 is also used to determine that the DDR system meets the eye diagram index in the time domain if the worst DDR channel meets the design target; if the worst DDR channel does not meet the design target, determine that the DDR system does not meet the eye diagram index in the time domain.
[0095] Other embodiments or specific implementations of the simulation and analysis device applied to the DDR system of the present application can refer to the above-mentioned method embodiments and will not be described in detail here.
[0096] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.
[0097] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0098] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.
[0099] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A simulation analysis method applied to DDR system, It is characterized in that The method comprises the following steps: When receiving a simulation instruction, exporting target routing information from a design file, and extracting target parameters from the target routing information; Simulating a sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to a sample DDR signal in the sample DDR channel; constructing an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determining the worst DDR channel in the DDR system according to the eye diagram data calculation formula; The DDR system is simulated and analyzed based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain.
2. The simulation analysis method applied to the DDR system according to claim 1, It is characterized in that The design file includes a package design file and a PCB design file, the target parameters include package target parameters and PCB target parameters, and when a simulation instruction is received, the step of deriving target routing information from the design file and extracting target parameters from the target routing information includes: When receiving a simulation instruction, exporting package routing information from a package design file, and extracting package target parameters from the package routing information; PCB routing information is exported from a PCB design file, and PCB target parameters are extracted from the PCB routing information.
3. The simulation analysis method applied to the DDR system as claimed in claim 2, It is characterized in that The package target parameters include the total package length, the package fanout area line length and the package breakout area line length, and the PCB target parameters include the total PCB length, the PCB breakout area line length and the PCB routing layer.
4. The simulation analysis method applied to a DDR system according to claim 1, It is characterized in that The sample DDR channels include the channel with the longest total routing of the package, the channel with the longest routing in the neck area of the package, and the channel with the longest routing on each layer of the PCB.
5. The simulation analysis method applied to a DDR system as claimed in claim 1, It is characterized in that The step of constructing an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determining the worst DDR channel in the DDR system according to the eye diagram data calculation formula includes: Performing weighted fitting on the target parameters according to the error between the sample eye diagram data and the design target to obtain an eye diagram data calculation formula; The eye diagram data corresponding to all DDR channels in the DDR system are calculated according to the eye diagram data calculation formula, and the DDR channel with the smallest eye diagram data in the DDR system is determined as the worst DDR channel.
6. The simulation analysis method applied to a DDR system according to claim 1, It is characterized in that The step of simulating and analyzing the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram indicator in the time domain includes: If the worst DDR channel meets the design target, it is determined that the DDR system meets the eye diagram indicator in the time domain; If the worst DDR channel does not meet the design target, it is determined that the DDR system does not meet the eye diagram indicator in the time domain.
7. A simulation analysis device applied to a DDR system, It is characterized in that The simulation analysis device applied to the DDR system comprises: A parameter extraction module, used for deriving target routing information from a design file and extracting target parameters from the target routing information when receiving a simulation instruction; A sample simulation module, used for simulating a sample DDR channel selected from the DDR system to obtain sample eye diagram data corresponding to a sample DDR signal in the sample DDR channel; A data calculation module, configured to construct an eye diagram data calculation formula based on the target parameter and the sample eye diagram data, and determine the worst DDR channel in the DDR system according to the eye diagram data calculation formula; The simulation analysis module is used to perform simulation analysis on the DDR system based on the worst DDR channel to determine whether the DDR system meets the eye diagram index in the time domain.
8. A simulation analysis device applied to DDR system, It is characterized in that The device includes: a memory, a processor, and a simulation analysis program applied to a DDR system stored in the memory and executable on the processor, wherein the simulation analysis program applied to a DDR system is configured to implement the steps of a simulation analysis method applied to a DDR system as described in any one of claims 1 to 6.
9. A storage medium, It is characterized in that The storage medium is a computer-readable storage medium, on which is stored a simulation analysis program applied to a DDR system. When the simulation analysis program applied to a DDR system is executed by a processor, the steps of the simulation analysis method applied to a DDR system as described in any one of claims 1 to 6 are implemented.
10. A computer program product, It is characterized in that The computer program product comprises a simulation analysis program applied to a DDR system, and when the simulation analysis program applied to a DDR system is executed by a processor, the steps of the simulation analysis method applied to a DDR system as claimed in any one of claims 1 to 6 are implemented.