A method and device for implementing the initialization process of a control state machine

Abstract

The present invention relates to the technical field of integrated circuit design, and particularly relates to a method and device for implementing the initialization process of a control state machine. The control state machine is arranged in the programmable logic circuit of an FPGA chip. The method includes: after the power-on of the control state machine is completed, performing reset and firmware loading processing on the control state machine; after the firmware loading processing is completed, obtaining a target initialization instruction, and combining and independently running the initialization processes in the TX transmission direction and / or the RX reception direction according to the target initialization instruction. The above solution implements the control state machine and its initialization process in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, so that the initialization process of the control state machine can be flexibly combined and independently run according to different application scenarios and requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a method and device for implementing the initialization process of a control state machine. Background Art

[0002] In traditional ASIC (Application Specific Integrated Circuit) design, the SERDES (Serializer / Deserializer) control state machine usually completes the overall initialization process based on a specific protocol. It includes steps such as PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment), PLL (Phase-Locked Loop), RX equalization, and rate switching. These initialization steps are to ensure that the control state machine can correctly process data, implement the interface connection with the physical medium, and meet the requirements of specific communication protocols.

[0003] However, in the FPGA (Field-Programmable Gate Array) scenario, the application scenarios of the control state machine are more diverse, so it is required that the initialization process of the control state machine has higher flexibility. This means that it is necessary to be able to flexibly control the initialization processes of each lane such as PCS, PMA, and PLL, as well as the use of RX equalization and rate switching. This difference results in the need for a more flexible and programmable initialization process and control mechanism for SERDES in FPGA design to meet diverse application requirements. Summary of the Invention

[0004] In view of this, the present invention provides a method and device for implementing the initialization process of a control state machine to solve the problem of poor flexibility in the initialization process of the control state machine in the prior art.

[0005] In a first aspect, the present invention provides a method for implementing the initialization process of a control state machine, where the control state machine is set in the programmable logic circuit of an FPGA chip, and the method includes:

[0006] After the control state machine is powered on and completed, perform a reset and firmware loading process on the control state machine;

[0007] After the firmware loading process is completed, obtain the target initialization instruction, and combine and independently execute the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction according to the target initialization instruction; the initialization process in the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization, and transmission rate switching; the initialization process in the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation, and reception rate switching.

[0008] The above solution realizes the control state machine and its initialization process in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, which helps to optimize the allocation and utilization of hardware resources and reduce resource waste.

[0009] In an optional implementation manner, after the control state machine is powered on, performing a reset and firmware loading process on the control state machine includes:

[0010] Power on the control state machine for digital power and analog power;

[0011] After the power-on is completed, perform a reset process on the control state machine to make the control state machine in a silent state;

[0012] After the reset is completed, perform a release reset process on the control state machine and perform a firmware loading process.

[0013] In an optional implementation manner, when the target initialization instruction indicates to automatically execute the initialization process in the order of the process, then the combining and independently executing the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction according to the target initialization instruction includes:

[0014] In the initialization process in the TX transmission direction, sequentially execute the PLL initialization, the TX PMA initialization, the TX PCS initialization, and the transmission rate switching, and,

[0015] In the initialization process in the RX reception direction, sequentially execute the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation, and the reception rate switching.

[0016] In an optional implementation manner, the sequentially executing the PLL initialization, the TX PMA initialization, the TX PCS initialization, and the transmission rate switching in the initialization process in the TX transmission direction includes:

[0017] Release the PLL phase-locked loop reset and configure the registers of the PLL phase-locked loop through the APB interface to perform the PLL initialization;

[0018] After the PLL initialization is completed, give a lock signal through the PLL phase-locked loop, release the TX PMA lane reset, and configure the corresponding bit width and associated clock to perform the TX PMA initialization;

[0019] After the associated clock is stable, release the TX PCS lane reset and adapt to the corresponding protocol according to the register configuration to perform the TX PCS initialization;

[0020] After the TX PCS initialization is completed, reset the TX PCS reset and TX PMA reset, reconfigure the registers, and re-execute the TX PMA initialization and the TX PCS initialization to perform the transmission rate switching.

[0021] In an optional implementation manner, in the initialization process in the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation, and the receiving rate switching are sequentially performed, including:

[0022] Release the RX PMA reset and perform the RX PMA initialization according to the register configuration;

[0023] After the RX PMA initialization is completed, wait for the RX-side clock to be stable, and use rxX_data_valid as the indication signal to perform the clock verification;

[0024] After the clock verification is completed, release the RX PCS reset and perform the RX PCS initialization according to the APB configuration value;

[0025] After the RX PCS initialization is completed and it is determined to be the target high-speed scenario, initiate a handshake process and perform the EQ operation;

[0026] After the EQ operation is completed, reset the RX PCS reset and RX PMA reset, reconfigure the registers, and re-execute the RX PCS initialization and the EQ operation to perform the receiving rate switching.

[0027] In an optional implementation manner, when the target initialization instruction indicates to combine or independently execute the target initialization process, then the initialization process in the TX transmission direction and / or the initialization process in the RX receiving direction are combined and independently run according to the target initialization instruction, including:

[0028] When the target initialization instruction indicates to execute the PCS and PMA initialization processes in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed;

[0029] When the target initialization instruction indicates to execute the unidirectional high-speed TX interface initialization, the respective initialization processes in the TX transmission direction are executed in sequence;

[0030] When the target initialization instruction indicates to independently execute the initialization in the TX transmission direction and the RX reception direction based on different protocols, the respective initialization processes in the TX transmission direction and the respective initialization processes in the RX reception direction are independently executed at different rates;

[0031] When the target initialization instruction indicates separate initialization under PCS exception, the TX PCS initialization in the TX transmission direction is independently executed, and the RX PCS initialization in the RX reception direction is independently executed;

[0032] When the target initialization instruction indicates PMA separate initialization, the TX PMA initialization in the TX transmission direction is independently executed, and the RX PMA initialization in the RX reception direction is independently executed;

[0033] When the target initialization instruction indicates PLL separate initialization, the PLL initialization in the TX transmission direction is independently executed.

[0034] In a second aspect, the present invention provides a device for implementing the initialization process of a control state machine. The control state machine is set in the programmable logic circuit of an FPGA chip. The device includes:

[0035] A reset and firmware loading module, configured to perform reset and firmware loading processing on the control state machine after the control state machine is powered on;

[0036] A combination and independent operation module, configured to obtain a target initialization instruction after the firmware loading process is completed, and perform combination and independent operation on the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction according to the target initialization instruction; the initialization process in the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization, and transmission rate switching; the initialization process in the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation, and reception rate switching.

[0037] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to execute a method for implementing the initialization process of a control state machine according to the first aspect or any corresponding embodiment thereof.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute a method for implementing the initialization process of a control state machine according to the first aspect or any corresponding embodiment thereof.

[0039] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute a method for implementing the initialization process of a control state machine according to the first aspect or any corresponding embodiment thereof.

[0040] The technical solution provided by the present invention may include the following beneficial effects:

[0041] The present invention implements a control state machine and its initialization process in the programmable logic circuit of an FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, so that the initialization process of the control state machine can be compatible with the initialization process requirements under various different protocols, which helps to optimize the allocation and utilization of hardware resources and reduce resource waste. By subdividing the initialization process into multiple independently operable steps and allowing them to be combined as needed, the present invention can significantly accelerate the entire initialization process. The initialization process of the control state machine can be flexibly combined and independently operated according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 is a schematic diagram of the architecture in which a control state machine is integrated inside a SerDes IP in the ASIC design according to an embodiment of the present invention;

[0044] Figure 2 is a flowchart of a method for implementing the initialization process of a control state machine according to an embodiment of the present invention;

[0045] Figure 3 Schematic diagram of a SERDES control state machine architecture based on FPGA characteristics according to an embodiment of the present invention;

[0046] Figure 4 Flowchart of another method for implementing the initialization process of a control state machine according to an embodiment of the present invention;

[0047] Figure 5 Flowchart of yet another method for implementing the initialization process of a control state machine according to an embodiment of the present invention;

[0048] Figure 6 Schematic diagram of initializing a TX PCS lane according to an embodiment of the present invention;

[0049] Figure 7 Schematic diagram of an RX EQ process in a target high-speed scenario according to an embodiment of the present invention;

[0050] Figure 8 Block diagram of a device for implementing the initialization process of a control state machine according to an embodiment of the present invention;

[0051] Figure 9 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Specific embodiments

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] It should be noted that in ASIC design, due to the specific requirements of different communication protocols (such as low-speed Ethernet, PCIe, etc.) for the physical coding sublayer (PCS), the PCS is protocol-customized. This design approach results in the initialization state machine associated with the PCS also needing to vary according to the protocol. For example Figure 1As shown in the figure, in order to optimize the chip area and improve the user experience, the control state machine in the above ASIC design is often integrated inside the SerDes IP. Among them, RX represents the receiving end, TX represents the transmitting end, and PLL represents the phase-locked loop. In the present invention, the control state machine of PCS+PMA (physical medium attachment) is separated from the hard IP and instead soft logic (such as the programmable logic of an FPGA) is used for processing. The soft logic can be repeatedly modified as needed to adapt to different protocols or application scenarios, thereby improving the flexibility and response speed of the system. By implementing the control state machine with soft logic, system developers can more easily adjust and optimize the initialization process without relying on a fixed hardware design.

[0054] According to an embodiment of the present invention, there is provided an embodiment of a method for implementing the initialization process of a control state machine. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0055] In this embodiment, there is provided a method for implementing the initialization process of a control state machine, and the control state machine is set in the programmable logic circuit of an FPGA chip. Figure 2 It is a flowchart of a method for implementing the initialization process of a control state machine according to an embodiment of the present invention. As Figure 2 shown, the process includes the following steps:

[0056] Step S201, after the power-on of the control state machine is completed, perform a reset and firmware loading process on the control state machine.

[0057] Further, please refer to Figure 3 the schematic diagram of the SERDES control state machine architecture based on the FPGA characteristics shown. In this embodiment, the control state machine is separated from the hard IP and instead soft logic (such as the programmable logic of an FPGA) is used for processing. By implementing the control state machine with soft logic, system developers can more easily adjust and optimize the initialization process without relying on a fixed hardware design. In this embodiment, after the FPGA chip is powered on, first, the control state machine (i.e., the SERDES control state machine) needs to be reset, and during the reset process, ensure that the control state machine starts from a known initial state and clears any potential error states. After the reset is completed, this embodiment will load the firmware required by the control state machine, and the firmware can include the program code required for initialization and operation control.

[0058] Step S202: After the firmware loading process is completed, obtain the target initialization instruction, and combine and independently execute the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction according to the target initialization instruction; the initialization process in the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization, and transmission rate switching; the initialization process in the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation, and reception rate switching.

[0059] Further, after the firmware is loaded, the system obtains the target initialization instruction. The target initialization instruction defines the specific initialization tasks that the control state machine needs to execute. In this embodiment, according to the initialization instruction, multiple steps in the transmission (TX) and reception (RX) directions are initialized respectively, including PLL configuration, PMA initialization, PCS initialization, rate switching, clock verification, and EQ operation, etc. These steps can be combined or executed independently to ensure the correct initialization and operation of the system. Among them, PLL initialization: Configure the Phase-Locked Loop (PLL) to generate the required clock frequency to ensure the correct timing of the transmitted signal.

[0060] Among them, PLL initialization means: Configure the Phase-Locked Loop (PLL) to generate the required clock frequency to ensure the correct timing of the transmitted signal.

[0061] TX PMA initialization means: Initialize the Transmitter Physical Medium Attachment (TX PMA), which is responsible for encoding the transmitted data and preparing it for transmission.

[0062] TX PCS initialization means: Initialize the Transmitter Physical Coding Sublayer (TX PCS) to perform physical layer coding of the data.

[0063] Transmission rate switching means: Switch the transmission rate as needed to match the requirements of the target communication protocol.

[0064] RX PMA initialization means: Initialize the Receiver Physical Medium Attachment (RX PMA) to process the received data and decode it.

[0065] Clock verification means: Verify whether the clock signal at the receiving end is stable and synchronized.

[0066] RX PCS initialization means: Initialize the Receiver Physical Coding Sublayer (RX PCS) to decode the received data.

[0067] EQ operation means: Perform Equalization (EQ) operation to optimize the quality of the received signal.

[0068] Receiving rate switching means: switching the receiving rate as needed to match the requirements of the target communication protocol.

[0069] In summary, in this embodiment, the control state machine and its initialization process are implemented in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, enabling the initialization process of the control state machine to be compatible with the initialization process requirements under various different protocols, helping to optimize the allocation and utilization of hardware resources, and reducing resource waste. By subdividing the initialization process into multiple independently executable steps and allowing them to be combined as needed in this embodiment, the entire initialization process can be significantly accelerated. The initialization process of the control state machine can be flexibly combined and independently run according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed.

[0070] In this embodiment, another method for implementing the initialization process of the control state machine is provided. The control state machine is set in the programmable logic circuit of the FPGA chip. Figure 4 It is a flowchart of another method for implementing the initialization process of the control state machine according to an embodiment of the present invention. As Figure 4 shown, the process includes the following steps:

[0071] Step S401, power on the control state machine for digital power and analog power.

[0072] Further, please refer to Figure 5 the flowchart of yet another method for implementing the initialization process of the control state machine shown. Figure 5 The control state machine in [[ ]] is implemented by the soft logic of the FPGA. Since it is implemented by soft logic, Figure 5 each step in [[ ]] can be disassembled and combined. Figure 5 The left side of [[ ]] includes steps 1 to 4.8. Among them, step 1 is: power on the entire chip system, and the SERDES completes the power on for digital power and analog power. That is, in this embodiment, the entire FPGA chip system is powered on, which includes the digital and analog circuit parts of the SERDES control state machine. Ensure that all parts of the SERDES control state machine obtain the necessary power supply.

[0073] Step S402, after the power on is completed, perform a reset process on the control state machine to make the control state machine in a silent state.

[0074] Further, as Figure 5As shown, step 2 is: the por_rst of the SERDES control state machine is reset to ensure that the SERDES control state machine is silent. That is to say, after the power-on is completed, in this embodiment, the Power-On Reset (POR) signal is used to reset the SERDES control state machine to its initial state, ensuring that it is in a known state after being fully powered on. At this time, the SERDES control state machine is in the reset state and does not perform any operations.

[0075] Step S403, after the reset is completed, perform a release reset process on the control state machine and perform a firmware loading process.

[0076] Further, as Figure 5 shown, step 3 is: release the reset of the por_rst of the SERDES control state machine, and the SERDES control state machine performs a fireware loading process. That is to say, once the system is stable, the POR reset is released. At this time, the reset signal is removed, and the SERDES control state machine starts to execute the firmware loading process. The SERDES control state machine loads and executes the necessary firmware (fireware) to prepare for subsequent initialization operations.

[0077] Step S404, after the firmware loading process is completed, obtain the target initialization instruction.

[0078] Step S405, when the target initialization instruction indicates to automatically execute the initialization process in the process order, in the initialization process in the TX transmission direction, sequentially execute the PLL initialization, the TX PMA initialization, the TX PCS initialization, and the transmission rate switching, and,

[0079] in the initialization process in the RX reception direction, sequentially execute the RX PMA initialization, the clock verification, the RXPCS initialization, the EQ operation, and the reception rate switching.

[0080] In some alternative embodiments, step S405 includes:

[0081] In the initialization process in the TX transmission direction, release the PLL phase-locked loop reset, and configure the registers of the PLL phase-locked loop through the APB interface to perform the PLL initialization;

[0082] After the PLL initialization is completed, give a lock signal through the PLL phase-locked loop, and release the TX PMA lanereset, and configure the corresponding bit width and the lane clock to perform the TX PMA initialization;

[0083] After the associated clock is stable, release the TX PCS lane reset and adapt it to the corresponding protocol according to the register configuration to perform the TX PCS initialization;

[0084] After the TX PCS initialization is completed, reset the TX PCS reset and TX PMA reset, reconfigure the registers, and re - execute the TX PMA initialization and the TX PCS initialization to perform the transmission rate switching.

[0085] In some alternative embodiments, step S405 includes:

[0086] In the initialization process of the RX receiving direction, release the RX PMA reset and perform the RX PMA initialization according to the register configuration;

[0087] After the RX PMA initialization is completed, wait for the RX - side clock to be stable, and use rxX_data_valid as the indication signal to perform the clock verification;

[0088] After the clock verification is completed, release the RX PCS reset and perform the RX PCS initialization according to the APB configuration value;

[0089] After the RX PCS initialization is completed and it is determined to be the target high - speed scenario, initiate the handshake process and perform the EQ operation;

[0090] After the EQ operation is completed, reset the RX PCS reset and RX PMA reset, reconfigure the registers, and re - execute the RX PCS initialization and the EQ operation to perform the receiving rate switching.

[0091] Further, as Figure 5 shown, step 4 is: Detailed process breakdown of the TX transmission direction:

[0092] 4.1 After the firmware loading of the SERDES control state machine is completed, release the PLL reset of the control state machine, and the soft logic configures the registers of the PLL through the APB interface to configure the corresponding frequency points. That is to say, in this embodiment, the firmware (fireware) loading of the SERDES control state machine is first completed. The firmware contains the necessary codes and configuration information required for the initialization of the Serdes module. Subsequently, the reset of the PLL (Phase - Locked Loop) is released. The PLL is a key component in the SERDES control state machine for generating a stable clock signal. Through the APB (Advanced Peripheral Bus) interface, the soft logic configures the registers of the PLL to set the required frequency points, thereby ensuring that the TX path can generate a clock signal with the correct frequency.

[0093] 4.2 After the configuration is completed, the PLL gives a lock signal, indicating that the PLL has completed initialization. That is, after the configuration is completed, the PLL will emit a lock signal, indicating that it has successfully locked on the specified frequency point and is ready to provide a stable clock signal for the TX path.

[0094] 4.3 The TX PMA lane reset is released. The TX PMA is configured with the corresponding bit width according to the initial value given by the APB and gives the corresponding clock along the path. That is, in this embodiment, the lane reset of the physical media adaptation layer (PMA) in the TX transmission direction is released. The PMA is a component responsible for signal transmission and reception at the physical layer. Then, the TX PMA is configured with the corresponding bit width according to the initial value provided by the APB interface and generates the corresponding clock along the path. The clock along the path is a clock signal transmitted together with the data signal and is used for the receiving end to synchronize and recover the data.

[0095] 4.4 The clock along the TX path is stable. That is, ensure that the clock signal along the path provided by the PMA is stable and meets the system requirements.

[0096] 4.5 The PMA gives an indication to enable the TX link (TX PMA done). That is, when the configuration of the TX PMA is completed and the clock along the path is stable, the PMA will emit a TX PMA done signal, indicating that the TX link is ready to send data.

[0097] 4.6 The TX PCS lane reset in the transmission direction is released. The PCS is adapted to the corresponding protocol according to the register configuration. That is, in this embodiment, the lane reset of the physical coding sublayer (PCS) in the TX transmission direction is released. The PCS is responsible for converting parallel data into serial data and performing encoding and error detection, etc. Then, the PCS is adapted to the corresponding communication protocol according to the register configuration to ensure that the data sent conforms to the format and protocol expected by the receiving end.

[0098] 4.7 Giving TX PCS done indicates that the reset initialization process in the PCS direction of TX is completed. That is, when the PCS completes initialization and is ready to send data, it will emit a TX PCS done signal, indicating that the reset initialization process in the PCS direction of TX has been completed.

[0099] 4.8 If the transmission rate needs to be switched in the TX transmission direction.

[0100] 4.8.1 The system resets the PCS reset and PMA reset in the TX transmission direction. That is, if the rate in the TX transmission direction needs to be changed, the system needs to reset the PCS and PMA resets in the TX transmission direction to avoid interference during the rate switching process.

[0101] 4.8.2. Modify the PCS and PMA registers via the APB. That is, in this embodiment, the register settings of the PCS and PMA are modified through the APB interface to meet the new rate requirements.

[0102] 4.8.3. Initialize and complete the process from step 4.3 to step 4.7 again. That is, re-execute the initialization process from step 4.3 to step 4.7 to ensure that the TX path can be correctly initialized and operate stably at the new rate.

[0103] Further, as Figure 5 shown, step 5 is the detailed process breakdown of the RX receiving direction:

[0104] 5.1. Release the RX PMA reset, and the PMA initializes the lanes of the PMA according to the register configuration values. That is, in this embodiment, the reset of the Physical Medium Attachment (PMA) layer at the RX side is first released. The PMA is the underlying physical interface responsible for signal reception and transmission and is directly connected to the physical medium (such as optical fiber, copper wire). This step allows the PMA to start initializing its lanes (channels) according to the register configuration values, including setting parameters such as signal strength and equalizer.

[0105] 5.2. Wait for the RX side clock issue, with rxX_data_valid as the indication signal. That is, in this embodiment, wait for the RX receiving end clock to stabilize and use the rxX_data_valid signal as an indication of clock stability. Ensure that the clock has stabilized before data starts to be effectively received, and then correctly receive the data.

[0106] 5.3. The PMA gives RX PMA reset done. That is, in this embodiment, after the PMA completes the initialization, it will issue a signal (such as RX_PMA_RESET_DONE) indicating that the PMA is ready to receive data. RX_PMA_RESET_DONE is the signal for continuing the subsequent process, indicating that the PMA layer has been initialized and can start normal operation.

[0107] 5.4. Release the RX PCS reset and initialize the PCS according to the current APB configuration values. That is, in this embodiment, release the reset of the Physical Coding Sublayer (PCS) in the RX receiving direction and initialize the PCS according to the current APB (Advanced Peripheral Bus) configuration values.

[0108] 5.5. If it is determined to be a high-speed scenario (>10 Gbps), initiate the handshake process and trigger the PMA to perform an EQ once. That is, if the system is operating in a high-speed scenario (such as >10 Gbps), then initiate the handshake process and trigger the PMA to perform an equalization (EQ operation) process. The handshake process is used to confirm that the parameters at both ends of the link match, while EQ is used to adjust the signal quality to compensate for losses in the channel and ensure that data can be correctly received.

[0109] 5.6. After the EQ operation is completed, the PCS gives a reset done. After the EQ operation is completed, the PCS will issue a signal (such as PCS_RESET_DONE), indicating that the PCS initialization is completed and ready to process data. This marks that both the underlying and intermediate layers of the receive path have been initialized and can start receiving and processing data.

[0110] 5.7. If the user's first EQ operation does not meet the requirements, initiate another EQ operation. That is, if the user believes that the result of the first EQ operation does not meet the requirements, an additional EQ operation can be initiated, allowing the system to perform multiple EQ adjustments as needed to optimize the signal quality.

[0111] 5.8. If the RX receive direction needs to perform a rate switch:

[0112] 5.8.1. The system resets the PCS reset and PMA reset in the TX transmit direction. That is, if a rate switch is needed in the RX receive direction, the system first resets the PCS and PMA resets in the TX transmit direction to avoid interference during the rate switch process.

[0113] 5.8.2. The user reconfigures the registers of the PCS and PMA through the APB. That is, the user modifies the register configuration of the PCS and PMA through the APB to adapt to the new rate.

[0114] 5.8.3. Initialize and complete steps 5.4 -> 5.6 again. That is, re-execute steps 5.4 to 5.6 to complete the initialization and stabilization process of the PCS and PMA at the new rate.

[0115] In summary, to achieve the effects of automation and flexibility, in this embodiment, an initialized reset signal is provided to trigger the entire initialization process, which will sequentially execute all necessary initialization actions in the current scenario. This method greatly simplifies the user operation and improves the automation level of the system. It includes: designing a global reset signal that, when triggered, starts a preset initialization process; the initialization process contains multiple sub-processes, and each sub-process corresponds to the initialization of one or more hardware components; the sub-processes are executed in a certain order to ensure that all necessary initialization actions are correctly executed; at the end of the process, the system will send a signal indicating that the initialization is complete to inform the user that all initialization actions have been completed.

[0116] Step S406: When the target initialization instruction indicates to combine or independently execute the target initialization process, the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction is combined or independently run.

[0117] In some optional implementation manners, step S406 includes:

[0118] When the target initialization instruction indicates to execute the PCS and PMA initialization processes in a low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed.

[0119] When the target initialization instruction indicates to execute the one-way high-speed TX interface initialization, the respective initialization processes in the TX transmission direction are sequentially executed.

[0120] When the target initialization instruction indicates to independently execute the initialization in the TX transmission direction and the RX reception direction based on different protocols, the respective initialization processes in the TX transmission direction and the respective initialization processes in the RX reception direction are independently executed at different rates.

[0121] When the target initialization instruction indicates a separate initialization under PCS exception, the TX PCS initialization in the TX transmission direction is independently executed, and the RX PCS initialization in the RX reception direction is independently executed.

[0122] When the target initialization instruction indicates a separate PMA initialization, the TX PMA initialization in the TX transmission direction is independently executed, and the RX PMA initialization in the RX reception direction is independently executed.

[0123] When the target initialization instruction indicates a separate PLL initialization, the PLL initialization in the TX transmission direction is independently executed.

[0124] Furthermore, this embodiment provides a flexible configuration and usage method for different components (such as PCS, PMA, PLL, EQ, etc.) in a Serdes (Serializer / Deserializer) system. It includes:

[0125] 1.1 If it is a low-speed PCS + PMA, the user can bypass the EQ-related process:

[0126] In a low-speed communication scenario, since the signal attenuation and distortion are relatively small, complex equalization (EQ) operations may not be required. Therefore, the system allows the user to bypass the processes related to EQ operations and directly initialize the PCS and PMA. This can reduce unnecessary processing time and improve system efficiency.

[0127] 1.2 If the user only wants to use the TX transmission direction for a high-speed interface, the user only needs to go through the TX transmission direction initialization process:

[0128] In some application scenarios, the user may only need to use the TX transmission direction of the Serdes for high-speed data transmission and not the RX reception direction. In this case, the user can choose to only execute the initialization process of the TX transmission direction, including TX PCS, TX PMA, and related clock and signal configurations. This can save resources and focus on the performance optimization of the TX transmission direction.

[0129] 1.3 If the user wants the TX and RX reception directions to follow different protocols, the TX and RX can be initialized separately with different rates:

[0130] The SERDES control state machine supports independent configuration of the TX transmission direction and the RX reception direction, including protocols and rates. That is, the user can select different protocols and rates for the TX transmission direction and the RX reception direction according to needs. During the initialization process, the user can separately configure the PCS layer of the TX transmission direction and the RX reception direction to adapt to different protocol requirements and set the corresponding rates, enabling the SERDES control state machine to be widely applied in various communication scenarios.

[0131] 1.4 If only the PCS is abnormal, the PCS can be initialized separately:

[0132] During the operation of the SERDES control state machine, if an abnormality (such as data error, loss of synchronization, etc.) is detected in the PCS layer, the user can choose to only re-initialize the PCS layer without resetting the entire SERDES control state machine. This can quickly restore the normal function of the PCS layer while keeping the states of other components (such as PMA, PLL, etc.) unchanged. This local initialization method helps to reduce the system recovery time and improve the system stability.

[0133] 1.5 If PCS is not required, the PMA initialization process can be performed separately:

[0134] If the user may not need to use the PCS layer for protocol processing, but directly serialize and deserialize data through the PMA layer. In this case, this embodiment can only execute the initialization process of the PMA, configure the corresponding clock and signal parameters, thereby simplifying the system structure and reducing power consumption and cost.

[0135] 1.6 If only the PLL is used, the PLL initialization process can be performed separately to obtain a clock from the PLL:

[0136] The PLL (Phase Locked Loop) is a key component in the SERDES control state machine for generating a stable clock signal. If the user only needs to use the PLL to provide a clock signal without data transmission, then only the PLL initialization process can be executed. During the initialization process, the user can configure the parameters of the PLL (such as frequency, phase, etc.) to generate a clock signal that meets the requirements. In this way, the PLL can be used as an independent clock source to provide a stable clock reference for other system components.

[0137] Furthermore, this embodiment can implement a flexible combination of block diagrams and component resets. The system allows the user to flexibly combine the components in the block diagram according to needs and perform a reset operation on any component. This flexibility enables the system to adapt to a variety of different application scenarios and user requirements. Exemplarily, if the user wishes to initialize only a certain lane of the PCS in the TX transmission direction, please refer to Figure 6 the schematic diagram showing the initialization of the TX PCS lane. In Figure 6 it, the user can choose to trigger only the initialization process related to the TX PCS lane. If the user wishes to perform an EQ (equalization) operation on the RX reception direction in a target high-speed scenario, please refer to Figure 7 the schematic diagram showing the RX EQ process in the target high-speed scenario. In Figure 7 it, the user can directly trigger the EQ operation process without performing the initialization of the entire RX path.

[0138] In summary, in this embodiment, the control state machine and its initialization process are implemented in the programmable logic circuit of the FPGA chip, making full use of the high flexibility and reconfigurability of the FPGA, enabling the initialization process of the control state machine to be compatible with the initialization process requirements under various different protocols, helping to optimize the allocation and utilization of hardware resources, and reducing resource waste. In this embodiment, by subdividing the initialization process into multiple independently operable steps and allowing them to be combined as needed, the entire initialization process can be significantly accelerated. The initialization process of the control state machine can be flexibly combined and independently operated according to different application scenarios and requirements. This parallel processing or on-demand execution method reduces unnecessary waiting time and improves the system startup speed.

[0139] In this embodiment, a device for implementing the initialization process of the control state machine is also provided. This device is used to implement the above-mentioned embodiment and preferred implementation manners, and those that have been described will not be repeated here. As used hereinafter, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0140] This embodiment provides a device for implementing the initialization process of the control state machine. The control state machine is set in the programmable logic circuit of the FPGA chip, as Figure 8 shown, including:

[0141] A reset and firmware loading module 801, configured to perform a reset and firmware loading process on the control state machine after the power-on of the control state machine is completed;

[0142] A combination and independent operation module 802, configured to obtain a target initialization instruction after the firmware loading process is completed, and perform combination and independent operation on the initialization process in the TX transmission direction and / or the initialization process in the RX reception direction according to the target initialization instruction; the initialization process in the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization, and transmission rate switching; the initialization process in the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation, and reception rate switching.

[0143] In some optional implementation manners, the reset and firmware loading module 801 is further configured to:

[0144] Power on the digital power and analog power of the control state machine;

[0145] After the power-on is completed, perform a reset process on the control state machine to make the control state machine in a silent state;

[0146] After the reset is completed, perform a release reset process on the control state machine and a firmware loading process.

[0147] In some alternative embodiments, when the target initialization instruction indicates to automatically execute the initialization process in the process sequence, the combined and independent operation module 802 is further configured to:

[0148] In the initialization process in the TX transmission direction, sequentially execute the PLL initialization, the TX PMA initialization, the TX PCS initialization, and the transmission rate switching, and,

[0149] In the initialization process in the RX reception direction, sequentially execute the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation, and the reception rate switching.

[0150] In some alternative embodiments, the combined and independent operation module 802 is further configured to:

[0151] Release the PLL phase-locked loop reset, and configure the registers of the PLL phase-locked loop through the APB interface to perform the PLL initialization;

[0152] After the PLL initialization is completed, give a lock signal through the PLL phase-locked loop, and release the TX PMA lanereset, configure the corresponding bit width and the associated clock to perform the TX PMA initialization;

[0153] After the associated clock is stable, release the TX PCS lane reset, and adapt to the corresponding protocol according to the register configuration to perform the TX PCS initialization;

[0154] After the TX PCS initialization is completed, reset the TX PCSreset and the TXPMA reset, reconfigure the registers, and re-execute the TX PMA initialization and the TX PCS initialization to perform the transmission rate switching.

[0155] In some alternative embodiments, the combined and independent operation module 802 is further configured to:

[0156] Release the RX PMA reset, and perform the RX PMA initialization according to the register configuration;

[0157] After the RX PMA initialization is completed, wait for the RX-side clock to be stable, and use rxX_data_valid as the indication signal to perform the clock verification;

[0158] After the clock verification is completed, release the RX PCS reset, and perform the RX PCS initialization according to the APB configuration value;

[0159] After the initialization of the RX PCS is completed and it is determined to be the target high-speed scenario, a handshake process is initiated and the EQ operation is performed.

[0160] After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receive rate switching.

[0161] In some alternative embodiments, when the target initialization instruction indicates to perform the target initialization process in combination or independently, the combined and independent operation module 802 is further configured to:

[0162] When the target initialization instruction indicates to perform the PCS and PMA initialization processes in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are performed, the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are performed.

[0163] When the target initialization instruction indicates to perform the one-way high-speed TX interface initialization, the respective initialization processes in the TX transmission direction are sequentially performed.

[0164] When the target initialization instruction indicates to independently perform the initialization of the TX transmission direction and the RX reception direction based on different protocols, the respective initialization processes in the TX transmission direction and the respective initialization processes in the RX reception direction are independently performed at different rates.

[0165] When the target initialization instruction indicates the separate initialization under PCS exception, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed.

[0166] When the target initialization instruction indicates the separate initialization of PMA, the TX PMA initialization in the TX transmission direction is independently performed, and the RX PMA initialization in the RX reception direction is independently performed.

[0167] When the target initialization instruction indicates the separate initialization of PLL, the PLL initialization in the TX transmission direction is independently performed.

[0168] The further function descriptions of the above-mentioned respective modules and units are the same as those in the corresponding above-mentioned embodiments, and will not be elaborated here.

[0169] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention, as Figure 9As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting the components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 9 In the figure, a processor 10 is taken as an example.

[0170] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field programmable gate array, a generic array logic, or any combination thereof.

[0171] Among them, the memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0172] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0173] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memories.

[0174] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0175] Embodiments of the present invention also provide a computer-readable storage medium. The method according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0176] A part of the present invention can be applied as a computer program product, for example, computer program instructions. When executed by a computer, through the operation of the computer, the methods and / or technical solutions according to the present invention can be called or provided. Those skilled in the art should be able to understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0177] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the defined scope.

Claims

1. A method for implementing a control state machine initialization process, characterized in that: The control state machine is arranged in a programmable logic circuit of an FPGA chip, and the method comprises: After the control state machine is powered on, resetting and firmware loading processing is performed on the control state machine; After the firmware loading process is completed, a target initialization instruction is obtained, and the initialization process of the TX transmission direction and / or the initialization process of the RX reception direction are combined and independently operated according to the target initialization instruction; the initialization process of the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and transmission rate switching; the initialization process of the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and reception rate switching; When the target initialization instruction indicates that the initialization process is automatically executed according to the process sequence, the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently run according to the target initialization instruction, including: In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, and, In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence; When the target initialization instruction indicates to combine or independently execute the target initialization process, the initialization process of the TX sending direction and / or the initialization process of the RX receiving direction are combined and independently executed according to the target initialization instruction, including: When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed; When the target initialization instruction indicates to perform unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence; When the target initialization instruction indicates that the initialization of the TX transmission direction and the RX reception direction are to be performed independently based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are to be performed independently at different rates; When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed; When the target initialization instruction indicates that the PMA is initialized separately, the TX PMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently; When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

2. The method according to claim 1, characterized in that After the control state machine is powered on, resetting and firmware loading processing are performed on the control state machine, including: Powering on the control state machine digitally and analogly; After power-on is completed, resetting the control state machine to put the control state machine in a silent state; After the reset is completed, the control state machine is released from the reset process and the firmware is loaded.

3. The method according to claim 1, characterized in that In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, including: Release the PLL phase-locked loop reset, and configure the register of the PLL phase-locked loop through the APB interface to perform the PLL initialization; After the PLL initialization is completed, a lock signal is given through the PLL phase-locked loop, and the TX PMA lanereset is released, and the corresponding bit width and lane clock are configured to perform the TX PMA initialization; After the lane clock is stable, the TX PCS lane reset is released, and the corresponding protocol is adapted according to the register configuration to perform the TX PCS initialization; After the TX PCS initialization is completed, TX PCSreset and TXPMA reset are reset, registers are reconfigured, and the TX PMA initialization and the TX PCS initialization are re-executed to perform the transmission rate switching.

4. The method according to claim 1, characterized in that: In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence, including: Release RX PMA reset and perform the RX PMA initialization according to the register configuration; After the RX PMA initialization is completed, wait for the RX side clock to be stable, and use rxX_data_valid as an indication signal to perform the clock verification; After the clock verification is completed, the RX PCS reset is released, and the RX PCS is initialized according to the APB configuration value; After the RX PCS initialization is completed and it is determined to be a target high-speed scenario, a handshake process is initiated and the EQ operation is performed; After the EQ operation is completed, the RX PCS reset and the RX PMA reset are reset, the registers are reconfigured, and the RX PCS initialization and the EQ operation are re-executed to perform the receiving rate switching.

5. A device for implementing a control state machine initialization process, characterized in that: The control state machine is arranged in a programmable logic circuit of an FPGA chip, and the device comprises: A reset and firmware loading module, used for resetting and loading firmware on the control state machine after the control state machine is powered on; A combination and independent operation module, used for obtaining a target initialization instruction after the firmware loading process is completed, and combining and independently operating the initialization process of the TX transmission direction and / or the initialization process of the RX reception direction according to the target initialization instruction; the initialization process of the TX transmission direction includes at least one of PLL initialization, TX PMA initialization, TX PCS initialization and transmission rate switching; the initialization process of the RX reception direction includes at least one of RX PMA initialization, clock verification, RX PCS initialization, EQ operation and reception rate switching; When the target initialization instruction indicates to automatically execute the initialization process according to the process sequence, the combination and independent operation module is further used to: In the initialization process of the TX transmission direction, the PLL initialization, the TX PMA initialization, the TX PCS initialization and the transmission rate switching are performed in sequence, and, In the initialization process of the RX receiving direction, the RX PMA initialization, the clock verification, the RX PCS initialization, the EQ operation and the receiving rate switching are performed in sequence; When the target initialization instruction indicates to execute the target initialization process in combination or independently, the combination and independent operation module is further used to: When the target initialization instruction indicates to execute the PCS and PMA initialization process in the low-speed scenario, the TX PMA initialization and the TX PCS initialization in the TX transmission direction are executed, and the EQ operation is skipped, and the RX PMA initialization and the RX PCS initialization are executed; When the target initialization instruction indicates to perform unidirectional high-speed TX interface initialization, each initialization process of the TX transmission direction is executed in sequence; When the target initialization instruction indicates that the initialization of the TX transmission direction and the RX reception direction are to be performed independently based on different protocols, each initialization process of the TX transmission direction and each initialization process of the RX reception direction are to be performed independently at different rates; When the target initialization instruction indicates separate initialization under PCS abnormality, the TX PCS initialization in the TX transmission direction is independently performed, and the RX PCS initialization in the RX reception direction is independently performed; When the target initialization instruction indicates that the PMA is initialized separately, the TX PMA initialization in the TX transmission direction is performed independently, and the RX PMA initialization in the RX reception direction is performed independently; When the target initialization instruction instructs the PLL to be initialized independently, the PLL initialization in the TX transmission direction is performed independently.

6. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a method for implementing a control state machine initialization process as described in any one of claims 1 to 4 by executing the computer instructions.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a method for implementing a control state machine initialization process according to any one of claims 1 to 4.

8. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute a method for implementing an initialization process of a control state machine according to any one of claims 1 to 4.

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