A switching loss evaluation method and system based on semi-soft switching modulation technology

Abstract

The present invention discloses a switching loss evaluation method and system based on semi-soft switching modulation technology, and relates to the field of information technology. The present invention obtains the parasitic inductance parameters and buffer capacitance parameters of the device, establishes a resonant circuit working model, obtains the initial voltage waveform and the initial current waveform by solving the model, and calculates the corresponding voltage stress and current stress; optimizes the parasitic inductance parameters and buffer capacitance parameters of the device by using a genetic algorithm; adjusts the buffer circuit design according to the optimized device parameters, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the device parameters and buffer circuit design. Finally, semi-soft switching modulation simulation is performed, and a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed to determine the optimal design scheme of the device, effectively reducing the switching loss of the device and ensuring that the device operates within a safe working area.

Description

Technical Field

[0001] The invention belongs to the field of information technology, and in particular relates to a switching loss evaluation method and system based on semi-soft switching modulation technology. Background Art

[0002] SiC-MOSFET devices are silicon carbide metal oxide semiconductor field effect transistors, which are field effect transistors based on silicon carbide (SiC) semiconductor materials. During the semi-soft switching modulation process of SiC-MOSFET devices, due to the resonance effect between the device parasitic inductance and the buffer capacitor, large voltage spikes and current spikes are generated during the switching process, which increases the switching loss of the device.

[0003] There are parameter matching issues between the parasitic inductance and buffer capacitance of SiC-MOSFET devices. Different parameter combinations will lead to differences in the resonance process, which in turn affects the magnitude of the switching loss. Moreover, the voltage stress and current stress distribution during the resonance process are uneven, with high peak values, which also exacerbates the device loss. In addition, the balance between the optimization and performance of device parameters and buffer circuit design is a more complex issue. In addition, during the semi-soft switching modulation process, the switching speed of the device and the parameters of the drive circuit will also affect the resonance process, further increasing the difficulty of optimization. Therefore, there is an urgent need for a switching loss evaluation method and system based on semi-soft switching modulation technology to solve the defects of the prior art. Summary of the invention

[0004] The present invention aims to provide a switching loss evaluation method and system based on semi-soft switching modulation technology to solve the above technical problems. In the process of semi-soft switching modulation of SiC-MOSFET devices, the switching loss of SiC-MOSFET devices is evaluated by the resonant voltage and current between the parasitic inductance and the buffer capacitor, thereby optimizing the SiC-MOSFET device parameters and the buffer circuit design, effectively reducing the switching loss of SiC-MOSFET devices and improving the working performance of SiC-MOSFET devices.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a switching loss evaluation method based on a semi-soft switching modulation technology, comprising:

[0006] Obtaining parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device to be evaluated; constructing a resonant circuit working model of the SiC-MOSFET device according to the parasitic inductance parameters and buffer capacitance parameters, and solving the resonant circuit working model to obtain an initial resonant voltage waveform and an initial resonant current waveform;

[0007] Calculating the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judging whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress;

[0008] When the SiC-MOSFET device is in a safe working state, the total switching loss of the SiC-MOSFET device is determined according to the initial resonant voltage waveform and the initial resonant current waveform; taking minimizing the total switching loss as the objective function, the parasitic inductance parameter and the buffer capacitance parameter of the SiC-MOSFET device are optimized according to the genetic algorithm to obtain a first parasitic inductance parameter and a first buffer capacitance parameter;

[0009] Adjusting the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitor parameter to obtain a first resonant voltage waveform and a first resonant current waveform; performing frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimizing the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude;

[0010] Obtain the measured resonant voltage waveform, measured resonant current waveform and measured switching loss according to the optimized SiC-MOSFET device parameters and snubber circuit design;

[0011] Semi-soft switching modulation simulation is performed on the SiC-MOSFET device to obtain simulated switching loss, a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, the optimal design scheme of the SiC-MOSFET device is determined, and the switching loss evaluation of the SiC-MOSFET device is completed.

[0012] It can be understood that, compared with the prior art, the present invention obtains the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device, establishes a resonant circuit working model in the semi-soft switch modulation process, obtains the initial voltage waveform and initial current waveform in the resonance process by solving the model, calculates the voltage stress and current stress of the SiC-MOSFET device in the resonance process, and determines whether the device is in a safe working state. On this basis, the present invention uses a genetic algorithm to calculate the objective function of minimizing the total switching loss, and optimizes the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device. According to the optimized device parameters, the present invention adjusts the buffer circuit design, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the SiC-MOSFET device parameters and buffer circuit design. Finally, a semi-soft switch modulation simulation is performed to obtain the simulated switching loss, construct the temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, and determine the optimal design scheme of the SiC-MOSFET device. The present invention effectively reduces the switching loss of the SiC-MOSFET device and ensures that the device operates in a safe working area.

[0013] Accordingly, an embodiment of the present invention provides a switching loss evaluation system based on semi-soft switching modulation technology, including: a resonant waveform acquisition module, a working state judgment module, a parameter optimization module, a device optimization module, a measured data acquisition module and a switching loss evaluation module;

[0014] The resonant waveform acquisition module is used to acquire the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device to be evaluated; a resonant circuit working model of the SiC-MOSFET device is constructed according to the parasitic inductance parameters and buffer capacitance parameters, and the resonant circuit working model is solved to obtain an initial resonant voltage waveform and an initial resonant current waveform;

[0015] The working state judgment module is used to calculate the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judge whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress;

[0016] The parameter optimization module is used to determine the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform when the SiC-MOSFET device is in a safe working state; taking minimizing the total switching loss as the objective function, the parasitic inductance parameter and the buffer capacitance parameter of the SiC-MOSFET device are optimized according to the genetic algorithm to obtain the first parasitic inductance parameter and the first buffer capacitance parameter;

[0017] The device optimization module is used to adjust the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain a first resonant voltage waveform and a first resonant current waveform; perform frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimize the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude;

[0018] The measured data acquisition module is used to obtain the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the buffer circuit design;

[0019] The switching loss evaluation module is used to perform semi-soft switching modulation simulation on the SiC-MOSFET device, obtain simulated switching loss, construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, determine the optimal design scheme of the SiC-MOSFET device, and complete the switching loss evaluation of the SiC-MOSFET device.

[0020] It can be understood that the system obtains the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device, establishes the resonant circuit working model in the semi-soft switching modulation process, obtains the initial voltage waveform and initial current waveform in the resonance process by solving the model, calculates the voltage stress and current stress of the SiC-MOSFET device in the resonance process, and determines whether the device is in a safe working state. On this basis, the system uses a genetic algorithm to calculate the objective function of minimizing the total switching loss, optimizes the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device. According to the optimized device parameters, the system adjusts the buffer circuit design, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the SiC-MOSFET device parameters and buffer circuit design. Finally, a semi-soft switching modulation simulation is performed to obtain the simulated switching loss, construct the temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, and determine the optimal design scheme of the SiC-MOSFET device. The system effectively reduces the switching loss of the SiC-MOSFET device and ensures that the device works in a safe working area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 : A flow chart of the steps of a switching loss evaluation method based on a semi-soft switching modulation technology provided by an embodiment of the present invention;

[0022] Figure 2 : A structural schematic diagram of a switching loss evaluation system based on a semi-soft switching modulation technology provided by an embodiment of the present invention;

[0023] Among them, 201: resonant waveform acquisition module; 202: working state judgment module; 203: parameter optimization module; 204: device optimization module; 205: measured data acquisition module; 206: switching loss evaluation module. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Embodiment 1

[0026] Please refer to Figure 1 , is a flow chart of the steps of a switching loss evaluation method based on semi-soft switching modulation technology provided by an embodiment of the present invention, including steps S101 to S106.

[0027] Step S101: obtaining parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device to be evaluated; constructing a resonant circuit working model of the SiC-MOSFET device according to the parasitic inductance parameters and buffer capacitance parameters, and solving the resonant circuit working model to obtain an initial resonant voltage waveform and an initial resonant current waveform.

[0028] In this embodiment, the resonant circuit working model of the SiC-MOSFET device is constructed according to the parasitic inductance parameters and the buffer capacitance parameters, and the resonant circuit working model is solved to obtain the initial resonant voltage waveform and the initial resonant current waveform, specifically including:

[0029] The parasitic inductance parameters are sampled at high frequency to obtain a single-cycle waveform; according to the gradient descent algorithm, the single-cycle waveform and the buffer capacitor parameters are matched, and the calculation error of the parameter matching is judged by an adaptive threshold to obtain a parameter combination that meets the preset error requirement; a second-order ordinary differential equation is established according to the parameter combination, the second-order ordinary differential equation is frequency-domain transformed by Laplace transformation, and the characteristic root of the equation is obtained based on the frequency domain space obtained by the frequency domain transformation; the characteristic root of the equation is discretized according to the bilinear transformation to obtain the dynamic response data of the resonant circuit to construct the resonant circuit of the SiC-MOSFET device. Circuit working model; according to the resonant circuit working model, the dynamic response data of the resonant circuit is subjected to sliding average processing, and the high-frequency components of the smoothed dynamic response data of the resonant circuit are eliminated by a preset Chebyshev filter to obtain the initial resonant voltage waveform output by the Chebyshev filter; the initial resonant voltage waveform is subjected to a fifth-order Fourier series expansion to obtain a voltage spectrum; the voltage spectrum is converted to a time domain space based on a forward Euler formula to obtain a time domain current response; the time domain current response is subjected to zero point correction according to a preset linear phase compensator to obtain the initial resonant current waveform output by the linear phase compensator.

[0030] In an optional embodiment, the parasitic inductance parameters are sampled at high frequency within a fixed time window, and a single-cycle waveform is extracted from the sampled data. Ten sets of data are collected for the buffer capacitor parameters at preset fixed time intervals, and the single-cycle waveform is matched with the buffer capacitor collected data according to a gradient descent algorithm. The calculation error is determined by an adaptive threshold, and a parameter combination that meets the error requirement is obtained from the calculation result.

[0031] A second-order ordinary differential equation is established according to the parameter combination, a damping coefficient term and an oscillation term are introduced into the second-order ordinary differential equation, the equation is converted to the frequency domain space by Laplace transform, the characteristic roots of the equation are obtained from the frequency domain space, the characteristic roots are discretized by bilinear transformation, and the dynamic response data of the resonant circuit is obtained from the discretized data to construct a resonant circuit working model of the SiC-MOSFET device.

[0032] According to the resonant circuit working model, a sliding average with a window length of one quarter of the resonant period is performed on the dynamic response data of the resonant circuit, and a Chebyshev filter is applied to the smoothed data to eliminate high-frequency components. If the difference between the filtered voltage peak and the dynamic response peak is less than a threshold, a voltage waveform is obtained from the output end of the Chebyshev filter, and the voltage waveform is subjected to noise suppression through a Butterworth bandpass filter.

[0033] According to the voltage waveform, a fifth-order Fourier series is selected to expand the data within a half cycle to obtain a voltage spectrum, and the voltage spectrum is converted into a time-domain current response according to the forward Euler formula to obtain the time-domain current response. A linear phase compensator is used to perform zero-point correction on the current response, and a current waveform is obtained from the output of the linear phase compensator. A moving median filter is applied to the current waveform to eliminate interference caused by sampling.

[0034] It should be noted that the parasitic inductance parameters described in the embodiment of the present invention are manifested as lead inductance and chip package inductance in semiconductor switching devices, the sampling time window value range is nanoseconds, the sampling frequency is gigahertz, and the single-cycle waveform extraction interval is hundreds of nanoseconds. The buffer capacitor parameters include gate capacitance and junction capacitance. A set of data is collected every ten nanoseconds, and ten sets of data constitute a complete sampling sequence. The gradient descent algorithm sets the learning rate to 0.01, the number of iterations to fifty, and the calculation error threshold to one percent.

[0035] It should be noted that the second-order ordinary differential equation described in the embodiment of the present invention contains inductive and capacitive terms, the damping coefficient is introduced to reflect the switching loss, and the oscillation term characterizes the parasitic oscillation during the switching process. The Laplace transform converts the time domain differential equation into a frequency domain algebraic equation, and the characteristic root reflects the circuit quality factor and the resonant frequency. The bilinear transformation uses zero-pole configuration to realize discretization processing, the discretization frequency takes one-fourth of the sampling frequency, and the dynamic response data of the resonant circuit includes voltage stress information and current stress information. The dynamic response data of the resonant circuit contains high-frequency oscillation components caused by the switching process, the sliding average window length selects one-fourth of the resonant period, and the sliding step is the sampling interval. The Chebyshev filter order is set to fourth order, the cutoff frequency is five times the resonant frequency, and the passband ripple is less than 0.1 decibel. The voltage peak threshold is set to 5% of the switching voltage stress, the Butterworth bandpass filter bandwidth is twice the resonant frequency, and the center frequency is aligned with the resonant frequency. The fifth-order Fourier series expansion described in the embodiment of the present invention includes a DC component and five AC components, and the expansion interval covers half a switching cycle. The forward Euler formula adopts the forward difference format, and the difference step is the sampling interval. The linear phase compensator adopts an all-pass network structure, and the phase compensation amount is linearly related to the frequency. The moving median filter window length takes three sampling points, which can effectively suppress sampling noise.

[0036] This optional embodiment can obtain a complete initial resonant voltage waveform and an initial resonant current waveform, and then obtain the device stress distribution during the switching process. In practical applications in this field, parasitic parameter extraction is common in SiC-MOSFET devices. This type of wide bandgap semiconductor has a fast switching speed and significant parasitic effects. Resonant circuit modeling involves the energy transfer path during the switching process, which has an important impact on switching losses and electromagnetic interference. Waveform reconstruction reflects the law of change of voltage stress and current stress during the switching process, and provides a basis for device reliability and heat dissipation design. The initial resonant voltage waveform and the initial resonant current waveform can guide the selection of buffer circuit parameters and reduce switching losses and switching stress.

[0037] By performing high-frequency sampling on the parasitic inductance parameters, this embodiment can accurately capture its changes at different time points, thereby obtaining a more accurate single-cycle waveform; the accuracy and efficiency of parameter matching are improved by the gradient descent algorithm; by establishing a second-order ordinary differential equation and performing frequency domain conversion through Laplace transformation to obtain the characteristic roots of the equation, the dynamic characteristics of the resonant circuit of the SiC-MOSFET device can be more accurately described; the dynamic response data of the resonant circuit can be obtained through discretization processing, so that the resonant circuit working model of the constructed SiC-MOSFET device is more in line with the actual working conditions of the SiC-MOSFET device; sliding average processing and high-frequency component elimination of the dynamic response data of the resonant circuit can obtain a more accurate initial resonant voltage waveform; by presetting a linear phase compensator to perform zero-point correction on the time domain current response, the phase error can be eliminated and the accuracy of the initial resonant current waveform can be improved.

[0038] Step S102: calculating the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judging whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress.

[0039] In this embodiment, the voltage stress and current stress of the SiC-MOSFET device are calculated according to the initial resonant voltage waveform and the initial resonant current waveform, and whether the SiC-MOSFET device is in a safe working state is judged according to the voltage stress and the current stress, specifically including:

[0040] The initial resonant voltage waveform is differentially operated to obtain a voltage change rate sequence, and the instantaneous peak point of the voltage change rate sequence is extracted; the instantaneous peak point is normalized according to the hyperbolic tangent function to determine the normalized voltage data to obtain the voltage stress of the SiC-MOSFET device; the curve envelope of the initial resonant current waveform is extracted based on a preset conjugate gradient algorithm, and a current amplitude sequence is obtained based on the curve envelope; the current amplitude sequence is fitted according to the cubic spline difference method to determine the current stress amplitude to obtain the current stress of the SiC-MOSFET device; according to the normalized voltage A state-space equation is established based on the normalized voltage data and the current stress amplitude, and the normalized voltage data and the current stress amplitude are filtered based on a preset discrete Kalman filter and the state-space equation to obtain an over-limit duration interval; the stress over-limit degree is statistically calculated according to the over-limit duration interval to obtain an over-limit stress value, and the over-limit stress value is integrated on the time axis to obtain a stress failure warning threshold from the result of the integral calculation; the stress change trend is predicted based on a preset exponential averaging algorithm and the stress failure warning threshold, and the predicted value is compared with the preset safe working area boundary to determine whether the SiC-MOSFET device is in a safe working state.

[0041] In an optional embodiment, a differential operation is performed on the initial resonant voltage waveform at a sampling interval, a voltage change rate sequence is obtained based on the differential result, an instantaneous peak point is detected from the voltage change rate sequence, the instantaneous peak is normalized using a hyperbolic tangent function, a normalized parameter value is set to correspond to the rated voltage of the device, peak detection is performed on the normalized waveform, the peak data is corrected by a junction temperature compensation function, and a voltage stress peak value is obtained from the corrected value to obtain the voltage stress of the SiC-MOSFET device.

[0042] Based on the preset conjugate gradient algorithm, the curve envelope of the initial resonant current waveform is extracted, the number of iterations is set to one-fourth of the number of sampling points, the current amplitude sequence is obtained from the envelope curve, the amplitude sequence is fitted using cubic spline interpolation, the cutoff frequency of the sixth-order Butterworth low-pass filter is set to one-tenth of the switching frequency, the fitting curve is smoothed, and the current stress amplitude and overshoot are calculated from the smoothed data to obtain the current stress of the SiC-MOSFET device.

[0043] A state space equation is established based on the normalized voltage data and current stress amplitude, the temperature compensation coefficient and the gate voltage correction term are set, the observation matrix and the state transfer matrix are constructed, the reverse recovery parameters are obtained from the device data manual, and the stress data is filtered using a discrete Kalman filter. If the filter value exceeds the preset working area for three consecutive cycles, the start and end points of the limit are recorded, and the limit continuation interval is obtained from the recorded data.

[0044] The stress over-limit degree is statistically calculated according to the over-limit continuous interval to obtain the over-limit stress value, the over-limit stress value is integrated to calculate the area on the time axis, the stress failure warning threshold is obtained from the area value, the temperature influence is corrected by the weight coefficient, the stress change trend is predicted by exponential weighted average, the working state of the device is judged by comparing the predicted value with the boundary of the safe working area, the safety margin is calculated from the comparison result, and it is determined whether the SiC-MOSFET device is in a safe working state.

[0045] It should be noted that in the processing of the initial resonant voltage waveform, the differential operation sampling interval is selected in the nanosecond level, which can reflect the rapid voltage change characteristics during the switching process. The voltage change rate sequence is in the order of kilovolts per microsecond, and the instantaneous peak detection sets the sliding window width to five times the sampling period. The normalized parameter of the hyperbolic tangent function corresponds to the rated voltage of the device. When the rated voltage of the device is in the kilovolt level, the normalized parameter takes a value between 0.1 and 0.5. The junction temperature compensation function adopts linear correction. For every ten degrees increase in junction temperature, the voltage margin decreases by one percent.

[0046] It should be noted that in the processing of the initial resonant current waveform, the conjugate gradient algorithm is used, and the number of iterations is one-fourth of the number of sampling points to ensure convergence and computational efficiency. The envelope curve extraction sets the upper envelope and the lower envelope to reflect the current fluctuation range during the switching process. The cubic spline interpolation adopts natural boundary conditions to maintain the continuity of the curve. The cutoff frequency of the sixth-order Butterworth filter is one-tenth of the switching frequency to achieve low-frequency smoothing effect. The overshoot is defined as the ratio of the peak current to the steady-state current. The state space equation contains voltage state quantities and current state quantities. The temperature compensation coefficient increases with the increase of junction temperature, and the gate voltage correction term is inversely proportional to the gate resistance value. The observation matrix is ​​used to reflect the voltage and current sampling characteristics, and the state transfer matrix describes the dynamic characteristics of the switching process. The reverse recovery parameters include the reverse recovery time and the reverse recovery charge. The three consecutive cycle over-limit criterion is applicable to the working condition of the switching frequency in the kilohertz range. The stress integral in the over-limit continuous interval adopts the trapezoidal integral algorithm, and the integral value exceeds the rated value by 20% to trigger the failure warning. The temperature influence weight coefficient increases exponentially with the increase of junction temperature, and the weight doubles for every 25 degrees increase. The exponentially weighted average forecast uses recent data with a greater weight than long-term data, and the forecast window length is five times the switching cycle. The safety margin is defined as the difference between the actual stress and the rated stress as a percentage of the rated value.

[0047] It should be noted that in the actual application of this field, during the switching process of SiC-MOSFET devices with a power of kilowatts, the voltage stress is in the order of kilovolts, and the voltage change rate reaches the order of volts per nanosecond. The current stress is in the order of hundreds of amperes, and the overshoot is about 20%. The switching frequency is in the order of tens of kilohertz, and the reverse recovery time is in the order of hundreds of nanoseconds. The junction temperature ranges from room temperature to one hundred and fifty degrees, and the temperature coefficient is in the order of three thousandths per degree. The boundary of the safe operating area shrinks as the junction temperature increases, and the boundary curve has a hyperbolic characteristic. Stress over-limit warning and failure prediction play a key role in device reliability protection.

[0048] The differential operation of this embodiment can capture more accurate voltage changes, thereby obtaining the dynamic characteristics of the device. The normalization process can eliminate the differences between different voltage peak points, thereby improving the accuracy of voltage stress. The conjugate gradient algorithm can more efficiently obtain a more accurate current amplitude sequence, and a more accurate current stress can be obtained by cubic spline difference. Based on the state space equation, combined with the discrete Kalman filter, more accurate real-time device operating data can be obtained, and the over-limit duration interval and over-limit stress value can be used to quantify the working state of the device, ensuring that the device is in a safe working state. This embodiment realizes accurate monitoring and prediction of SiC-MOSFET devices, ensuring that SiC-MOSFET devices are in a safe working state.

[0049] Step S103: when the SiC-MOSFET device is in a safe working state, determining the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform; taking minimizing the total switching loss as the objective function, optimizing the parasitic inductance parameters and the buffer capacitance parameters of the SiC-MOSFET device according to the genetic algorithm to obtain the first parasitic inductance parameters and the first buffer capacitance parameters.

[0050] In this embodiment, when the SiC-MOSFET device is in a safe working state, determining the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform specifically includes:

[0051] Extract the interval from the rising edge value to the falling edge value of the gate signal in the initial resonant voltage waveform to obtain the conduction interval; subtract the drain inductance voltage drop from the conduction interval sampling data to obtain the on-resistance value; fit the on-resistance value according to the forgetting factor recursive least squares method, and correct the on-resistance value in combination with the preset junction temperature coefficient; obtain the on-current value, and calculate the instantaneous conduction loss based on the product of the corrected on-resistance value and the square of the on-current value; locate the switching instant of the initial resonant current waveform according to the preset quadratic spline wavelet basis function, determine the switching time interval, and calculate the instantaneous switching loss by sliding integration of the voltage and current product in the switching time interval; perform trapezoidal integration on the instantaneous conduction loss to determine the single-cycle conduction loss; perform definite integration on the instantaneous switching loss to determine the single-cycle switching loss; when the accumulated fluctuation amplitude of the single-cycle conduction loss and the single-cycle switching loss within the preset period is less than the preset average value ratio, perform arithmetic averaging on the accumulated fluctuation amplitude, and compensate the average value in combination with the preset junction temperature correction coefficient to determine the total switching loss of the SiC-MOSFET device.

[0052] In an optional embodiment, the interval from the rising edge value to the falling edge value of the gate signal in the initial resonant voltage waveform is extracted to obtain the conduction interval, the drain inductance voltage drop is subtracted from the conduction interval sampling data to obtain the on-resistance value, the on-resistance value is fitted using the recursive least squares method with a forgetting factor of 0.98, the on-resistance is corrected according to a preset junction temperature coefficient, and the instantaneous conduction loss is calculated by the product of the corrected resistance value and the square of the on-current.

[0053] The switching instant of the initial resonant current waveform is located according to the preset quadratic spline wavelet basis function, and a quarter of the switching cycle is taken before and after the gate signal edge as the switching time interval. The voltage-current product in the switching time interval is calculated by sliding integration with a fixed window width of ten times the sampling interval. The voltage-current product in the reverse recovery interval is supplementarily integrated, and the parasitic capacitance charging and discharging loss is deducted from the integral data. The instantaneous switching loss is smoothed by a Gaussian filter to determine the instantaneous switching loss.

[0054] The instantaneous conduction loss is subjected to trapezoidal integration at every fixed sampling point during the conduction time, and the single-cycle conduction loss is obtained from the rising edge to the falling edge of the gate signal.

[0055] The instantaneous switching loss is definitely integrated within the switching time interval, and the single-cycle switching loss and the gate drive loss are obtained from the boundary point of the switching interval.

[0056] The single-cycle conduction loss and the single-cycle switching loss are accumulated over ten consecutive cycles. If the loss fluctuation amplitude is less than 5% of the average value, the accumulated results are arithmetic averaged, the average value is compensated by a preset junction temperature correction coefficient, the total switching loss of the device is obtained from the compensated value, the loss calculation accuracy is verified using the actual measured temperature of the thermocouple, and the total switching loss of the SiC-MOSFET device is determined.

[0057] It should be noted that in the process of extracting the conduction interval, the gate signal switches from a low level to a high level to mark the start of conduction. The duration of the high level is in the order of microseconds and decreases as the switching frequency increases. The drain inductance in SiC-MOSFET devices is usually tens of nanohenries. The inductor voltage drop is proportional to the current change rate and reaches a peak value at the moment of turn-on. The recursive least squares forgetting factor is set to 0.98, taking into account the calculation convergence speed and data update timeliness. The on-resistance temperature coefficient is in the order of milliohms per unit.

[0058] It should be noted that the switching instant positioning uses a quadratic spline wavelet basis function, which has good time-frequency positioning characteristics and is suitable for processing fast-changing signals during the switching process. The switching time interval covers a quarter cycle, which can reflect the voltage and current overlap area during the switching process. The sliding integral window width is ten times the sampling interval, which balances the calculation accuracy and noise suppression effect. The reverse recovery interval is located after the turn-off moment, lasts for hundreds of nanoseconds, and the loss accounts for 10% to 20%.

[0059] It should be noted that in the trapezoidal integral calculation, the sampling point interval is selected in the nanosecond level to ensure the capture of the transient characteristics of the switching process. The gate signal edge positioning accuracy reaches the nanosecond level, accurately defining the calculation boundary of the conduction loss. The gate drive loss is related to the gate capacitance value and the drive voltage, and accounts for a small proportion of the total loss but cannot be ignored. The loss fluctuation amplitude is judged using ten consecutive cycles of data to reflect the stability of the loss calculation. The fluctuation threshold is set to 5% of the average value to filter out the influence of occasional interference factors. The junction temperature correction coefficient increases with the increase of temperature, and the correction amount reaches 30% of the room temperature state loss value at the rated operating temperature. The thermocouple temperature measurement accuracy is at the level of zero point one degree, and is arranged on the surface of the device housing.

[0060] In practical applications in this field, the on-resistance of SiC-MOSFET devices is in the milliohm range, and the junction temperature coefficient is about 3 thousandths per degree. The switching frequency is in the order of tens of kilohertz, and the switching time is in the order of hundreds of nanoseconds. The gate drive voltage is in the range of plus or minus twenty volts, and the drive current is in the order of amperes. The reverse recovery charge is in the order of microcoulombs, and the recovery time is in the order of hundreds of nanoseconds. Parasitic capacitance charging and discharging losses account for about 15% of the total losses. The loss calculation accuracy is verified by the thermocouple temperature measurement results, and the error between the calculated value and the measured value is within 10%. The junction temperature range covers room temperature to one hundred and fifty degrees, the loss increases with the increase of temperature, and the temperature coefficient is nonlinear.

[0061] This embodiment obtains the on-resistance value through the initial resonant voltage waveform and corrects the on-resistance value, so as to obtain accurate instantaneous conduction loss, thereby improving the accuracy of loss calculation; by calculating the instantaneous switching loss and the instantaneous conduction loss, the loss of the SiC-MOSFET device can be accurately reflected, and dynamic loss monitoring of the SiC-MOSFET device can be realized; the periodic loss is calculated by the instantaneous switching loss and the instantaneous conduction loss, which is more accurate than the traditional average loss evaluation method, and the influence of temperature change on the loss is considered, thereby improving the accuracy of the total switching loss calculation of the SiC-MOSFET device.

[0062] In this embodiment, the objective function is to minimize the total switching loss, optimize the parasitic inductance parameters and the buffer capacitance parameters of the SiC-MOSFET device according to the genetic algorithm, and obtain the first parasitic inductance parameters and the first buffer capacitance parameters, which specifically include:

[0063] A parameter interval is constructed based on the parasitic inductance parameter and the buffer capacitor parameter, and the parameter interval is encoded by Gray code mapping to obtain a chromosome coding sequence; the chromosome coding sequence is decoded to obtain a parameter value; the parameter value is substituted into the resonant circuit of the SiC-MOSFET device to calculate the switching loss, and the switching loss value is obtained, and the fitness function of the genetic algorithm is constructed according to the switching loss value, with minimizing the total switching loss as the objective function, and with the SiC-MOSFET device operating in a safe working area defined by a voltage safety range and a current safety range as a constraint condition, a crossover point is set for the chromosome coding sequence in combination with the fitness function, and a crossover operation is performed to obtain a first chromosome coding sequence; the first chromosome coding sequence is decoded to obtain a first parameter value; the first parameter value is substituted into the resonant circuit of the SiC-MOSFET device to calculate the first switching loss and the stress overlimit, and the optimal chromosome sequence is obtained in combination with a preset loss weighted penalty value; the optimal chromosome sequence is decoded to obtain a first parasitic inductance parameter and a first buffer capacitor parameter.

[0064] In an optional embodiment, a parameter value interval is constructed based on the device rated value based on the parasitic inductance parameter and the buffer capacitance parameter, the interval is divided into several sub-intervals according to the preset parameter accuracy requirements, the number of binary coding bits is set for each parameter, the chromosome code is constructed using Gray code mapping, the parameter validity judgment condition is generated from the sub-interval boundary value, the parameter boundary is corrected by a preset junction temperature compensation coefficient, and the encoded parameter is restored using the binary to decimal rule to obtain the parameter value.

[0065] Substituting the parameter value into the resonant circuit of the SiC-MOSFET device to calculate the switching loss, the switching loss value is obtained, and the fitness function of the genetic algorithm is constructed according to the switching loss value, the voltage stress exceeding limit penalty coefficient and the current stress exceeding limit penalty coefficient are set, the fitness function is multiplied by the temperature correction factor, the parameters are encoded, and an initial population with a scale of five times the chromosome length is generated. The selection probability is calculated using the fitness function, and the dominant gene is selected through the roulette algorithm, and one quarter of the individuals with the highest fitness are retained from the dominant genes.

[0066] Taking minimizing the total switching loss as the objective function and taking the SiC-MOSFET device operating in the safe working area defined by the voltage safety range and the current safety range as the constraint condition, the dominant gene is crossovered with a probability of 0.8, the crossover point is set at the parameter boundary, the chromosome after crossover is mutated with a probability of 0.01, the first parameter value is obtained from the mutated chromosome decoding, the first parameter value is smoothed by using the Butterworth bandpass filter, the first parameter value is limited according to the device safe working area boundary, and the first parameter value is corrected by calculating the junction temperature through the thermal resistance network. The switching loss and stress over-limit are calculated according to the first parameter value, the population is sorted according to the loss weighted penalty value, the best quarter of individuals are selected from the sorting results to enter the next generation, the standard deviation of the loss value of the best individual for five consecutive generations is calculated, and if the standard deviation is less than one percent of the average value and the number of iterations exceeds five times the chromosome length, the optimal chromosome sequence is determined to be obtained; the optimal chromosome sequence is decoded to obtain the first parasitic inductance parameter and the first buffer capacitor parameter.

[0067] It should be noted that the parasitic inductance parameters and buffer capacitance parameters have a typical range of values ​​in SiC-MOSFET devices. The parasitic inductance is in the order of tens of nanohenries, and the buffer capacitance is in the order of hundreds of picofarads. The parameter accuracy requirements are reflected in the number of binary code bits, usually eight bits to ensure a resolution of four thousandths. Gray code changes only one bit in adjacent values, reducing the convergence problems caused by parameter mutations. The junction temperature compensation coefficient increases exponentially with increasing temperature, affecting the effective range of the parameters.

[0068] It should be noted that in the calculation of switching loss, both conduction loss and switching loss take into account the influence of temperature, and the fitness function reflects the constraint conditions through penalty terms. The voltage stress over-limit penalty coefficient is set to five times the basic fitness value, and the current stress over-limit penalty coefficient is set to three times the basic fitness value. The temperature correction factor doubles every twenty-five degrees, thus reflecting the trend of increasing losses when working at high temperatures. The initial population size is five times the chromosome length to ensure the effect of the genetic operator. The selection probability is proportional to the inverse of the fitness, and the proportion of dominant individuals is retained to one-quarter. The crossover operation probability is set to 0.8, and the crossover point is set at the parameter boundary to ensure parameter integrity. The mutation probability is 0.01 to avoid algorithm divergence caused by excessive disturbance. The cutoff frequency of the bandpass filter is selected as twice the switching frequency to achieve parameter smoothing. The thermal resistance network includes the thermal resistance from junction temperature to case temperature and the thermal resistance from case temperature to ambient temperature to accurately calculate the temperature rise of the device.

[0069] It should be noted that in the application of SiC-MOSFET devices, the switching frequency is tens of kilohertz, and the switching loss accounts for a significant proportion. The device junction temperature range covers room temperature to 150 degrees, and the safe working area shrinks with the increase of temperature. In the parameter optimization process, the loss weighted penalty value comprehensively considers the size of the switching loss and the degree of constraint violation, and the sorting selection ensures the quality of the population. The standard deviation threshold is set to 1% of the average value, reflecting the stability requirement of the optimization result. The number of iterations exceeds five times the chromosome length to ensure the adequacy of convergence. The optimization result verification uses the measured waveform to measure the voltage stress and current stress distribution during the switching process to verify the effectiveness of the optimization parameters. Parasitic inductance optimization reduces the switch overvoltage, and buffer capacitor optimization reduces the switching loss, and the two constitute a compromise relationship. Temperature changes cause parameter drift, and parameter adaptive adjustment is achieved through online optimization. The boundary of the device safe working area is set with a reserved margin to ensure that the stress does not exceed the limit during the optimization process. The convergence of the algorithm is judged by the stability of the optimal individual loss value of multiple consecutive generations to avoid the local optimal trap.

[0070] In this embodiment, a parameter interval is constructed by parasitic inductance parameters and buffer capacitance parameters, and Gray code mapping is performed, so that the genetic algorithm is based on the actual working data of the SiC-MOSFET device, thereby improving the iteration accuracy of the genetic algorithm; by bringing the parameter value back to the resonant circuit to calculate the switching loss, the switching loss value under different parameter values ​​can be accurately evaluated, providing reliable data support for constructing the fitness function of the genetic algorithm; by constructing an objective function and constraint conditions that meet the working conditions of the SiC-MOSFET device, iterating with the genetic algorithm can improve the working efficiency and reliability of the SiC-MOSFET device, reduce the switching loss of the SiC-MOSFET device, and thereby obtain the first parasitic inductance parameter and the first buffer capacitance parameter of the SiC-MOSFET device in a more excellent condition.

[0071] Step S104: adjusting the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain a first resonant voltage waveform and a first resonant current waveform; performing frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimizing the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude.

[0072] In this embodiment, the buffer circuit design of the SiC-MOSFET device is adjusted according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain the first resonant voltage waveform and the first resonant current waveform, specifically including:

[0073] The loop damping equation of the SiC-MOSFET device is corrected according to the first parasitic inductance parameter and the first buffer capacitor parameter, and the parasitic inductance voltage drop and the buffer capacitor charging and discharging current of the SiC-MOSFET device are integrated by a fourth-order Runge-Kutta integral to obtain a resonance process waveform; the resonance starting point of the resonance process waveform is located according to a preset double threshold crossing detection method, and the post-sampling data of the resonance starting point is fitted with a sixth-order Chebyshev polynomial to obtain an attenuation rate and a frequency offset; the fitted parameters of the SiC-MOSFET device are corrected according to a gradient descent method, and the buffer circuit design of the SiC-MOSFET device is adjusted according to the correction result; a singular value decomposer is constructed according to the attenuation rate and the frequency offset to sort the parameter sensitivity of the fitted parameters of the SiC-MOSFET device, and a parameter update value is obtained according to a preset complementary state observer; the cache loop mutual impedance matrix of the SiC-MOSFET device is reconstructed according to the parameter update value, and the admittance equation of the cache loop mutual impedance matrix is ​​solved according to a third-order Bode integral format to obtain a first resonance voltage waveform and a first resonance current waveform.

[0074] In an optional embodiment, the loop damping equation of the SiC-MOSFET device is corrected according to the first parasitic inductance parameter and the first buffer capacitor parameter, the integration step is set to one thousandth of the switching period, the parasitic inductance voltage drop and the buffer capacitor charge and discharge current are integrated by fourth-order Runge-Kutta integration, the resonance quality factor is calculated from the damping attenuation coefficient, the state equation is constructed according to the resonance quality factor and the natural resonant frequency, the state equation is iteratively calculated by a variable step solver, and the resonance process waveform is obtained from the calculation results.

[0075] The resonance starting point of the resonance process waveform is located according to a preset double threshold cross detection method, the detection thresholds are set to one quarter and three quarters of the waveform peak value, sixth-order Chebyshev polynomial fitting is performed on the sampling data after the starting point, the fitting interval is set to include three complete oscillation cycles, the attenuation rate and the frequency offset are calculated from the regression coefficient, the fitted parameters of the SiC-MOSFET device are corrected according to the gradient descent method, and the buffer circuit design of the SiC-MOSFET device is adjusted according to the correction results.

[0076] A singular value decomposer is constructed according to the attenuation rate and frequency offset, the dimension of the decomposition matrix is ​​set equal to the number of parameters, the parameter sensitivity is sorted according to the size of the singular value, the sensitive parameters are estimated online using a complementary state observer, the observer gain is set to match the resonant frequency, the parameter estimation value is filtered by the least squares method, if the parameter error after filtering exceeds the preset value by 5%, the recursive least squares method is used for online update, and finally the parameter update value is obtained.

[0077] The cache loop mutual impedance matrix of the SiC-MOSFET device is reconstructed according to the parameter update value, a branch connection topology is generated according to the impedance value, a node admittance matrix is ​​calculated from the topological structure, the admittance equation is solved in the time domain using the third-order Bode integral format, the solution step is set to 1% of the resonance period, numerical oscillation is eliminated by a smoothing factor, a first resonant voltage waveform and a first resonant current waveform are obtained from the solution data, and the waveform is amplitude corrected using a series damping network.

[0078] It should be noted that in the loop damping equation, the parasitic inductance voltage drop is proportional to the rate of change of the inductance current, and the coefficient is the inductance value. The buffer capacitor charge and discharge current is proportional to the rate of change of the capacitor voltage, and the coefficient is the capacitance value. The integration step is one thousandth of the switching period, which corresponds to the nanosecond level at a switching frequency of tens of kilohertz. The fourth-order Runge-Kutta integral contains four sub-steps, each of which uses a different weight to improve the calculation accuracy. The resonance quality factor reflects the degree of energy loss, and the value is between five and ten.

[0079] The dual threshold crossing detection uses the intersection of the waveform and two fixed thresholds. The detection threshold is set to one-quarter and three-quarters of the waveform peak value to avoid noise interference. The sixth-order Chebyshev polynomial has good function approximation characteristics. The fitting interval covers three complete oscillation cycles and can reflect the waveform attenuation trend. The attenuation rate reflects the damping size, and the frequency offset reflects the change in the resonance characteristics.

[0080] It should be noted that the singular value decomposer decomposes the parameter matrix into three matrix products, and the size of the singular value reflects the degree of parameter influence. The complementary state observer adopts a voltage and current complementary structure, and the observer gain matches the resonant frequency to ensure the dynamic response speed. The parameter estimation error threshold is set to five percent, and exceeding the threshold triggers parameter update. In practical applications, the switching frequency of silicon carbide devices reaches tens of kilohertz, the parasitic inductance is in the order of tens of nanohenries, and the buffer capacitance is in the order of hundreds of picofarads. Loop damping is achieved through series resistance, and the resistance value is in the order of ohms. The resonant frequency is in the order of megahertz, and the oscillation duration covers several cycles. During the parameter optimization process, the parasitic inductance value is reduced to reduce the switch overvoltage, and the buffer capacitance value is increased to reduce the switching loss.

[0081] The node admittance matrix can reflect the circuit topology, and the matrix dimension is equal to the number of independent nodes. The third-order Bode integral format has good stability, and the solution step size is 1% of the resonance period to ensure the calculation accuracy. The series damping network is composed of a resistor and a capacitor in series, and the resistance value shows a nonlinear characteristic with frequency. The smoothing factor eliminates high-frequency numerical oscillations, and the coefficient is selected between 0.1 and 0.5. The optimized waveform characteristics are reflected in the reduction of overvoltage amplitude, accelerated oscillation attenuation, and reduced switching loss. The voltage stress is reduced by 20%, the oscillation duration is shortened to two-thirds of the original, and the switching loss is reduced by 30%. The online update of parameters compensates for the drift caused by temperature changes to ensure the stability of the optimization effect. The waveform optimization results are verified by actual measurements, and the error between the measured data and the simulation results is within 10%.

[0082] This embodiment corrects the loop damping equation by optimizing the first parasitic inductance parameter and the first buffer capacitor parameter, thereby ensuring that the equation can more accurately reflect the actual working condition of the device, improving the accuracy of the parasitic inductance voltage drop and the buffer capacitor charging and discharging current, and improving the accuracy of the resonance process waveform; by optimizing the resonance starting point and the sampling data after fitting, the accuracy of the attenuation rate and the frequency offset is ensured, thereby optimizing the buffer circuit design adjustment effect of the SiC-MOSFET device, and making the performance of the SiC-MOSFET device more excellent; by sorting the parameter sensitivity, the parameters that have a greater impact on the SiC-MOSFET device can be identified, and then the parameter values ​​are updated in combination with the complementary state observer, so as to further optimize the SiC-MOSFET device and reduce the switching loss of the SiC-MOSFET device; by solving the admittance equation, the resonant voltage waveform and the resonant current waveform can be accurately obtained.

[0083] In this embodiment, the frequency domain analysis of the first resonant voltage waveform and the first resonant current waveform is performed to obtain the resonant frequency and the resonant amplitude, and the SiC-MOSFET device parameters and the buffer circuit design are optimized according to the resonant frequency and the resonant amplitude, specifically including:

[0084] A Hanning window function is set according to the first resonant voltage waveform and the first resonant current waveform, and spectrum data is obtained based on discrete Fourier transform; five frequency points before and after the main peak in the spectrum data are fitted according to the parabolic interpolation method to determine the resonant frequency; the resonant amplitude is determined according to the amplitude corresponding to the frequency point in the spectrum data and the preset window function correction coefficient; the energy density of the integer points of the resonant frequency is calculated according to the resonant frequency and the resonant amplitude, and the energy density sequence is decomposed in combination with the wavelet packet transform method to obtain the on-off switching frequency band range; the on-off switching frequency band range is reconstructed using an autoregressive spectrum estimator to determine the interference amount; the interference amount is subjected to frequency range multi-resolution spectrum analysis to extract the spectrum envelope curve, and calculate the interference suppression depth based on the spectrum envelope curve; when the interference suppression depth is less than a preset interference suppression depth threshold, generate a SiC-MOSFET device parameter optimization objective function according to a preset random forest regressor; perform resonant frequency constraints and switch stress constraints on a first parasitic inductance parameter and a first buffer capacitor parameter according to the SiC-MOSFET device parameter optimization objective function, and solve the SiC-MOSFET device parameter optimization objective function based on a preset step-size adaptive gradient projection method to obtain optimal parameter values; optimize the SiC-MOSFET device parameters and buffer circuit design according to the optimal parameter values.

[0085] In an optional embodiment, a Hanning window function with a window length of ten times the switching period is set according to the first resonant voltage waveform and the first resonant current waveform, a discrete Fourier transform is performed according to the windowing sequence to obtain the spectrum, parabolic interpolation is used to fit the five frequency points before and after the main peak, the resonant frequency is obtained from the highest point of the fitting curve, and the resonant amplitude is calculated by the corresponding amplitude of the frequency point and the window function correction coefficient.

[0086] The energy density at the integer points of the resonant frequency is calculated according to the resonant frequency and the resonant amplitude, the energy density sequence is decomposed using a five-layer wavelet packet transform, the basis function is set to be a Dobesi wavelet, the on-off switching frequency band range is obtained from the third to fifth layer coefficients, the spectrum within the frequency band is reconstructed using a thirty-second-order autoregressive spectrum estimator, the spectrum lines are integrated using the electromagnetic interference limit curve, and the interference amount is determined.

[0087] An eight-band multi-resolution spectrum analysis is performed on the interference. The frequency resolution is set from one-tenth to ten times the switching frequency. The spectrum envelope curve is extracted according to the resolution sequence, and the interference suppression depth is calculated from the curve area. If the suppression depth is less than 60% of the derating of the electromagnetic interference limit curve, the random forest regressor is used to generate the SiC-MOSFET device parameter optimization objective function, and the weight distribution of conduction loss and interference suppression is established from the objective function.

[0088] According to the SiC-MOSFET device parameter optimization objective function, the resonant frequency constraint and the switch stress constraint are performed on the first parasitic inductance parameter and the first buffer capacitor parameter in combination with weight allocation, the initial value of the Lagrange multiplier is set as the midpoint of the constraint boundary, the multiplier is iterated by the gradient projection method with adaptive step size, the parameter validity is ensured by the projection operator, the optimal parameter value is obtained from the iterative sequence variance being less than the preset convergence threshold, the temperature coefficient is corrected for the optimal parameter value, and the SiC-MOSFET device parameters and the buffer circuit design are optimized according to the optimal parameter value.

[0089] It should be noted that in frequency domain analysis, the Hanning window function has excellent spectrum leakage suppression characteristics, and the window length is selected to be ten times the switching period to ensure that the frequency resolution reaches 10% of the switching frequency. Parabolic interpolation uses five frequency points before and after the main peak to construct a quadratic curve, which improves the frequency estimation accuracy to the Hertz level. The window function correction coefficient compensates for the amplitude attenuation, and the coefficient value is between 0.5 and 1. The correlation coefficient between the spectrum reconstruction signal and the original signal reaches more than 0.95. In power converters, the resonant frequency is usually in the megahertz level, and the energy is mainly distributed near the integer multiples of the switching frequency.

[0090] The five-layer wavelet packet decomposition covers from the switching frequency to the radio frequency band, and the Dobesi wavelet basis function has good frequency positioning characteristics. The order of the autoregressive spectrum estimator is selected as the 32nd order to balance the calculation amount and the spectrum resolution. The electromagnetic interference limit curve uses quasi-peak detection below 30 MHz. The multi-resolution spectrum analysis uses an eight-octave frequency range, covering the range from one-tenth to ten times the switching frequency, reflecting the energy diffusion characteristics during the switching process. The area of ​​the spectrum envelope curve represents the total amount of interference, and the suppression depth requires a 60% reduction in the limit, corresponding to a 30-decibel attenuation. The random forest regressor training samples come from historical optimization data, and the feature quantities include switching frequency, resonant frequency, and quality factor.

[0091] It should be noted that the switching frequency of SiC-MOSFET devices reaches tens of kilohertz, the parasitic inductance optimization range is in the nanohenry level, and the buffer capacitance is in the picofarad level. The resonant frequency constraint ensures that the resonant period is less than one-quarter of the switching period, and the switch stress constraint limits the overvoltage to within 30% of the rated value. The step size of the gradient projection method starts from zero point one and decays with the number of iterations. The temperature coefficient correction takes into account the change in junction temperature, and the coefficient value increases exponentially with the increase in temperature. Among them, the parasitic inductance is reduced from fifty nanohenries to twenty nanohenries, the buffer capacitance is increased from one hundred picofarads to three hundred picofarads, and the resonant frequency is reduced from two megahertz to one and a half megahertz. The main peak of the interference spectrum is reduced by forty decibels, and the sideband attenuation exceeds thirty decibels. The switching loss is reduced by thirty percent, and the overvoltage is reduced by forty percent. When the temperature changes from room temperature to one hundred and fifty degrees, the parameter drift is controlled within ten percent. The optimization results are verified by electromagnetic interference actual measurement, and the test data and simulation predictions are 85% consistent.

[0092] This embodiment sets a Hanning window function and combines discrete Fourier transform to obtain spectrum data, which can effectively reduce spectrum leakage and improve the accuracy of spectrum analysis, and accurately determine the resonant frequency and resonant amplitude by fitting data and correcting data; effectively identifies the on-switch frequency band range by energy density and wavelet packet transform method, and accurately obtains the interference amount by reconstructing the on-switch frequency band range by autoregressive spectrum estimator, so as to accurately calculate the interference suppression depth and generate an optimization objective function that is more suitable for SiC-MOSFET devices. By constructing constraints and solving the optimization objective function, the parameter optimization and buffer circuit design optimization of SiC-MOSFET devices are realized, the switching loss of SiC-MOSFET devices is reduced, and the working performance of SiC-MOSFET devices is improved.

[0093] Step S105: obtaining the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the snubber circuit design.

[0094] In this embodiment, obtaining the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the buffer circuit design specifically includes:

[0095] Based on the optimized SiC-MOSFET device parameters and buffer circuit design, the voltage signal and current signal of the switch modulation circuit are collected, and the sampling waveform data are obtained to determine the measured resonant voltage waveform and the measured resonant current waveform; the sampling waveform data are denoised by Dobesi wavelet, and the signal envelope is extracted according to the Hilbert transform method; the conduction interval and the switching interval are determined based on the gate signal of the SiC-MOSFET device; the instantaneous power waveform is determined according to the signal envelope, and the instantaneous power waveform is respectively integrated in the conduction interval and the switching interval to determine the loss value; the thermocouple temperature measurement data of the SiC-MOSFET device is obtained, and a correction relationship between the loss value and the thermocouple temperature measurement data is constructed, and a temperature characteristic curve corresponding to the correction relationship is constructed according to a Gaussian kernel function regressor; the measured switching loss is obtained based on the temperature characteristic curve.

[0096] In an optional embodiment, based on the optimized SiC-MOSFET device parameters and buffer circuit design, a differential probe acquisition structure is arranged, a sampling rate is set according to five times the resonant frequency, a sampling accuracy of twelve bits is selected, a resistor divider network with an attenuation ratio of one percent is configured for the voltage signal, an isolation amplifier with a gain of ten is set for the current signal, waveforms are collected through an optical fiber transmission link with a bandwidth of five times the sampling rate, and data is recorded using a dual-channel synchronous sampler triggered by the rising edge of the gate signal to determine the measured resonant voltage waveform and the measured resonant current waveform. The edge point of the driving signal is extracted according to the sampled data, four-layer decomposition of the Dobesi wavelet denoising is performed on the collected waveform, the threshold is set to three times the standard deviation of the noise, four periodic waveforms containing the switching process are intercepted from the denoised data, the waveform is subjected to a twelve-order finite-length Hilbert transform to extract the signal envelope, and the signal is processed by a sixth-order Butterworth bandpass filter with the center frequency aligned to the resonant frequency.

[0097] The voltage-current product of the processed signal is calculated to obtain the instantaneous power waveform, the conduction interval and the switching interval are located from the edge of the gate signal, a trapezoidal integration with a step size of the sampling interval is performed on the instantaneous power in the conduction interval, and a step size of half the sampling interval is used to integrate the instantaneous power in the switching interval to determine the loss value.

[0098] By comparing the temperature measurement data of three thermocouples set up on the surface of the device with the integration results, a loss correction relationship is established from the comparison data; based on the correction relationship, a Gaussian kernel function regressor is used to construct the temperature characteristic curve, and the kernel function bandwidth selects one-fourth of the temperature change range. The temperature coefficient is calculated from the slope of the characteristic curve, and the instantaneous switching loss integral value is corrected by the temperature coefficient. The calculation accuracy is verified by comparing with a standard calorimeter, and the measured switching loss is obtained from the verified value. The measured switching loss is continuously monitored for twenty cycles to verify the measurement stability.

[0099] It should be noted that the differential probe acquisition structure is widely used in wide bandgap semiconductor switch applications, with high common mode rejection ratio and wide bandwidth characteristics. When the resonant frequency is in the megahertz range, the sampling rate reaches hundreds of megahertz, meeting the requirements of the Nyquist sampling theorem. The twelve-bit sampling accuracy provides microvolt resolution to meet the switching loss measurement requirements. The resistor divider network uses high-voltage precision resistors, and the voltage divider ratio is set to one percent, which is suitable for kilovolt voltage measurement. The isolation amplifier has a gain of ten, and is used with a shunt to measure currents from several amperes to tens of amperes.

[0100] The four-layer wavelet decomposition corresponds to a frequency band from the switching frequency to the radio frequency band, and the Dobesi wavelet basis function has good time-frequency positioning characteristics. The denoising threshold is set to three times the noise standard deviation, corresponding to a 99 percent confidence level under the Gaussian white noise assumption. The four switching cycle waveforms include the complete switching process and the oscillation attenuation process. The twelfth-order Hilbert transform introduces a 90-degree phase shift in the frequency domain to accurately extract the envelope information.

[0101] In the instantaneous power calculation, the voltage and current sampling points are precisely aligned to the nanosecond level to eliminate the influence of delay errors. The conduction interval integration uses all sampling points, and the switching interval integration is encrypted to half the sampling interval to improve the calculation accuracy of the key interval. The three thermocouples are distributed in different positions of the device to reflect the uneven temperature distribution, and the temperature measurement accuracy reaches 0.1 degree. The loss correction is based on the thermoelectric characteristic curve to establish the relationship between power loss and temperature rise.

[0102] It should be noted that in the application of SiC-MOSFET devices, the switching frequency reaches tens of kilohertz, the voltage stress is in the kilovolt level, and the current stress is in the tens of amperes. The bandwidth of the Gaussian kernel function selects one-fourth of the temperature change range to ensure the smoothness of the curve fitting. The temperature coefficient increases exponentially with the increase of junction temperature, and the loss increases by 20% for every 25 degrees increase. The calorimeter comparison verifies the accuracy of loss calculation, and the error is controlled within 5%. In actual testing, the bandwidth of the differential probe reaches 500 megahertz, and the common mode rejection ratio exceeds 80 decibels. The bandwidth of the optical fiber transmission link exceeds the sampling rate by five times, and the anti-interference ability is strong. The jitter of the synchronous sampling trigger is less than one nanosecond, ensuring the accuracy of waveform reconstruction. The digital filter adopts a sixth-order Butterworth structure, and the passband ripple is less than 0.1 decibel. After continuous monitoring for 20 cycles, the loss fluctuation amplitude is controlled within 3% of the mean to verify the measurement stability. The overall performance of the measurement system meets the switching characteristic test requirements of wide bandgap semiconductor devices.

[0103] This embodiment can effectively remove noise in the sampled waveform data through Dobesi wavelet denoising and Hilbert transform method, improve the signal-to-noise ratio of the signal, accurately reflect the dynamic change characteristics of the signal, and provide a reliable basis for the subsequent calculation of instantaneous power and loss values; by determining the conduction interval and the switching interval through the gate signal of the SiC-MOSFET device, the source of power loss can be accurately divided, and the calculation accuracy of the loss value is improved; and by establishing a correction relationship between the thermocouple temperature measurement data and the loss value, and constructing a temperature characteristic curve, the influence of the temperature measurement error on the loss value calculation can be eliminated, and the calculation accuracy of the measured switching loss can be improved.

[0104] Step S106: Perform semi-soft switching modulation simulation on the SiC-MOSFET device to obtain simulated switching loss, and construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss to determine the optimal design scheme of the SiC-MOSFET device and complete the switching loss evaluation of the SiC-MOSFET device.

[0105] In this embodiment, the semi-soft switching modulation simulation is performed on the SiC-MOSFET device to obtain the simulated switching loss, the temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, the optimal design scheme of the SiC-MOSFET device is determined, and the switching loss evaluation of the SiC-MOSFET device is completed, which specifically includes:

[0106] The first resonant voltage waveform, the first resonant current waveform, the measured resonant voltage waveform and the measured resonant current waveform are fast Fourier transformed to determine the time offset; the waveforms are synchronized according to the dynamic time warping algorithm in combination with the time offset to determine the phase error sequence; the synchronized waveforms are feature extracted according to the support vector machine regressor of the preset Gaussian kernel function to obtain waveform features, and a root mean square error sequence is constructed based on the waveform features; a resonant frequency weighting matrix is ​​generated according to the root mean square error sequence, and an orthogonal basis vector is constructed based on the preset parasitic parameter sensitivity; a sensitivity calculation interval is set according to the orthogonal basis vector, and when the parameter deviation of the SiC-MOSFET device exceeds the preset rated value nominal range, the parameters are corrected to update the design scheme of the SiC-MOSFET device; a semi-soft switching modulation simulation is performed on the updated SiC-MOSFET device, and the simulated switching loss is extracted from the simulation results; a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed to determine the optimal design scheme of the SiC-MOSFET device, and complete the switching loss evaluation of the SiC-MOSFET device.

[0107] In an optional embodiment, the gate rising edge is set as the time origin for the first resonant voltage waveform, the first resonant current waveform, the measured resonant voltage waveform and the measured resonant current waveform, a fast Fourier transform with a window length that is a multiple of the switching period is performed on the waveform, and the time offset is calculated from the frequency domain phase difference.

[0108] The waveforms are synchronized using a dynamic time warping algorithm with a window length equal to the switching period. The phase error sequence is calculated using the Hamming distance. The degree of waveform alignment is determined when the mean of the error sequence is less than one tenth of the sampling period. The normalized cross-correlation function is used to calculate the similarity of the aligned waveforms.

[0109] A support vector machine regressor with a preset Gaussian kernel function is used to extract features of the synchronized waveform to obtain waveform features. The kernel function bandwidth takes the standard deviation of the waveform amplitude, and a root mean square error sequence is constructed based on the waveform features. A resonant frequency weighted matrix is ​​generated based on the root mean square error sequence, and the principal components of the error are extracted using singular value decomposition. An orthogonal basis vector is constructed through the parasitic parameter sensitivity, and the error distribution characteristics are obtained from the basis vector projection. The error features are iterated five times in a row until convergence to verify stability.

[0110] A parameter sensitivity analyzer is established according to the orthogonal basis vectors, and the sensitivity calculation interval is set to 10% above and below the nominal value of the parameter. The parameters are sorted according to the sensitivity data, and the parameters in the first quarter of the sorting are linearized near the nominal value. If the parameter deviation exceeds the device rated value by 20%, the parameter is corrected using the step-size adaptive Newton iteration method, and the optimality of the corrected parameter is verified through global search to update the design scheme of the SiC-MOSFET device.

[0111] A semi-soft switching modulation simulation is performed on the updated SiC-MOSFET device, the simulation step is set as the sampling period, the simulated switching loss is extracted from the simulation results, a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, and the design deviation is calculated using the switching loss weight matrix. If the deviation is less than 5% of the loss mean for three consecutive iterations, the optimal design scheme of the SiC-MOSFET device is determined from the convergence parameters, and the switching loss evaluation of the SiC-MOSFET device is completed.

[0112] It should be noted that in the waveform alignment process, the rising edge of the gate signal has obvious timing characteristics and is suitable as a time reference point. At a switching frequency of tens of kilohertz, the sampling period is in the nanosecond order, and the fast Fourier transform window length selects four switching periods, which not only ensures frequency resolution but also meets real-time requirements. The dynamic time warping algorithm compensates for waveform distortion by elastically stretching the time axis, the Hamming distance reflects the distribution of phase errors, and the error mean is controlled within one-tenth of the sampling period to ensure synchronization accuracy. The support vector machine regression uses a Gaussian kernel function, and the kernel function bandwidth matches the standard deviation of the waveform amplitude to improve the robustness of feature extraction.

[0113] In SiC-MOSFET device applications, the voltage waveform amplitude is in the kilovolt range, and the current waveform amplitude is in the tens of amperes range. The error weighting matrix highlights the error near the resonant frequency and reflects the dynamic characteristics of the switching process. Singular value decomposition extracts three principal components, covering more than 95% of the total error energy. Parameter sensitivity analysis covers parasitic inductance from ten nanohenries to one hundred nanohenries, and buffer capacitance from one hundred picofarads to one thousand picofarads. The linearization processing interval selects 10% above and below the nominal value to ensure that the local linearity assumption holds. The initial step size of the Newton iteration is 5% of the parameter rated value, and the convergence threshold is set to 1% of the parameter nominal value. The global search verifies the uniqueness of the optimal solution through random initial values.

[0114] It should be noted that in practical applications, when the switching frequency reaches tens of kilohertz, the simulation step size is in the nanosecond range to ensure the calculation accuracy of the resonance process. The temperature coefficient mapping reflects the influence of junction temperature on loss, and the coefficient value increases exponentially with the increase of temperature. The weight of switching loss in the loss weight matrix is ​​higher than that of conduction loss, reflecting the importance of optimizing the switching process. After more than five iterations of optimization, the loss error of the design scheme converges to within 5% of the mean. The long-term stability test includes temperature cycling, load changes, switching frequency adjustment and other working conditions to verify the adaptability of the design scheme. The test results show that when the junction temperature of the device changes from room temperature to 150 degrees, the switching loss increases by no more than 30%, the overvoltage amplitude increases by less than 20%, and the resonant frequency drifts by less than 10%. The comparison before and after parameter optimization shows that the switching loss is reduced by 40%, the overvoltage is reduced by 30%, and the oscillation decay time is shortened by 50%, which fully verifies the effectiveness of the optimized design.

[0115] This embodiment determines the time offset through fast Fourier transform, and synchronizes the waveform using a dynamic time warping algorithm, which can accurately correct the phase error between the measured waveform and the theoretical waveform, providing an accurate basis for subsequent feature extraction and error analysis; feature extraction is performed on the synchronized waveform, so that key feature information can be efficiently and accurately extracted from the waveform, and the error between the waveforms is quantified by constructing a root mean square error sequence, thereby generating a resonant frequency weighted matrix and constructing an orthogonal basis vector, thereby realizing an accurate analysis of the parameter sensitivity of the SiC-MOSFET device; by constructing a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, the influence of temperature on the switching loss is comprehensively considered, the accuracy of the switching loss evaluation is improved, and a design scheme of a SiC-MOSFET device with lower switching loss is obtained, thereby improving the working performance of the SiC-MOSFET device.

[0116] This embodiment obtains the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device, establishes a resonant circuit working model during semi-soft switching modulation, obtains the initial voltage waveform and initial current waveform during the resonance process by solving the model, calculates the voltage stress and current stress of the SiC-MOSFET device during the resonance process, and determines whether the device is in a safe working state. On this basis, this embodiment uses a genetic algorithm to calculate the objective function of minimizing the total switching loss, and optimizes the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device. According to the optimized device parameters, this embodiment adjusts the buffer circuit design, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the SiC-MOSFET device parameters and buffer circuit design. Finally, a semi-soft switching modulation simulation is performed to obtain the simulated switching loss, construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, and determine the optimal design scheme of the SiC-MOSFET device. This embodiment effectively reduces the switching loss of the SiC-MOSFET device and ensures that the device operates within a safe working area.

[0117] Embodiment 2

[0118] Please refer to Figure 2 , which is a structural schematic diagram of a switching loss evaluation system based on semi-soft switching modulation technology provided in an embodiment of the present invention, including: a resonant waveform acquisition module 201, a working state judgment module 202, a parameter optimization module 203, a device optimization module 204, a measured data acquisition module 205 and a switching loss evaluation module 206.

[0119] The resonant waveform acquisition module 201 is used to acquire the parasitic inductance parameters and the buffer capacitance parameters of the SiC-MOSFET device to be evaluated; a resonant circuit working model of the SiC-MOSFET device is constructed according to the parasitic inductance parameters and the buffer capacitance parameters, and the resonant circuit working model is solved to obtain an initial resonant voltage waveform and an initial resonant current waveform.

[0120] In this embodiment, the resonant waveform acquisition module 201 includes: a resonant waveform acquisition unit; the resonant waveform acquisition unit is used to perform high-frequency sampling on the parasitic inductance parameters to obtain a single-cycle waveform; according to the gradient descent algorithm, the single-cycle waveform and the buffer capacitor parameters are parameter matched, and the calculation error of the parameter matching is judged by an adaptive threshold to obtain a parameter combination that meets the preset error requirement; a second-order ordinary differential equation is established according to the parameter combination, the second-order ordinary differential equation is frequency-domain transformed by Laplace transformation, and the characteristic root of the equation is obtained based on the frequency domain space obtained by the frequency domain transformation; the characteristic root of the equation is discretized according to the bilinear transformation to obtain the dynamic response of the resonant circuit. The invention discloses a method for obtaining a resonant circuit working model of a SiC-MOSFET device by using a fifth-order Fourier series expansion of the initial resonant voltage waveform. The method comprises the following steps: first, performing a sliding average processing on the dynamic response data of the resonant circuit according to the working model of the resonant circuit, and performing high-frequency component elimination on the smoothed dynamic response data of the resonant circuit by using a preset Chebyshev filter, so as to obtain an initial resonant voltage waveform output by the Chebyshev filter; second, performing a fifth-order Fourier series expansion on the initial resonant voltage waveform to obtain a voltage spectrum; third, converting the voltage spectrum to a time domain space based on a forward Euler formula to obtain a time domain current response; fourth, performing a zero point correction on the time domain current response according to a preset linear phase compensator to obtain an initial resonant current waveform output by the linear phase compensator.

[0121] The working state judgment module 202 is used to calculate the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judge whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress.

[0122] In this embodiment, the working state judgment module 202 includes: a working state judgment unit; the working state judgment unit is used to perform a differential operation on the initial resonant voltage waveform to obtain a voltage change rate sequence, and extract the instantaneous peak point of the voltage change rate sequence; normalize the instantaneous peak point according to the hyperbolic tangent function to determine the normalized voltage data to obtain the voltage stress of the SiC-MOSFET device; extract the curve envelope of the initial resonant current waveform based on a preset conjugate gradient algorithm, and obtain the current amplitude sequence based on the curve envelope; fit the current amplitude sequence according to the cubic spline difference method to determine the current stress amplitude to obtain the SiC-M The invention discloses a method for detecting the current stress of an SiC-MOSFET device by measuring the current stress of the SiC-MOSFET device; establishing a state-space equation according to the normalized voltage data and the current stress amplitude, and filtering the normalized voltage data and the current stress amplitude based on a preset discrete Kalman filter and the state-space equation to obtain an over-limit duration interval; calculating the stress over-limit degree according to the over-limit duration interval to obtain an over-limit stress value, and integrating the over-limit stress value on the time axis to obtain a stress failure warning threshold from the result of the integral calculation; predicting the stress change trend based on a preset exponential averaging algorithm and a stress failure warning threshold, and comparing the predicted value with the preset safe working area boundary to determine whether the SiC-MOSFET device is in a safe working state.

[0123] The parameter optimization module 203 is used to determine the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform when the SiC-MOSFET device is in a safe working state; taking minimizing the total switching loss as the objective function, the parasitic inductance parameter and the buffer capacitance parameter of the SiC-MOSFET device are optimized according to the genetic algorithm to obtain the first parasitic inductance parameter and the first buffer capacitance parameter.

[0124] In this embodiment, the parameter optimization module 203 includes: a total switching loss calculation unit; the total switching loss calculation unit is used to extract the interval from the rising edge value to the falling edge value of the gate signal in the initial resonant voltage waveform to obtain the conduction interval; subtract the drain inductance voltage drop from the conduction interval sampling data to obtain the on-resistance value;

[0125] The on-resistance value is fitted according to the forgetting factor recursive least squares method, and the on-resistance value is corrected in combination with a preset junction temperature coefficient; the on-current value is obtained, and the instantaneous conduction loss is calculated based on the product of the corrected on-resistance value and the square of the on-current value; the initial resonant current waveform is positioned at the switching instant according to a preset quadratic spline wavelet basis function, the switching time interval is determined, and the instantaneous switching loss is calculated by sliding integration of the voltage and current product in the switching time interval; the instantaneous conduction loss is trapezoidally integrated to determine the single-cycle conduction loss; the instantaneous switching loss is definitely integrated to determine the single-cycle switching loss; when the accumulated fluctuation amplitude of the single-cycle conduction loss and the single-cycle switching loss within a preset period is less than the preset average value ratio, the accumulated fluctuation amplitude is arithmetic averaged, and the average value is compensated in combination with a preset junction temperature correction coefficient to determine the total switching loss of the SiC-MOSFET device.

[0126] In this embodiment, the parameter optimization module 203 includes: a parameter optimization unit; the parameter optimization unit is used to construct a parameter interval based on the parasitic inductance parameter and the buffer capacitor parameter, and use Gray code mapping to encode the parameter interval to obtain a chromosome coding sequence; decode the chromosome coding sequence to obtain a parameter value; substitute the parameter value into the resonant circuit of the SiC-MOSFET device to calculate the switching loss, obtain the switching loss value, and construct a fitness function of the genetic algorithm according to the switching loss value, with minimizing the total switching loss as the objective function, and with the SiC-MOSFET device operating in a safe working area defined by a voltage safety range and a current safety range as a constraint condition, set a crossover point for the chromosome coding sequence in combination with the fitness function, and perform a crossover operation to obtain a first chromosome coding sequence; decode the first chromosome coding sequence to obtain a first parameter value; substitute the first parameter value into the resonant circuit of the SiC-MOSFET device to calculate the first switching loss and the stress excess limit, and obtain an optimal chromosome sequence in combination with a preset loss weighted penalty value; decode the optimal chromosome sequence to obtain a first parasitic inductance parameter and a first buffer capacitor parameter.

[0127] The device optimization module 204 is used to adjust the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain a first resonant voltage waveform and a first resonant current waveform; perform frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimize the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude.

[0128] In this embodiment, the device optimization module 204 includes: a buffer circuit design preliminary adjustment unit; the buffer circuit design preliminary adjustment unit is used to correct the loop damping equation of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitor parameter, and use the fourth-order Runge-Kutta integral to integrate the parasitic inductance voltage drop of the SiC-MOSFET device and the buffer capacitor charging and discharging current to obtain a resonance process waveform; locate the resonance starting point of the resonance process waveform according to a preset double threshold crossing detection method, perform sixth-order Chebyshev polynomial fitting on the post-sampling data of the resonance starting point, and obtain the attenuation rate and frequency The invention relates to a method for realizing a first resonant voltage waveform and a first resonant current waveform. The invention relates to a method for realizing a first resonant voltage waveform and a first resonant current waveform. The invention relates to a method for realizing a first resonant voltage waveform and a first resonant current waveform. The invention relates to a method for realizing a first resonant current ...

[0129] In this embodiment, the device optimization module 204 includes: a frequency domain analysis unit; the frequency domain analysis unit is used to set a Hanning window function according to the first resonant voltage waveform and the first resonant current waveform, and obtain spectrum data based on discrete Fourier transform; five frequency points before and after the main peak in the spectrum data are fitted according to the parabolic interpolation method to determine the resonant frequency; the resonant amplitude is determined according to the amplitude corresponding to the frequency point in the spectrum data and the preset window function correction coefficient; the energy density of the integer points of the resonant frequency is calculated according to the resonant frequency and the resonant amplitude, and the energy density sequence is decomposed in combination with the wavelet packet transform method to obtain the on-off switching frequency band range; the on-off switching frequency band range is reconstructed using an autoregressive spectrum estimator to determine the interference amount; The interference quantity is subjected to frequency range multi-resolution spectrum analysis, the spectrum envelope curve is extracted, and the interference suppression depth is calculated based on the spectrum envelope curve; when the interference suppression depth is less than a preset interference suppression depth threshold, a SiC-MOSFET device parameter optimization objective function is generated according to a preset random forest regressor; a first parasitic inductance parameter and a first buffer capacitor parameter are subjected to resonant frequency constraints and switch stress constraints according to the SiC-MOSFET device parameter optimization objective function, and the SiC-MOSFET device parameter optimization objective function is solved based on a preset step-size adaptive gradient projection method to obtain optimal parameter values; and SiC-MOSFET device parameters and buffer circuit design are optimized according to the optimal parameter values.

[0130] In this embodiment, the measured data acquisition module 205 is used to obtain the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the buffer circuit design.

[0131] In this embodiment, the measured data acquisition module 205 includes: a measured data acquisition unit; the measured data acquisition unit is used to collect the voltage signal and current signal of the switch modulation circuit based on the optimized SiC-MOSFET device parameters and the buffer circuit design, and obtain the sampled waveform data to determine the measured resonant voltage waveform and the measured resonant current waveform; perform Dobesi wavelet denoising on the sampled waveform data, and extract the signal envelope according to the Hilbert transform method; determine the conduction interval and the switching interval based on the gate signal of the SiC-MOSFET device; determine the instantaneous power waveform according to the signal envelope, integrate the instantaneous power waveform in the conduction interval and the switching interval respectively, and determine the loss value; obtain the thermocouple temperature measurement data of the SiC-MOSFET device, and construct a correction relationship between the loss value and the thermocouple temperature measurement data, and construct a temperature characteristic curve corresponding to the correction relationship according to the Gaussian kernel function regressor; obtain the measured switching loss based on the temperature characteristic curve. The switching loss evaluation module 206 is used to perform semi-soft switching modulation simulation on the SiC-MOSFET device, obtain simulated switching loss, and construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss to determine the optimal design scheme of the SiC-MOSFET device and complete the switching loss evaluation of the SiC-MOSFET device.

[0132] In this embodiment, the switching loss evaluation module 206 includes: a switching loss evaluation unit; the switching loss evaluation unit is used to perform fast Fourier transform on the first resonant voltage waveform, the first resonant current waveform, the measured resonant voltage waveform and the measured resonant current waveform to determine the time offset; synchronize the waveforms according to the dynamic time warping algorithm in combination with the time offset to determine the phase error sequence; extract features of the synchronized waveforms according to a support vector machine regressor with a preset Gaussian kernel function to obtain waveform features, and construct a root mean square error sequence based on the waveform features; generate a resonant frequency weighting matrix according to the root mean square error sequence, and An orthogonal basis vector is constructed based on the preset parasitic parameter sensitivity; a sensitivity calculation interval is set according to the orthogonal basis vector, and when the parameter deviation of the SiC-MOSFET device exceeds the preset rated value nominal range, the parameter is corrected to update the design scheme of the SiC-MOSFET device; a semi-soft switching modulation simulation is performed on the updated SiC-MOSFET device, and the simulated switching loss is extracted from the simulation result; a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, the optimal design scheme of the SiC-MOSFET device is determined, and the switching loss evaluation of the SiC-MOSFET device is completed.

[0133] This embodiment obtains the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device, establishes a resonant circuit working model during semi-soft switching modulation, obtains the initial voltage waveform and initial current waveform during the resonance process by solving the model, calculates the voltage stress and current stress of the SiC-MOSFET device during the resonance process, and determines whether the device is in a safe working state. On this basis, this embodiment uses a genetic algorithm to calculate the objective function of minimizing the total switching loss, and optimizes the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device. According to the optimized device parameters, this embodiment adjusts the buffer circuit design, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the SiC-MOSFET device parameters and buffer circuit design. Finally, a semi-soft switching modulation simulation is performed to obtain the simulated switching loss, construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, and determine the optimal design scheme of the SiC-MOSFET device. This embodiment effectively reduces the switching loss of the SiC-MOSFET device and ensures that the device operates within a safe working area.

[0134] In summary, this embodiment obtains the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device, establishes a resonant circuit working model during semi-soft switching modulation, obtains the initial voltage waveform and initial current waveform during the resonance process by solving the model, calculates the voltage stress and current stress of the SiC-MOSFET device during the resonance process, and determines whether the device is in a safe working state. On this basis, this embodiment uses a genetic algorithm to calculate the objective function of minimizing the total switching loss, and optimizes the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device. According to the optimized device parameters, this embodiment adjusts the buffer circuit design, re-simulates the resonance process, and performs frequency domain analysis on the optimized resonant voltage waveform and resonant current waveform, and optimizes the SiC-MOSFET device parameters and buffer circuit design. Finally, a semi-soft switching modulation simulation is performed to obtain the simulated switching loss, construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, and determine the optimal design scheme of the SiC-MOSFET device. This embodiment effectively reduces the switching loss of the SiC-MOSFET device and ensures that the device operates within a safe working area.

[0135] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A switching loss evaluation method based on semi-soft switching modulation technology, characterized in that: include: Obtaining parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device to be evaluated; constructing a resonant circuit working model of the SiC-MOSFET device according to the parasitic inductance parameters and buffer capacitance parameters, and solving the resonant circuit working model to obtain an initial resonant voltage waveform and an initial resonant current waveform; Calculating the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judging whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress; When the SiC-MOSFET device is in a safe working state, the total switching loss of the SiC-MOSFET device is determined according to the initial resonant voltage waveform and the initial resonant current waveform; taking minimizing the total switching loss as the objective function, the parasitic inductance parameter and the buffer capacitance parameter of the SiC-MOSFET device are optimized according to the genetic algorithm to obtain a first parasitic inductance parameter and a first buffer capacitance parameter; Adjusting the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitor parameter to obtain a first resonant voltage waveform and a first resonant current waveform; Performing frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimizing SiC-MOSFET device parameters and a buffer circuit design according to the resonant frequency and the resonant amplitude; Obtain the measured resonant voltage waveform, measured resonant current waveform and measured switching loss according to the optimized SiC-MOSFET device parameters and snubber circuit design; Semi-soft switching modulation simulation is performed on the SiC-MOSFET device to obtain simulated switching loss, a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, the optimal design scheme of the SiC-MOSFET device is determined, and the switching loss evaluation of the SiC-MOSFET device is completed.

2. A switching loss evaluation method based on semi-soft switching modulation technology as claimed in claim 1, characterized in that: The step of constructing a resonant circuit working model of the SiC-MOSFET device according to the parasitic inductance parameters and the buffer capacitance parameters, and solving the resonant circuit working model to obtain an initial resonant voltage waveform and an initial resonant current waveform specifically includes: Performing high frequency sampling on the parasitic inductance parameter to obtain a single-cycle waveform; According to the gradient descent algorithm, the single-cycle waveform and the buffer capacitor parameters are matched, and the calculation error of the parameter matching is judged by the adaptive threshold to obtain the parameter combination that meets the preset error requirement; Establishing a second-order ordinary differential equation according to the parameter combination, performing frequency domain transformation on the second-order ordinary differential equation through Laplace transformation, and obtaining characteristic roots of the equation based on the frequency domain space obtained by the frequency domain transformation; Discretizing the characteristic roots of the equation according to bilinear transformation to obtain dynamic response data of the resonant circuit to construct a resonant circuit working model of the SiC-MOSFET device; According to the resonant circuit working model, the dynamic response data of the resonant circuit is subjected to sliding average processing, and the high-frequency component of the smoothed dynamic response data of the resonant circuit is eliminated by a preset Chebyshev filter to obtain an initial resonant voltage waveform output by the Chebyshev filter; Performing a fifth-order Fourier series expansion on the initial resonant voltage waveform to obtain a voltage spectrum; converting the voltage spectrum to a time domain space based on a forward Euler formula to obtain a time domain current response; The time domain current response is subjected to zero point correction according to a preset linear phase compensator to obtain an initial resonant current waveform output by the linear phase compensator.

3. A switching loss evaluation method based on semi-soft switching modulation technology as claimed in claim 2, characterized in that: The calculating the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judging whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress, specifically includes: Performing a differential operation on the initial resonant voltage waveform to obtain a voltage change rate sequence, and extracting an instantaneous peak point of the voltage change rate sequence; Normalizing the instantaneous peak point according to a hyperbolic tangent function to determine normalized voltage data to obtain a voltage stress of the SiC-MOSFET device; Extracting a curve envelope of the initial resonant current waveform based on a preset conjugate gradient algorithm, and acquiring a current amplitude sequence based on the curve envelope; Fitting the current amplitude sequence according to the cubic spline difference method to determine the current stress amplitude to obtain the current stress of the SiC-MOSFET device; Establishing a state space equation according to the normalized voltage data and the current stress amplitude, and filtering the normalized voltage data and the current stress amplitude based on a preset discrete Kalman filter and the state space equation to obtain an over-limit duration interval; According to the over-limit duration interval, the stress over-limit degree is counted to obtain the over-limit stress value, and the over-limit stress value is integrated on the time axis to obtain the stress failure warning threshold value from the result of the integration calculation; The stress change trend is predicted based on the preset exponential averaging algorithm and stress failure warning threshold, and the predicted value is compared with the preset safe working area boundary to determine whether the SiC-MOSFET device is in a safe working state.

4. The switching loss evaluation method based on semi-soft switching modulation technology according to claim 1, characterized in that: When the SiC-MOSFET device is in a safe working state, determining the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform specifically includes: Extract the interval from the rising edge value to the falling edge value of the gate signal in the initial resonant voltage waveform to obtain the conduction interval; Subtract the drain inductance voltage drop from the conduction interval sampling data to obtain the on-resistance value; Fitting the on-resistance value according to the forgetting factor recursive least square method, and correcting the on-resistance value in combination with a preset junction temperature coefficient; Obtaining the on-current value, and calculating the instantaneous on-loss based on the product of the corrected on-resistance value and the square of the on-current value; The initial resonant current waveform is positioned at the switching instant according to a preset quadratic spline wavelet basis function, a switching time interval is determined, and a voltage-current product in the switching time interval is slidingly integrated to calculate the instantaneous switching loss; Performing trapezoidal integration on the instantaneous conduction loss to determine a single-cycle conduction loss; Performing definite integration on the instantaneous switching loss to determine a single-cycle switching loss; When the accumulated fluctuation amplitude of the single-cycle conduction loss and the single-cycle switching loss within a preset period is less than the preset average value ratio, the accumulated fluctuation amplitude is arithmetic averaged, and the average value is compensated in combination with a preset junction temperature correction coefficient to determine the total switching loss of the SiC-MOSFET device.

5. The switching loss evaluation method based on semi-soft switching modulation technology according to claim 4, characterized in that: The objective function is to minimize the total switching loss, optimize the parasitic inductance parameters and the buffer capacitance parameters of the SiC-MOSFET device according to the genetic algorithm, and obtain the first parasitic inductance parameters and the first buffer capacitance parameters, which specifically include: Constructing a parameter interval based on the parasitic inductance parameter and the buffer capacitance parameter, and encoding the parameter interval using Gray code mapping to obtain a chromosome coding sequence; Decoding the chromosome coding sequence to obtain a parameter value; Substitute the parameter values ​​into the resonant circuit of the SiC-MOSFET device to calculate the switching loss, obtain the switching loss value, and construct the fitness function of the genetic algorithm based on the switching loss value. Taking minimizing the total switching loss as the objective function and taking the SiC-MOSFET device operating in a safe working area defined by a voltage safety range and a current safety range as a constraint condition, setting a crossover point for the chromosome coding sequence in combination with a fitness function, and performing a crossover operation to obtain a first chromosome coding sequence; Decoding the first chromosome coding sequence to obtain a first parameter value; Substituting the first parameter value into the resonant circuit of the SiC-MOSFET device to calculate the first switching loss and the stress excess limit, and obtaining the optimal chromosome sequence in combination with the preset loss weighted penalty value; The optimal chromosome sequence is decoded to obtain a first parasitic inductance parameter and a first buffer capacitance parameter.

6. A switching loss evaluation method based on semi-soft switching modulation technology as claimed in claim 1 or 5, characterized in that: The step of adjusting the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain the first resonant voltage waveform and the first resonant current waveform specifically includes: The loop damping equation of the SiC-MOSFET device is modified according to the first parasitic inductance parameter and the first buffer capacitor parameter, and the parasitic inductance voltage drop of the SiC-MOSFET device and the buffer capacitor charge and discharge current are integrated by using the fourth-order Runge-Kutta integral to obtain the resonance process waveform; Locating the resonance starting point of the resonance process waveform according to a preset double threshold crossing detection method, performing sixth-order Chebyshev polynomial fitting on the post-sampling data of the resonance starting point, and obtaining the attenuation rate and frequency offset; The fitted parameters of the SiC-MOSFET device are corrected according to the gradient descent method, and the buffer circuit design of the SiC-MOSFET device is adjusted according to the correction results; A singular value decomposer is constructed based on the attenuation rate and frequency offset to sort the parameter sensitivity of the SiC-MOSFET device after fitting, and the parameter update value is obtained according to the preset complementary state observer; The cache loop mutual impedance matrix of the SiC-MOSFET device is reconstructed according to the parameter update value, and the admittance equation of the cache loop mutual impedance matrix is ​​solved according to the third-order Bode integral format to obtain a first resonant voltage waveform and a first resonant current waveform.

7. A switching loss evaluation method based on semi-soft switching modulation technology as claimed in claim 6, characterized in that: The performing frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain the resonant frequency and the resonant amplitude, and optimizing the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude, specifically includes: Setting a Hanning window function according to the first resonant voltage waveform and the first resonant current waveform, and acquiring spectrum data based on discrete Fourier transform; The five frequency points before and after the main peak in the spectrum data are fitted according to the parabolic interpolation method to determine the resonant frequency; the resonant amplitude is determined according to the corresponding amplitude of the frequency point in the spectrum data and the preset window function correction coefficient; Calculate the energy density at the integer points of the resonant frequency according to the resonant frequency and the resonant amplitude, and decompose the energy density sequence by combining the wavelet packet transform method to obtain the on-off frequency band range; Reconstructing the conduction switching frequency band using an autoregressive spectrum estimator to determine the interference amount; Performing frequency range multi-resolution spectrum analysis on the interference amount, extracting the spectrum envelope curve, and calculating the interference suppression depth based on the spectrum envelope curve; When the interference suppression depth is less than a preset interference suppression depth threshold, generating a SiC-MOSFET device parameter optimization objective function according to a preset random forest regressor; According to the SiC-MOSFET device parameter optimization objective function, a resonant frequency constraint and a switch stress constraint are performed on the first parasitic inductance parameter and the first buffer capacitor parameter, and the SiC-MOSFET device parameter optimization objective function is solved based on a preset step-size adaptive gradient projection method to obtain an optimal parameter value; SiC-MOSFET device parameters and buffer circuit design are optimized according to the optimal parameter values.

8. The switching loss evaluation method based on semi-soft switching modulation technology according to claim 7, characterized in that: The step of obtaining the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the snubber circuit design specifically includes: Based on the optimized SiC-MOSFET device parameters and buffer circuit design, the voltage signal and current signal of the switch modulation circuit are collected, and the sampling waveform data is obtained to determine the measured resonant voltage waveform and the measured resonant current waveform; Performing Dobesi wavelet denoising on the sampled waveform data and extracting the signal envelope according to the Hilbert transform method; Determining a conduction interval and a switching interval based on a gate signal of the SiC-MOSFET device; Determine an instantaneous power waveform according to the signal envelope, integrate the instantaneous power waveform in the conduction interval and the switching interval respectively, and determine a loss value; Acquire the thermocouple temperature measurement data of the SiC-MOSFET device, construct a correction relationship between the loss value and the thermocouple temperature measurement data, and construct a temperature characteristic curve corresponding to the correction relationship according to a Gaussian kernel function regressor; The measured switching loss is obtained based on the temperature characteristic curve.

9. A switching loss evaluation method based on semi-soft switching modulation technology as claimed in claim 8, characterized in that: The semi-soft switching modulation simulation is performed on the SiC-MOSFET device to obtain the simulated switching loss, to construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, to determine the optimal design scheme of the SiC-MOSFET device, and to complete the switching loss evaluation of the SiC-MOSFET device, specifically including: Performing a fast Fourier transform on the first resonant voltage waveform, the first resonant current waveform, the measured resonant voltage waveform and the measured resonant current waveform to determine a time offset; According to a dynamic time warping algorithm, the waveform is synchronized in combination with the time offset to determine a phase error sequence; Perform feature extraction on the synchronized waveform according to a support vector machine regressor with a preset Gaussian kernel function to obtain waveform features, and construct a root mean square error sequence based on the waveform features; generating a resonant frequency weighting matrix according to the root mean square error sequence, and constructing orthogonal basis vectors based on preset parasitic parameter sensitivities; Setting a sensitivity calculation interval according to the orthogonal basis vectors, and when a parameter deviation of the SiC-MOSFET device exceeds a preset rated value nominal range, correcting the parameter to update a design scheme of the SiC-MOSFET device; Perform semi-soft switching modulation simulation on the updated SiC-MOSFET device and extract simulated switching loss from the simulation results; A temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss is constructed, an optimal design scheme for the SiC-MOSFET device is determined, and a switching loss evaluation of the SiC-MOSFET device is completed.

10. A switching loss evaluation system based on semi-soft switching modulation technology, characterized in that: include: Resonance waveform acquisition module, working state judgment module, parameter optimization module, device optimization module, measured data acquisition module and switching loss evaluation module; The resonant waveform acquisition module is used to acquire the parasitic inductance parameters and buffer capacitance parameters of the SiC-MOSFET device to be evaluated; a resonant circuit working model of the SiC-MOSFET device is constructed according to the parasitic inductance parameters and buffer capacitance parameters, and the resonant circuit working model is solved to obtain an initial resonant voltage waveform and an initial resonant current waveform; The working state judgment module is used to calculate the voltage stress and current stress of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform, and judge whether the SiC-MOSFET device is in a safe working state according to the voltage stress and the current stress; The parameter optimization module is used to determine the total switching loss of the SiC-MOSFET device according to the initial resonant voltage waveform and the initial resonant current waveform when the SiC-MOSFET device is in a safe working state; taking minimizing the total switching loss as the objective function, the parasitic inductance parameter and the buffer capacitance parameter of the SiC-MOSFET device are optimized according to the genetic algorithm to obtain the first parasitic inductance parameter and the first buffer capacitance parameter; The device optimization module is used to adjust the buffer circuit design of the SiC-MOSFET device according to the first parasitic inductance parameter and the first buffer capacitance parameter to obtain a first resonant voltage waveform and a first resonant current waveform; perform frequency domain analysis on the first resonant voltage waveform and the first resonant current waveform to obtain a resonant frequency and a resonant amplitude, and optimize the SiC-MOSFET device parameters and the buffer circuit design according to the resonant frequency and the resonant amplitude; The measured data acquisition module is used to obtain the measured resonant voltage waveform, the measured resonant current waveform and the measured switching loss according to the optimized SiC-MOSFET device parameters and the buffer circuit design; The switching loss evaluation module is used to perform semi-soft switching modulation simulation on the SiC-MOSFET device, obtain simulated switching loss, construct a temperature coefficient mapping relationship between the simulated switching loss and the measured switching loss, determine the optimal design scheme of the SiC-MOSFET device, and complete the switching loss evaluation of the SiC-MOSFET device.

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