Expansion method of oxidation diffusion layer in N12 chip design
By expanding the chip area and placing a 12T Filler in the TSMC 12nm process, the problem of insufficient oxidation diffusion layer density is solved, and the hard rule requirements are met at low cost is achieved, and physical verification violations are avoided.
Patent Information
- Application Number
- CN202411206699.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-20
AI Technical Summary
In the TSMC 12nm process, it is difficult for the prior art to effectively increase the density of the oxidation diffusion layer to meet the hard rules, resulting in high costs or a significant expansion of chip area, and it is impossible to meet the requirements of OD density greater than or equal to 25% at low cost.
By expanding the chip area and placing a self-designed 12T Filler in the expanded portion, ensure its OD density is between 60% and 65% to meet the rules, while only a small chip area is required to avoid OD.DN.1 physical verification violations.
It achieves meeting the density requirements of oxidation diffusion layer at low cost, avoids the occurrence of physical verification violations, and saves the cost of expanding chip area.
Smart Images
Figure CN119167869A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor design, and in particular relates to a method for expanding an oxidation diffusion layer in N12 chip design. Background Art
[0002] TSMC's 12nm process technology is one of its advanced process nodes and is widely used in high-performance computing, mobile devices and other high-performance applications. The OD layer usually refers to the oxide diffusion layer, which is a key layer in the semiconductor manufacturing process.
[0003] In the TSMC 12nm process, there is a hard rule that must be met, that is, the chip OD density must be greater than or equal to 25%, where ALL_OD includes OD (Oxide Diffusion), DOD (dummy Oxide Diffusion) and SR_DOD (Smaller dummy Oxide Diffusion). This can ensure good insulation performance, reduce crosstalk effects, reduce circuit noise, reduce power consumption, and improve device performance. Such a design can help improve chip performance, stability and reliability. On the contrary, if the density of ALL_OD is less than 25%, a physical verification violation of OD.DN.1 will be reported in the Design Rule Check (DRC).
[0004] In the prior art solution, the following measures are taken to solve the violation:
[0005] Method 1: In the early stage of layout and routing, redesign the circuit layout so that OD can cover the entire chip surface more effectively and improve OD density.
[0006] Method 2: After the layout and routing are basically completed, expand the chip area and increase the DOD.
[0007] Among them, method 1 has a high cost because it requires redesigning the circuit. Although method 2 does not require redesigning the circuit, it requires a significant increase in the chip area, which also requires a high cost. Summary of the invention
[0008] Based on this, in order to solve the above technical problems, a method for expanding the oxide diffusion layer in the N12 chip design is provided.
[0009] The technical solution adopted by the present invention is as follows:
[0010] A method for expanding an oxide diffusion layer in an N12 chip design, characterized in that the method is based on a chip design tool and comprises:
[0011] The area of the chip is enlarged, and the area s2 of the enlarged portion of the chip is determined by the following formula:
[0012] (s1*d1+s2*d2) / (s1+s2)=25%
[0013] Wherein, s1 is the original area of the chip, d1 is the original OD density of the chip, and d2 is the OD density of the enlarged portion of the chip, which is greater than or equal to 60% and less than or equal to 65%;
[0014] Design a 12T Filler, wherein the length of the 12T Filler is 0.768 μm, which satisfies the requirement of accommodating 12 wiring tracks in the length direction, and the OD density thereof is greater than or equal to 60% and less than or equal to 65%, and is equal to d2, the 12T Filler comprises an NW layer, an OD layer, a plurality of M0_OD units and a plurality of poly-si units, the OD layer is located on the NW layer, the plurality of M0_OD units and the plurality of poly-si units are respectively arranged on the OD layer in sequence and at intervals along the width direction, the plurality of poly-si units are respectively arranged between two adjacent M0_OD units, the lengths of the M0_OD units and the poly-si units are both 0.768 μm, and the OD density of the 12T Filler = the area of the OD layer / the area of the 12T Filler;
[0015] The 12T filler is placed in the enlarged portion of the chip to make its OD density equal to d2.
[0016] The present invention only needs to slightly expand the chip area and place a self-designed 12T Filler in the expanded chip, so that the OD density of the chip meets the regulatory requirements, while reducing the cost and avoiding the occurrence of OD.DN.1 physical verification violations. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:
[0018] Figure 1 A flow chart of a method for expanding an oxidation diffusion layer in an N12 chip design provided by an embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of the structure of a 12T Filler according to an embodiment of the present invention;
[0020] Figure 3 FIG. 1 is a schematic diagram of a top view of a 12T Filler according to an embodiment of the present invention. DETAILED DESCRIPTION
[0021] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.
[0022] like Figure 1 As shown, the embodiment of the present application provides a method for expanding the oxide diffusion layer in the N12 chip design. The method is based on the chip design tool. In this embodiment, the two tools calibre+icc2 are used. The specific process is as follows:
[0023] S101, enlarging the area of the chip, the area s2 of the enlarged portion of the chip is determined by the following formula:
[0024] (s1*d1+s2*d2) / (s1+s2)=25%
[0025] Wherein, s1 is the original area of the chip, d1 is the original OD density of the chip, and d2 is the ODdensity of the enlarged part of the chip, which is greater than or equal to 60% and less than or equal to 65%. Greater than or equal to 60% is to avoid a substantial increase in the area of the chip, and other violations will occur if it exceeds 65%.
[0026] This step is implemented using the initialize_floorplan command of icc2.
[0027] S102. Design a 12T Filler whose OD density is greater than or equal to 60% and less than or equal to 65%, and is equal to d2.
[0028] Among them, the length of 12T Filler needs to be 0.768μm to meet the requirements in the length direction ( Figure 3 The vertical direction) accommodates 12 wiring tracks, such as Figure 2 and Figure 3As shown, the 12T Filler includes an NW (N well) layer 11, an OD layer 12, a plurality of M0_OD (oxidized diffusion layer of metal layer 0) units 13 and a plurality of poly-si (polycrystalline silicon) units 14, the OD layer 12 is located on the NW layer 11, and the plurality of M0_OD units 13 and the plurality of poly-si units 14 are respectively arranged along the width direction ( Figure 2 and Figure 3 The M0_OD units 13 are arranged in sequence on the OD layer (in the left and right directions), and multiple poly-si units 14 are respectively arranged between two adjacent M0_OD units 13. The lengths of the M0_OD unit and the poly-si unit are both 0.768μm. The OD density of 12T Filler = the area of the OD layer / the area of 12T Filler.
[0029] This step is achieved using the calibre box button.
[0030] In this embodiment, the OD density of d2 and 12T Filler is 65% to maximize the OD density without causing other violations, thereby minimizing the chip expansion area and saving costs.
[0031] For example, the width of the 12T Filler is 0.864 μm, the length is 0.768 μm, and the dimensions of the NW layer, the OD layer, the multiple M0_OD units, and the multiple poly-si units are as follows:
[0032] NW layer: width 0.864 μm, length 0.384 μm;
[0033] OD layer: divided into two parts spaced apart in the length direction, each part has a width of 0.864 μm and a length of 0.25 μm;
[0034] M0_OD unit: width 0.04μm, length 0.768μm, quantity 9;
[0035] Poly-si unit: width 0.016μm, length 0.768μm, number 8.
[0036] The OD density of the 12T Filler is (0.864 μm*0.25 μm*2) / (0.864 μm*0.768 μm)=0.65, that is, 65%.
[0037] It should be noted that the length of the 12T Filler must be 0.768μm, while the width can be adjusted according to the actual situation. The width of each part of the OD layer must be 0.864μm, and the length can be adjusted according to the OD density required. Currently, there are only 6T Filler and 9T Filler available in the cell library of the design tool, so you need to design it yourself in the tool.
[0038] S103. Place 12T filler in the enlarged part of the chip to make its OD density equal to d2.
[0039] The enlarged part of the chip is filled with 12T filler, which is equivalent to the OD density of this part reaching d2.
[0040] This step is implemented using the create_stdcell_filler_no_metal_cmd command of icc2.
[0041] With s1=100mm 2 , d1 = 22.6% of the chip as an example, we take d2 = 65%, through (100 * 22.6% + s2 * 65%) / (100 + s2) = 25%, calculated to get s2 is 4.5mm 2 .
[0042] As a result, the chip is enlarged by 4.5 mm 2 Then design a 12T Filler with an OD density of 65% and 2 The chip expansion part is filled with 12T fillers (4 million) so that the OD density of the chip expansion part is 65%, so that the OD density of the chip meets the rule requirements and avoids physical verification violations.
[0043] From the above, it can be seen that the method for expanding the oxide diffusion layer in the N12 chip design provided in the embodiment of the present application only requires a small expansion of the chip area and placing a self-designed 12T Filler in the expanded chip, so that the OD density of the chip meets the rule requirements. While reducing the cost, it avoids the occurrence of OD.DN.1 physical verification violations.
[0044] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method for expanding an oxide diffusion layer in an N12 chip design, characterized in that: The method is based on chip design tools, which include: The area of the chip is enlarged, and the area s2 of the enlarged portion of the chip is determined by the following formula: (s1*d1+s2*d2) / (s1+s2)=25% Wherein, s1 is the original area of the chip, d1 is the original OD density of the chip, and d2 is the OD density of the enlarged portion of the chip, which is greater than or equal to 60% and less than or equal to 65%; Design a 12T Filler, wherein the length of the 12T Filler is 0.768 μm, which satisfies the requirement of accommodating 12 wiring tracks in the length direction, and the OD density thereof is greater than or equal to 60% and less than or equal to 65%, and is equal to d2, the 12T Filler comprises an NW layer, an OD layer, a plurality of M0_OD units and a plurality of poly-si units, the OD layer is located on the NW layer, the plurality of M0_OD units and the plurality of poly-si units are respectively arranged on the OD layer in sequence and at intervals along the width direction, the plurality of poly-si units are respectively arranged between two adjacent M0_OD units, the lengths of the M0_OD units and the poly-si units are both 0.768 μm, and the OD density of the 12TFiller=the area of the OD layer / the area of the 12T Filler; The 12T filler is placed in the enlarged portion of the chip to make its OD density equal to d2.
2. The method for expanding the oxide diffusion layer in the N12 chip design according to claim 1, characterized in that: The OD density of the d2 and 12T Fillers are both 65%.
3. The method for expanding the oxide diffusion layer in the N12 chip design according to claim 1, characterized in that: The width of the 12T Filler is 0.864 μm and the length is 0.768 μm. The dimensions of the NW layer, OD layer, multiple M0_OD units and multiple poly-si units are as follows: NW layer: width 0.864 μm, length 0.384 μm; OD layer: divided into two parts spaced apart in the length direction, each part has a width of 0.864 μm and a length of 0.25 μm; M0_OD unit: width 0.04μm, length 0.768μm, quantity 9; Poly-si unit: width 0.016μm, length 0.768μm, number 8.