Method for carrying out circuit layout based on predicted distribution rate and training method of distribution rate prediction model

Abstract

The invention provides a method for predicting a distribution rate to carry out circuit layout and a training method of a distribution rate prediction model, and the method for predicting the distribution rate to carry out circuit layout comprises the steps: determining netlist information of a circuit layout sample under a current layout, so as to generate an incidence matrix sample according to the netlist information, and the incidence matrix sample is used for expressing the current layout; determining the position coordinates of each circuit module of the circuit layout sample under the current layout and the position coordinates of the port of each circuit module; generating a characteristic matrix sample according to the position coordinate of each circuit module and the position coordinate of the port of each circuit module; inputting the incidence matrix sample and the characteristic matrix sample into a to-be-trained distribution rate prediction model to obtain a distribution rate prediction value of the circuit layout sample; training a to-be-trained fabric pass rate prediction model based on the fabric pass rate prediction value; and calculating a distribution rate prediction value of the target circuit layout based on the trained distribution rate prediction model so as to optimize the layout of the target circuit layout.

Description

Technical Field

[0001] The present application belongs to the technical field of circuit design, and in particular to a method for performing circuit layout based on predicted routing rate, and a training method for a routing rate prediction model. Background Art

[0002] In analog layout design tools, in order to minimize the chip area and ensure the reliability of circuit performance, efforts are usually made to minimize the total length of the wire network and optimize the delay during the layout phase to ensure that the chip module units can be smoothly wired and connected. However, with the continuous expansion of chip scale and the continuous advancement of process technology, the wiring congestion problem in the wiring phase has become increasingly prominent. Layout optimization often leads to dense wire networks in certain areas, which in turn causes some wiring failures and makes it impossible to achieve a complete routing pass rate.

[0003] When regional congestion occurs in the routing stage, it is necessary to return to the layout stage to readjust the position of the module unit, and this layout adjustment process caused by routing congestion may require multiple cycles. For smaller circuits, the time consumption of this process is acceptable; but as the chip scale and complexity increase, it becomes increasingly difficult to complete all network routing within an acceptable time frame by relying on repeated cycles to optimize the layout.

[0004] Therefore, in recent years, researchers at home and abroad have tried to use a variety of optimization algorithms to reduce routing congestion areas to improve the routing pass rate of the layout. These algorithms usually use routing indicators (such as bus length, routing congestion areas, etc.) as the goal of layout optimization, guiding the layout algorithm to avoid routing congestion areas as much as possible during the layout stage, in order to shorten the layout time. However, since routing indicators are usually estimated approximately, there is often a significant difference between the estimated value and the actual value. Using such an imprecise indicator to guide the layout algorithm is difficult to effectively reduce the congestion area. Summary of the invention

[0005] The solutions provided in this application are as follows:

[0006] A method for circuit layout based on predicted routing rate, comprising:

[0007] Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout;

[0008] Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout;

[0009] Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module;

[0010] Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample;

[0011] Based on the predicted value of the disposition rate, training the disposition rate prediction model to be trained;

[0012] Based on the trained routing rate prediction model, a routing rate prediction value of a target circuit layout is calculated to optimize the layout of the target circuit layout.

[0013] A training method for a spread rate prediction model, comprising:

[0014] Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout;

[0015] Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout;

[0016] Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module;

[0017] Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample;

[0018] Based on the predicted value of the disposition rate, the disposition rate prediction model to be trained is trained.

[0019] It can be seen that in the present application, the netlist information of the circuit layout sample under the current layout is determined to generate an association matrix sample according to the netlist information, and the association matrix sample is used to describe the current layout; the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout are determined; according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module, a feature matrix sample is generated; the association matrix sample and the feature matrix sample are input into the routing rate prediction model to be trained to obtain the routing rate prediction value of the circuit layout sample; based on the routing rate prediction value, the routing rate prediction model to be trained is trained; based on the trained routing rate prediction model, the routing rate prediction value of the target circuit layout is calculated to optimize the layout of the target circuit layout, thereby directly replacing the role of the existing actual router in layout optimization, which can not only greatly shorten the layout adjustment time, but also migrate the model to the situation with a large number of modules, and the performance of the model remains unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a schematic flow chart of a method for performing circuit layout based on predicted routing rate according to an embodiment of the present application.

[0021] Figure 2 A schematic diagram of the principle of characteristic matrix formation for a target circuit layout with 5 circuit modules.

[0022] Figure 3 Schematic diagram of the principle of converting a netlist into an association matrix.

[0023] Figure 4 This is a schematic diagram of prediction using a hypergraph convolutional network as the throughput prediction model, with the linear layer and the nonlinear layer constituting a multilayer perceptron as an example.

[0024] Figure 5 A schematic diagram of the training loss function is obtained for training on 28224 sets of circuit layout samples.

[0025] Figure 6 The figure shows a schematic diagram comparing the layout operation before and after optimization and the actual routing rate obtained by the actual router. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0027] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0028] Figure 1 This is a schematic flow chart of a method for performing circuit layout based on predicted routing rate according to an embodiment of the present application. Figure 1 As shown, it includes:

[0029] Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout;

[0030] Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout;

[0031] Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module;

[0032] Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample;

[0033] Based on the predicted value of the disposition rate, training the disposition rate prediction model to be trained;

[0034] Based on the trained routing rate prediction model, a routing rate prediction value of a target circuit layout is calculated to optimize the layout of the target circuit layout.

[0035] It can be seen that in the present application, the netlist information of the circuit layout sample under the current layout is determined to generate an association matrix sample according to the netlist information, and the association matrix sample is used to describe the current layout; the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout are determined; according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module, a feature matrix sample is generated; the association matrix sample and the feature matrix sample are input into the routing rate prediction model to be trained to obtain the routing rate prediction value of the circuit layout sample; based on the routing rate prediction value, the routing rate prediction model to be trained is trained; based on the trained routing rate prediction model, the routing rate prediction value of the target circuit layout is calculated to optimize the layout of the target circuit layout, thereby directly replacing the role of the existing actual router in layout optimization, which can not only greatly shorten the layout adjustment time, but also migrate the model to the situation with a large number of modules, and the performance of the model remains unchanged.

[0036] Optionally, generating characteristic matrix samples according to the position coordinates of the circuit modules and the position coordinates of the ports of the circuit modules includes: forming a row vector or a column vector of the characteristic matrix samples with the position coordinates of each circuit module and the position coordinates of its ports to generate the characteristic matrix samples.

[0037] To this end, the position coordinates of each circuit module and the position coordinates of its ports are selected to form a row vector or column vector of the feature matrix sample. This design has the following technical benefits:

[0038] (1) The position coordinates of each circuit module and its port are integrated into a row vector or column vector, making the data structure of the feature matrix sample very intuitive. This structure is convenient for computer processing because each row (or column) directly corresponds to a circuit module and its port information, reducing the complexity of data access and processing.

[0039] At the same time, this design also improves the efficiency of data processing. In the subsequent analysis and calculation process, the information of a specific circuit module can be directly accessed through the index without complicated data parsing and conversion.

[0040] (2) This design of feature matrix samples makes it easier for machine learning models to learn and understand the characteristics of circuit layouts. The model can directly capture key information such as the spatial relationship between circuit modules and the potential length of connection paths from these data, thereby improving the accuracy and robustness of predictions.

[0041] In addition, since the information of each circuit module is independent and complete, the model can focus more on learning the mutual influence and layout rules between these modules during training, rather than wasting resources on data parsing and conversion.

[0042] (3) When performing layout adjustment and optimization, the position coordinates and port coordinates of the corresponding circuit module in the feature matrix sample can be easily modified. This modification will be directly reflected in the feature matrix sample without the need to reconstruct or adjust the entire data structure.

[0043] Therefore, designers can quickly try different layout solutions and quickly evaluate the pros and cons of these solutions through feature matrix samples and routing rate prediction models. This flexibility greatly improves the efficiency and accuracy of layout adjustments.

[0044] (4) As the complexity of circuit design increases and the number of modules increases, this design method of feature matrix samples can still maintain good adaptability and scalability, because each new circuit module can be simply added to a new row (or column) in the feature matrix sample, without making major changes to the existing data structure.

[0045] This design approach also enables the model to be easily transferred to circuit designs of different sizes and complexities, maintaining its predictive performance and optimization capabilities.

[0046] Optionally, the position coordinates of each circuit module include a pair of diagonal vertex coordinates; the position coordinates of each circuit module and the position coordinates of its ports are combined into a row vector or column vector of the characteristic matrix sample to generate the characteristic matrix sample, including: combining the diagonal vertex coordinate pairs of each circuit module and the position coordinates of the ports into a row vector or column vector of the characteristic matrix sample.

[0047] To this end, the position coordinates of each circuit module are defined as diagonal vertex coordinate pairs, and these coordinate pairs together with the port position coordinates form the row vector or column vector of the feature matrix sample. This design has the following technical benefits:

[0048] (1) Using diagonal vertex coordinate pairs to describe the location of circuit modules can more accurately reflect the shape and size of the module in two-dimensional space. This description is more accurate than a single center point coordinate or bounding box coordinate because it takes into account the actual shape and orientation of the module.

[0049] During the layout optimization process, accurate position information is crucial to assess the spatial relationship between modules and avoid overlaps and conflicts. The diagonal vertex coordinate pairs provide enough details to enable the model to more accurately predict the routing rate and optimize the layout.

[0050] (2) The diagonal vertex coordinate pairs and port position coordinates are integrated into a row vector or column vector, which simplifies the data processing process. This structured data representation makes subsequent data processing and model training more efficient and direct.

[0051] In the feature matrix sample, the information of each circuit module is independent and complete, which helps to reduce data redundancy and errors and improve the accuracy of data processing.

[0052] (3) The diagonal vertex coordinate pairs provide additional information about the shape and size of the circuit module, which is crucial for the model to predict the routing rate. The model can use this information to evaluate the connection difficulty between modules, predict potential routing conflicts, and optimize the layout accordingly.

[0053] Compared to using only center point coordinates or bounding box coordinates, diagonal vertex coordinate pairs enable the model to more fully understand the characteristics of the circuit layout, thereby improving the accuracy and robustness of the prediction.

[0054] (4) In complex circuit designs, the shapes and sizes of circuit modules may vary, and the layout may be subject to multiple constraints. Using diagonal vertex coordinate pairs to describe module positions allows the model to better adapt to these complex situations.

[0055] The model can evaluate the mutual influence of modules of different shapes and sizes in the layout based on the diagonal vertex coordinate pairs, thereby finding the optimal layout solution. This ability is of great significance for improving the overall performance and reliability of circuit design.

[0056] (5) During the layout optimization process, the model needs to continuously try different layout solutions and evaluate the pros and cons of these solutions. Using diagonal vertex coordinate pairs to describe module positions enables the model to generate and evaluate layout solutions more quickly.

[0057] Because the information of each circuit module is independent and complete, the model can process multiple modules in parallel, thereby accelerating the layout optimization process. This efficiency improvement is of great significance for shortening the design cycle and reducing costs.

[0058] Optionally, the diagonal vertex coordinate pair includes the upper left vertex coordinate, the lower right vertex coordinate, or the lower left vertex coordinate, the upper right vertex coordinate; the upper left vertex coordinate, the lower right vertex coordinate, or the lower left vertex coordinate, the upper right vertex coordinate of each circuit module and the position coordinates of the port form a row vector or column vector of the characteristic matrix sample.

[0059] To this end, the diagonal vertex coordinate pairs of the circuit module are defined as the combination of the upper left vertex coordinates and the lower right vertex coordinates, or the combination of the lower left vertex coordinates and the upper right vertex coordinates, and these coordinates together with the port position coordinates form the row vector or column vector of the feature matrix sample. This design has the following technical benefits

[0060] (1) Using diagonal vertex coordinate pairs (either the upper left corner and the lower right corner, or the lower left corner and the upper right corner) can accurately describe the position and shape of the circuit module in two-dimensional space. This description is more detailed than a single center point or bounding box because it takes into account the extension of the module in both the horizontal and vertical directions.

[0061] This precise spatial positioning helps the model more accurately assess the relative positions of modules, predict routing difficulties, and optimize layout to avoid potential conflicts and overlaps.

[0062] (2) By integrating the diagonal vertex coordinate pairs and port position coordinates into the row vector or column vector of the feature matrix sample, the entire circuit layout can be represented in a concise and efficient way. This representation not only reduces data redundancy, but also makes subsequent data processing and model training more direct and efficient.

[0063] (3) Using diagonal vertex coordinate pairs to describe the shape and position of circuit modules enables the model to learn the impact of modules of different shapes and sizes in the layout. This ability helps the model make accurate predictions and optimizations when faced with new, unseen circuit designs.

[0064] Furthermore, because the model is trained based on this common, structured data representation, it can be more easily transferred to different circuit design domains and application scenarios.

[0065] (4) In actual circuit design, wiring rules can be very complex and involve multiple factors such as signal integrity, electromagnetic compatibility, etc. Using diagonal vertex coordinate pairs to describe the position and shape of circuit modules allows the model to consider these wiring rules more comprehensively and optimize the layout accordingly.

[0066] For example, the model can evaluate the feasibility and cost of different routing paths based on pairs of diagonal vertex coordinates to find the layout solution that satisfies all routing rules and has the lowest cost.

[0067] (5) During the layout optimization process, the model needs to continuously try and adjust layout solutions and evaluate the pros and cons of these solutions. Using diagonal vertex coordinate pairs to describe the position and shape of circuit modules enables the model to generate and evaluate layout solutions more quickly.

[0068] Because the information of each circuit module is independent and complete, the model can process multiple modules in parallel, thereby accelerating the layout optimization process. This efficiency improvement is of great significance for shortening the design cycle and reducing costs.

[0069] Optionally, generating a correlation matrix sample from the netlist information includes: parsing the netlist, acquiring a wire net describing a connection relationship between circuit modules, and generating a correlation matrix sample.

[0070] To this end, we choose to use the netlist information to generate the correlation matrix sample. This step involves parsing the netlist to obtain the wire nets that describe the connection relationship between circuit modules, and constructing the correlation matrix based on this, which has the following technical benefits:

[0071] (1) The association matrix is ​​an intuitive and powerful data structure used to represent the connections or relationships between entities (here, circuit modules). By converting the netlist information into an association matrix sample, it is possible to clearly show which circuit modules are connected and the specific properties of these connections (such as weights, etc.).

[0072] This representation method makes the connection relationship of the circuit clear at a glance, facilitating subsequent analysis, optimization and verification.

[0073] (2) The incidence matrix is ​​a structured data representation that is very suitable for computer processing. After generating an incidence matrix sample, various matrix operations and algorithms can be used to analyze and optimize the circuit layout, such as matrix multiplication, eigenvalue analysis, graph theory algorithms, etc.

[0074] These algorithms and operations can efficiently process large-scale data and improve the automation and efficiency of circuit design.

[0075] (3) In complex circuit designs, the connection relationships between circuit modules may be very complex, including many-to-many connections, hierarchical connections, conditional connections, etc. The association matrix can flexibly represent these complex connection relationships without losing its expressive power due to the complexity of the relationship.

[0076] Through the association matrix, we can clearly see which modules are closely related and which modules are relatively independent, thus providing strong support for layout optimization.

[0077] (4) The process of generating the association matrix is ​​actually the process of modular decomposition and abstraction of the circuit. By dividing the circuit into different modules and describing the connection relationship between these modules, the application of modular design ideas in circuit design can be promoted.

[0078] Modular design helps reduce design complexity and improve design reusability and maintainability. At the same time, it also facilitates subsequent layout optimization and test verification.

[0079] (5) The association matrix sample is one of the important inputs of the automated layout optimization algorithm. By analyzing the connection relationship in the association matrix, the algorithm can evaluate the advantages and disadvantages of different layout schemes and find the optimal layout scheme.

[0080] Automated layout optimization algorithms can significantly improve the efficiency and quality of circuit design and reduce manual intervention and errors. At the same time, it can also cope with large-scale and complex circuit design challenges, providing strong support for the rapid development of modern electronic products.

[0081] Optionally, generating the association matrix sample includes: mapping each circuit module to a node in a hypergraph, and mapping a wire network to a hyperedge in the hypergraph, so as to generate the association matrix sample.

[0082] To this end, we choose to map circuit modules and wire nets into nodes and hyperedges in a hypergraph to generate association matrix samples. This design has the following technical benefits:

[0083] (1) Traditional graph models (such as simple graphs) can usually only represent binary relationships between nodes, that is, each edge connects two nodes. However, in circuit design, a wire network may connect multiple circuit modules, forming a multi-dimensional relationship. The hypergraph model can naturally represent this multi-dimensional relationship, where hyperedges can connect any number of nodes.

[0084] By mapping circuit modules as nodes in a hypergraph and wire networks as hyperedges, the complex connection relationships between circuit modules can be accurately represented, providing an accurate data basis for subsequent layout optimization and verification.

[0085] (2) Hypergraph models are more flexible than traditional graph models. In a hypergraph, nodes and hyperedges can be easily added, deleted, or modified to adapt to dynamic changes in circuit design.

[0086] This flexibility makes it easy to handle various complex circuit structures when generating correlation matrix samples, including modules with multiple inputs and outputs, cross-connected networks, etc.

[0087] (3) The hypergraph model provides a basis for many efficient algorithm analyses. For example, the concepts of hypergraph such as cut sets, covers, and coloring can be used to design optimization algorithms to solve various problems in circuit layout.

[0088] By converting the circuit layout problem into an optimization problem on a hypergraph, the existing graph theory and hypergraph algorithm library can be used to solve it, thereby improving the efficiency and reliability of the algorithm implementation.

[0089] (4) In the hypergraph model, each circuit module is regarded as an independent node, which helps promote the application of modular design ideas in circuit design.

[0090] Modular design helps reduce design complexity and improve design reusability and maintainability. At the same time, it also facilitates subsequent layout optimization and test verification because each module can be analyzed and optimized independently.

[0091] (5) With the continuous development of electronic products, the scale of circuit design is getting larger and larger, and the connection relationship is becoming more and more complex. Hypergraph models can handle large-scale data sets and effectively represent the complex relationships therein.

[0092] By converting the circuit layout problem into an optimization problem on a hypergraph and using efficient algorithms to analyze and solve it, we can meet the challenges of large-scale circuit design and improve the efficiency and quality of design.

[0093] Optionally, mapping each circuit module to a node in a hypergraph and mapping a wire net to a hyperedge in the hypergraph to generate an association matrix sample includes:

[0094] Assigning a first identifier to each node, so as to assign a second identifier to each hyperedge using the first identifiers corresponding to all nodes;

[0095] Fill all first identifiers in ascending order to the first column of the created initial matrix, and fill all second identifiers in ascending order to the first row of the initial matrix;

[0096] According to the relationship between the circuit modules and the wire nets, values ​​are assigned to the elements at the intersection of the first column and the first row in the initial matrix to generate the association matrix sample.

[0097] To this end, a series of steps are used to map circuit modules and wire nets into hypergraphs and generate association matrix samples. This process involves sophisticated data organization and structured processing, which has the following technical benefits:

[0098] (1) Each node (circuit module) is assigned a first identifier, and each hyperedge (line network) is assigned a second identifier, thus achieving a standardized representation of data. This representation method makes the data more unified and easier to manage in subsequent processing.

[0099] The identifiers are assigned in ascending order, which helps maintain data consistency and reduces errors caused by identifier confusion.

[0100] (2) All first identifiers and second identifiers are filled into the first column and first row of the initial matrix respectively. This step is actually to build an index for the association matrix. This indexing method enables each element in the matrix to directly correspond to a specific circuit module and line network, thereby improving the efficiency of data retrieval and processing.

[0101] The construction of the initial matrix provides a clear framework for the subsequent element assignment, making the entire correlation matrix generation process more orderly and efficient.

[0102] (3) According to the relationship between the circuit modules and the wire nets, the elements at the intersection of the first column and the first row in the initial matrix are assigned values. This step directly reflects the connection relationship between the circuit modules. Each non-zero element in the association matrix represents a specific connection, and the value of the element (if applicable) can further represent the strength, weight or other attributes of the connection.

[0103] This intuitive way of expressing connection relationships makes circuit layout, analysis, and optimization easier and more intuitive. By viewing the association matrix, you can quickly understand the overall structure of the circuit and the connections between the various modules.

[0104] (4) Since the hypergraph model can represent multivariate relationships, that is, a hyperedge can connect multiple nodes, this technical solution can well support circuit structures with complex connection relationships. Whether it is a multi-input and multi-output module or a cross-connected network, it can be accurately represented by the association matrix.

[0105] This support for complex circuit structures makes the technical solution more widely applicable and more flexible in practical applications.

[0106] (5) The generated association matrix sample is a structured data set, which is convenient for subsequent processing and analysis using various algorithms and tools. For example, graph theory algorithms can be used for path search and shortest path calculation; matrix operations can also be used for feature extraction and cluster analysis.

[0107] This feature, which facilitates subsequent processing and analysis, makes this technical solution of great application value in the automation, intelligence and efficiency of circuit design.

[0108] Optionally, assigning values ​​to elements at the intersection of the first column and the first row in the initial matrix according to the relationship between the circuit modules and the wire nets to generate the association matrix sample includes:

[0109] If there is a subordinate relationship between the circuit module and the line network, the first eigenvalue is assigned to the element at the intersection of the first identifier corresponding to the circuit module in the first column and the second identifier corresponding to the line network in the first row in the initial matrix;

[0110] If there is no affiliation between the circuit module and the line network, the element at the intersection of the first identifier corresponding to the circuit module in the first column and the second identifier corresponding to the line network in the first row in the initial matrix is ​​assigned a second eigenvalue, which is different from the first eigenvalue.

[0111] To this end, different eigenvalues ​​are assigned to the elements in the initial matrix to represent the affiliation between the circuit modules and the wire nets. This step further refines the construction process of the association matrix and has the following technical benefits:

[0112] (1) By assigning the first eigenvalue to the elements at the intersection of the circuit module and the wire net that have a membership relationship, and assigning the second eigenvalue to the elements at the intersection that do not have a membership relationship, the connection relationship is clearly identified. This identification method enables the association matrix to clearly reflect the connection status between the circuit module and the wire net, providing an accurate data basis for subsequent analysis and optimization.

[0113] (2) The process of assigning eigenvalues ​​can be automated through programming without human intervention. This makes the generation and updating of association matrices more efficient and reliable in large-scale circuit design. At the same time, automated eigenvalue assignment also facilitates subsequent automated analysis and optimization, such as using algorithms to automatically detect potential connection problems and optimize circuit layout.

[0114] (3) In complex circuit design, the relationship between circuit modules and wire networks may be very complex, including many-to-many connections, hierarchical connections, etc. By assigning different eigenvalues ​​to represent different connection states, this technical solution can flexibly handle these complex connection relationships. Whether it is a simple point-to-point connection or a complex network structure, it can be accurately represented by the association matrix.

[0115] (4) Each circuit module in the association matrix is ​​regarded as an independent entity (indicated by the first identifier), and the wire network serves as a bridge connecting these entities. This representation method helps promote the application of modular design ideas in circuit design. By analyzing and optimizing the connection relationship in the association matrix, independent analysis and optimization of circuit modules can be achieved, improving the reusability and maintainability of the design.

[0116] (5) After assigning different eigenvalues, the association matrix can not only be used to represent the relationship between circuit modules and wire nets, but also support a variety of analysis requirements. For example, eigenvalues ​​can be used for cluster analysis to group circuit modules with similar connection characteristics; eigenvalues ​​can also be used for path search and shortest path calculation. Meeting these analysis requirements helps to further explore the potential of circuit design and improve the performance and quality of the design.

[0117] Optionally, the first eigenvalue and the second eigenvalue are selected from 0 and 1, so that the incidence matrix sample is a 01 matrix.

[0118] To this end, 0 and 1 are selected as the first eigenvalue and the second eigenvalue to generate a 01 matrix as a correlation matrix sample, which has the following technical benefits:

[0119] (1) Using 0 and 1 as eigenvalues ​​greatly simplifies the data processing process. In a 01 matrix, each element can only be 0 or 1, which reduces the complexity of the data type and makes subsequent data processing and analysis more efficient.

[0120] The simplicity of the 01 matrix also reduces the storage space requirements because each element only needs one bit to be represented, which is particularly important for large-scale circuit design.

[0121] (2) The 01 matrix is ​​intuitive and easy to read. In the matrix, 0 usually means "no connection" or "does not belong", while 1 means "connected" or "belongs". This representation method enables the association matrix to clearly reflect the connection relationship between circuit modules and wire nets.

[0122] Designers can easily understand the overall structure of the circuit and the connections between various modules by viewing the 01 matrix without complicated explanations or additional instructions.

[0123] (3) The 01 matrix supports various logical operations, such as AND, OR, NOT, etc. These logical operations can be directly applied to the 01 matrix to further analyze and process the circuit connection relationship.

[0124] For example, logical operations can be used to detect potential connection problems (such as isolated circuit modules or unconnected wire nets), or to optimize circuit layout to reduce connection complexity.

[0125] (3) Many efficient algorithms are designed based on 01 matrices. For example, many algorithms in graph theory (such as the shortest path algorithm, maximum flow algorithm, etc.) can be directly applied to the incidence matrix represented by the 01 matrix.

[0126] The efficiency of these algorithms makes it possible to perform complex circuit analysis and optimization on the correlation matrix, thereby improving the efficiency and quality of circuit design.

[0127] (4) The simplicity of the 01 matrix makes it easier to implement modular design ideas in circuit design. Each circuit module can be regarded as an independent entity (represented by a row or column in the matrix), and the connection relationship between modules is represented by the element values ​​in the matrix.

[0128] This representation helps designers break down complex circuit designs into smaller, more manageable modules, thereby improving the reusability and maintainability of the design.

[0129] Optionally, the step of inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample includes:

[0130] Inputting the association matrix sample into the routing rate prediction model to be trained to calculate the node degree matrix, the hyperedge weight matrix and the hyperedge degree matrix;

[0131] Performing feature fusion on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix sample and the feature matrix sample to obtain sample layout features;

[0132] Calculating a predicted value of the routing rate of the circuit layout sample according to the layout features of the sample layout;

[0133] Determine whether the predicted value of the routing rate meets the preset standard. If so, the training ends. Otherwise, input the new association matrix sample and the feature matrix sample into the routing rate prediction model to be trained after the model parameters are updated to update the routing rate prediction value of the circuit layout sample, and again determine whether the updated routing rate prediction value meets the preset standard. If so, the training ends. Otherwise, input the updated association matrix sample and the feature matrix sample into the routing rate prediction model to be trained after the model parameters are updated again to update the routing rate prediction value of the circuit layout sample, and so on until the updated routing rate prediction value meets the preset standard.

[0134] The association matrix samples are input into the cloth rate prediction model to be trained to calculate the node degree matrix, hyperedge weight matrix and hyperedge degree matrix. The general technical processing process is: the cloth rate prediction model performs hypergraph convolution operation on the association matrix samples, mainly including: extraction, fusion and transformation. Among them, each node sends its own feature information to the associated node after transformation to complete the extraction and transformation of node features; the neighboring nodes gather the received feature information to realize the feature fusion of the node local structure information; the previous information is gathered and nonlinearly transformed to enhance the performance of the model, so as to obtain:

[0135] For the association matrix H corresponding to M rows and N columns, that is, M circuit modules and N wire nets, the hyperedge weight matrix W is: the diagonal matrix W ii =1, i from 1 to N; node degree matrix D: diagonal matrix, i ranges from 1 to M; hyperedge degree matrix B: diagonal matrix, i ranges from 1 to N.

[0136] To this end, a series of steps are used to input the association matrix samples and feature matrix samples into the routing rate prediction model to be trained, and the routing rate of the circuit layout samples is predicted by combining the feature fusion of the node degree matrix, the hyperedge weight matrix and the hyperedge degree matrix. At the same time, the iterative training method is used to continuously optimize the model prediction results, which has the following technical benefits:

[0137] (1) By calculating the node degree matrix, the hyperedge weight matrix and the hyperedge degree matrix, and performing feature fusion on them with the association matrix samples and the feature matrix samples, the model can comprehensively consider the multi-dimensional features of nodes (circuit modules) and hyperedges (wire networks) in the circuit layout. This multi-dimensional feature fusion helps to more comprehensively capture the layout characteristics of the circuit layout, thereby improving the accuracy of the routing rate prediction.

[0138] (2) By adopting an iterative training method, the model can continuously adjust and optimize its own parameters according to the difference between the predicted results and the actual standards. This training method enables the model to gradually approach the actual distribution of the distribution of the distribution rate, improving the stability and reliability of the prediction. At the same time, iterative training also helps to discover potential problems in the model and improve the model performance through continuous correction.

[0139] Optionally, the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix samples and the feature matrix samples are subjected to feature fusion to obtain sample layout features, including: performing a convolution operation on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix samples and the feature matrix samples to perform feature fusion and obtain sample layout features.

[0140] To this end, the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix sample and the feature matrix sample are convolved to achieve feature fusion to obtain the sample layout features. This step brings many technical benefits:

[0141] (1) Convolution operations can effectively extract local features while maintaining the spatial structure of the data. In circuit layout, the local connectivity between nodes and hyperedges is crucial for the prediction of routing rate. Through convolution operations, the model can capture these local features, such as the connection density of nodes and the weight distribution of hyperedges, thereby providing strong support for subsequent routing rate prediction.

[0142] (2) Feature fusion and enhancement are achieved through a multi-layer convolutional network. Convolution operations are performed on the node degree matrix, hyperedge weight matrix, hyperedge degree matrix, association matrix samples, and feature matrix samples to fuse the different feature information in these matrices to form a more comprehensive and rich sample layout feature. This feature fusion helps the model better understand the layout structure of the circuit layout and improve the accuracy of the routing rate prediction.

[0143] (3) Compared with other feature fusion methods (such as fully connected layers), convolution operations have lower computational complexity and fewer parameters. This advantage is particularly evident when processing large-scale circuit layout data. By performing feature fusion through convolution operations, the computational cost of the model can be reduced while ensuring prediction accuracy, thereby improving the efficiency of training and prediction.

[0144] (4) The layout of circuits is often very complex, containing a large number of nodes and hyperedges, and the connections between them are intricate. Through feature fusion through convolution operations, the model can adaptively handle this complexity, capture key features in the layout, and effectively represent and predict them. This makes the model more robust and generalizable when dealing with complex circuit layouts.

[0145] (5) Convolution operations can be easily embedded in deep learning models to achieve end-to-end training. This means that the model can learn the final prediction results directly from raw data (such as association matrices and feature matrices) without complex data preprocessing or feature engineering. This end-to-end training method simplifies the model design process, improves training efficiency, and helps discover potential patterns and features in the data.

[0146] (6) Convolution operations are usually combined with back-propagation algorithms to optimize model parameters. During the training process, the model adjusts the weights and biases of the convolution kernel based on the error between the predicted result and the actual label, thereby continuously optimizing the model's prediction performance. This optimization process enables the model to gradually approach the true distribution of the rate of spread, improving the accuracy and stability of the prediction.

[0147] Optionally, based on the set stacked convolutional layers, a convolution operation is performed on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix samples and the feature matrix samples to perform feature fusion and obtain sample layout features.

[0148] Optionally, for any convolutional layer in the stacked convolutional layers, a convolution operation is performed on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix sample and the feature matrix sample according to the following formula:

[0149] or X l+1 =σ(HW H T X l P)

[0150] Where D is the node degree matrix, H is the association matrix sample, W is the hyperedge weight matrix, B is the hyperedge degree matrix, P is the weight matrix connecting the l-layer convolution and the l+1-layer convolution, X l and X l+1 They are the feature expressions laid out on the l-layer convolution and the l+1-layer convolution respectively, σ is a nonlinear activation function, l is greater than or equal to 1, and the feature expression of the last convolution layer is the layout feature of the sample layout.

[0151] To this end, a convolution operation is performed on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix sample and the feature matrix sample based on a set stacked convolution layer to achieve feature fusion and obtain sample layout features. This method combines a variant or similar idea of ​​a graph convolutional network (GCN) and introduces a specific formula to perform the convolution operation, which has the following technical benefits:

[0152] (1) Traditional convolutional neural networks (CNNs) are mainly applicable to data in Euclidean space (such as images), while graph structure data such as circuit layout has non-Euclidean characteristics. By introducing graph structure-specific information such as the node degree matrix, hyperedge weight matrix, hyperedge degree matrix, association matrix samples, and feature matrix samples, and combining convolution operations with stacked convolution layers, this method can effectively process graph structure data and capture the complex relationships between nodes and hyperedges.

[0153] (2) The design of stacked convolutional layers allows the model to gradually extract and fuse feature information in the graph structure through multiple layers of convolution operations. Each layer of convolution further processes and abstracts the feature expression of the previous layer, thereby enhancing the understanding of the layout features of the graph structure. This layer-by-layer feature fusion method helps the model more accurately predict the routing rate of the circuit layout.

[0154] (3) The D^(-1 / 2) and B^(-1) terms in the formula play a normalization role, which helps to balance the influence of different nodes in the convolution operation and prevent certain highly connected nodes from dominating the feature propagation process. This normalization process helps the model to more fairly consider the contribution of each node to the overall layout and improve the accuracy of the prediction.

[0155] The P matrix in the formula (4) serves as the weight matrix connecting the l-layer convolution and the l+1-layer convolution, providing additional flexibility for the model. By adjusting the weights of the P matrix, the model can learn the best combination of feature expressions between different layers, thereby further optimizing the prediction performance.

[0156] (5) In the formula, σ represents a nonlinear activation function, such as ReLU. The introduction of nonlinear activation functions enables the model to learn complex nonlinear relationships and improve the model's expressiveness and generalization capabilities. This is especially important for processing complex circuit layout data.

[0157] (6) This method supports an end-to-end training process, that is, the model can directly learn the final prediction results from the original graph structure data. This training method simplifies the model design process, reduces the need for manual intervention, and helps the model automatically discover potential patterns and features in the data.

[0158] (7) By adjusting parameters such as the number of stacked convolutional layers, the size and number of convolution kernels, this method can flexibly adapt to circuit layout data of different scales and complexities. At the same time, since this method is based on a variant or similar idea of ​​graph convolutional networks, it can be easily combined with other graph neural network models or deep learning techniques to further improve the prediction performance.

[0159] Optionally, calculating the routing rate prediction value of the circuit layout sample according to the layout features of the sample layout includes:

[0160] Compressing the sample layout features based on a linear layer to obtain a compressed feature vector;

[0161] The compressed feature vector is nonlinearly transformed based on a nonlinear layer to obtain the predicted value of the spread rate.

[0162] Specifically, the linear layer is, for example, a fully connected layer; in addition, considering that the prediction value of the throughput rate must be in the interval [0,1], sigmoid is used as the nonlinear layer.

[0163] To this end, the sample layout features are compressed through a linear layer (such as a fully connected layer), and the compressed feature vector is nonlinearly transformed through a nonlinear layer (such as a sigmoid function) to obtain a predicted value of the routing rate. This step has the following technical benefits:

[0164] (1) The linear layer (such as the fully connected layer) plays a role in feature compression and dimensionality reduction. Since the sample layout features may contain a large amount of information, using them directly for prediction may result in high computational complexity and easy overfitting. Compression through the fully connected layer can map high-dimensional features to low-dimensional space while retaining key information that is useful for prediction of the routing rate. This helps reduce the computational burden of the model and improves prediction efficiency.

[0165] (2) The introduction of nonlinear layers (such as the sigmoid function) provides the model with powerful nonlinear transformation capabilities. Since the Bouth rate prediction problem is essentially a complex nonlinear problem, simple linear models often cannot accurately capture its internal laws. The sigmoid function can compress any real value into the interval [0,1]. This feature is very suitable for predicting probability values ​​or proportion values ​​(such as the Bouth rate). By performing nonlinear transformations with the sigmoid function, the model can learn more complex nonlinear relationships, thereby improving the accuracy and reliability of predictions.

[0166] (3) Another important benefit of using the sigmoid function as a nonlinear layer is that it can naturally limit the predicted value to the interval [0,1]. This is very suitable for the prediction of the propagation rate, because the propagation rate itself is a proportional value between 0 (completely unable to propagate) and 1 (completely propagating). By transforming with the sigmoid function, the predicted value output by the model can be directly interpreted as the probability value of the propagation rate, which is easy to understand and apply.

[0167] (4) This technical solution combines the advantages of linear and nonlinear layers, allowing the model to flexibly adapt to different prediction tasks while maintaining a certain level of complexity. By adjusting the parameters of the linear and nonlinear layers (such as the number of neurons, activation function, etc.), the prediction performance of the model can be further optimized to meet different application requirements.

[0168] (5) The linear layer and nonlinear layer in this technical solution are commonly used components in deep learning, with mature implementation and training algorithms. Therefore, in practical applications, it is very convenient to use existing deep learning frameworks (such as TensorFlow, PyTorch, etc.) to implement and train models. This reduces the difficulty and cost of technical implementation and improves the usability and maintainability of the model.

[0169] Optionally, the method further includes: calculating whether the mean square error between the predicted value of the transmission rate and the actual value of the sample reaches a set error threshold; if so, it is determined that the preset standard is met; otherwise, it is determined that the preset standard is not met.

[0170] To this end, the mean square error (MSE) between the predicted value of the spread rate and the actual value of the sample (or actual value, label value) is introduced to determine whether it reaches the set error threshold as a means of determining whether the model prediction performance meets the preset standard, which brings the following technical benefits:

[0171] (1) Mean square error can quantify the difference between the model's predicted value and the actual value. By calculating MSE, we can get a specific value to evaluate the model's prediction accuracy. This quantitative evaluation method makes the evaluation of model performance more objective and comparable.

[0172] (2) Setting an error threshold as the basis for determining whether the model meets the preset standards sets a clear goal for model training and evaluation. This helps maintain consistency during the model development process and ensures that the model performance meets the established requirements.

[0173] (3) By comparing MSE with the error threshold, we can quickly determine whether the model meets the preset standards. If not, it means that the model needs further adjustment and optimization. This instant feedback mechanism helps to quickly iterate the model and improve development efficiency.

[0174] (4) During model training, the changing trend of MSE can reflect the model fit. If the MSE is low on the training set but high on the validation set, it may indicate that the model is overfitting. On the contrary, if the MSE is high on both the training set and the validation set, it may indicate that the model is underfitting. By monitoring the MSE and comparing it with the error threshold, we can detect and correct these problems in a timely manner.

[0175] (5) By ensuring that the MSE of the model is below the set error threshold, we can improve the reliability of the model. This means that the model can more accurately predict the routing rate of the circuit layout in actual applications, thereby reducing the risk caused by inaccurate predictions.

[0176] (6) When there are multiple candidate models, we can select the model with the best performance by comparing their MSE. Setting the error threshold as a screening condition helps to quickly exclude models with poor performance and narrow the selection range.

[0177] (7) MSE, as one of the optimization objectives, can guide the model to continuously optimize its parameters during the training process to reduce the prediction error. By continuously iterating the training process and adjusting the model parameters, we can gradually reduce the MSE and make it close to or below the error threshold, thereby improving the prediction performance of the model.

[0178] For example, in a scenario, there are n target circuit layouts, and there are n corresponding routing rate prediction values ​​(y1, y2, ..., y n ), forming a prediction vector value y = (y1, y2, ..., y n ), corresponding to n actual sample values (e.g. obtained by a real router), recorded as the sample actual value vector

[0179] The mean square error between the two is:

[0180] Wherein, n is greater than or equal to 1.

[0181] Optionally, if the target circuit layout has N basic layouts, the method further includes:

[0182] Generate N extended layouts based on each basic layout, where N is an integer greater than or equal to 1;

[0183] Determine the association matrix and feature matrix under each basic layout and each extended layout;

[0184] Based on the trained routing rate prediction model, a routing rate prediction value of a target circuit layout is calculated to optimize the layout of the target circuit layout, including:

[0185] For each basic layout and each extended layout, the corresponding association matrix and feature matrix are input into the trained routing rate prediction model to calculate the routing rate of the target circuit layout under each basic layout and each extended layout;

[0186] The layout of the target circuit layout is optimized according to the routing rates of the target circuit layout under all basic layouts and all extended layouts.

[0187] To this end, in the case where the target circuit layout has multiple basic layouts, by generating an extended layout, determining the association matrix and the feature matrix, and using the trained routing rate prediction model to calculate and optimize the layout, this method brings many technical benefits as follows:

[0188] (1) By generating multiple extended layouts for each basic layout, this method can significantly expand the search space of layout design. This helps to discover potential better layout solutions because the extended layout may contain certain features or optimization points that the basic layout does not have.

[0189] (2) Each extended layout under each basic layout is evaluated in detail, including determining its association matrix and feature matrix, and inputting them into the trained routing rate prediction model to calculate the routing rate. This refined evaluation method can more accurately reflect the impact of different layout schemes on the routing rate and provide a reliable basis for layout optimization.

[0190] (3) Based on the calculation results of the routing rate prediction model, the routing rates of different layout schemes can be quickly compared to select the optimal layout scheme. This method is more efficient than the traditional trial and error method or heuristic algorithm because it can directly use the results of model prediction to guide the layout optimization process.

[0191] (4) In actual circuit design, layout optimization is a time-consuming and costly process. By introducing the routing rate prediction model, a large number of layout schemes can be quickly evaluated and optimized without increasing the actual manufacturing cost. This helps to reduce design costs and improve design efficiency.

[0192] (5) By optimizing the layout, the routing rate of the circuit layout can be significantly improved, thereby improving the performance and reliability of the circuit. A high routing rate means that the signal lines and power lines in the circuit can be connected more smoothly, reducing signal interference and power loss, and improving the overall performance of the circuit.

[0193] Optionally, generating N extended layouts based on each basic layout includes: adding random perturbations to each basic layout to generate N extended layouts.

[0194] Optionally, adding random perturbations to each basic layout to generate N extended layouts includes: for the obtained N*N extended layouts, taking the first N-1 layouts with the highest routing rates and one layout with the lowest routing rate to form the N extended layouts.

[0195] Optionally, optimizing the layout of the target circuit layout according to the routing rates of the target circuit layout under all basic layouts and all extended layouts includes:

[0196] According to the routing rates of all basic layouts, the average routing rate of the basic layouts is calculated;

[0197] According to the routing rates of all extended layouts, the average routing rate of the extended layout is calculated;

[0198] If the average routing rate of the extended layout is less than the average routing rate of the basic layout, the basic layout remains unchanged and directly proceeds to the next round of iteration; if the average routing rate of the extended layout minus the average routing rate of the basic layout is greater than the set routing rate difference threshold, the basic layout is replaced by the extended layout; if the average routing rate of the extended layout minus the average difference rate of the basic layout is less than or equal to the set routing rate difference threshold, the basic layout is replaced by the extended layout with a set probability.

[0199] To this end, for the layout optimization process of the target circuit layout, the average routing rate of the basic layout and the extended layout is counted, and the difference between them is used to decide whether to update the basic layout. This strategy brings the following technical benefits:

[0200] (1) By comparing the average routing rate of the extended layout with the average routing rate of the basic layout and setting a routing rate difference threshold, this method helps avoid blindly trying all extended layouts, thereby improving the efficiency and pertinence of the optimization process.

[0201] (2) When the average routing rate of the extended layout is significantly higher than that of the basic layout (i.e., the difference is greater than the set routing rate difference threshold), the method will update these extended layouts to the basic layout. This dynamic update mechanism can ensure that the latest and better layout solutions are always considered during the optimization process, thereby promoting the continuous improvement of layout quality.

[0202] (3) If the average routing rate of the extended layout is not much different from that of the basic layout (i.e., the difference is less than or equal to the set routing rate difference threshold), the method allows the extended layout to replace the basic layout with a set probability. This flexible selection method helps to avoid introducing too much unnecessary computational burden while maintaining optimization efficiency.

[0203] (4) By re-executing the calculation and optimization steps based on the trained routing rate prediction model, the method can achieve iterative optimization of the layout. This iterative process can continuously approach the optimal layout solution and improve the routing rate and overall performance of the circuit layout.

[0204] (5) Compared with blindly trying all possible layout combinations, this method significantly improves the efficiency of the optimization process by intelligently selecting and updating the basic layout. It can explore more optimization space in a limited time and converge to the optimal solution faster.

[0205] (6) This method allows designers to adjust the routing rate difference threshold and other parameters according to actual needs to adapt to different design scenarios and constraints. This design flexibility helps to meet the customized needs of different customers and improve the market competitiveness of products.

[0206] Optionally, replacing the basic layout with an extended layout with a set probability includes:

[0207] Calculating the probability of the extended layout replacing the basic layout based on the average routing rate of the extended layout and the average routing rate of the basic layout;

[0208] Based on the probability of the extended layout replacing the basic layout, all the extended layouts are used to replace the basic layout.

[0209] To this end, by optimizing the placement of the target circuit layout, these strategies provide the following technical benefits:

[0210] (1) The update probability is calculated based on the average routing rate of the extended layout and the average routing rate of the basic layout. This method can more finely control the replacement of the basic layout with the extended layout. The probabilistic selection not only considers the improvement of the routing rate, but also implicitly considers the relative advantages and disadvantages of different extended layouts, which helps to make a more reasonable choice among multiple potential optimization solutions.

[0211] Probabilistic selection also increases the diversity of layouts and avoids premature convergence to local optimal solutions. By allowing a certain probability to replace the basic layout with an extended layout, the algorithm can explore a wider solution space and increase the possibility of finding the global optimal solution.

[0212] Optionally, the probability of the extended layout replacing the basic layout is calculated based on the average routing rate of the extended layout and the average routing rate of the basic layout according to the following formula:

[0213]

[0214] R base is the average routing rate of the basic layout, R candidate is the average routing rate of the extended layout, threadhold is the threshold, T ori is the initial temperature of simulated annealing, T cur is the current temperature of simulated annealing.

[0215] To this end, the probability (P) of replacing the basic layout with the extended layout is calculated by combining the average routing rate of the extended layout (candidate layout) with the average routing rate of the basic layout, as well as the current temperature and initial temperature of the simulated annealing algorithm, which has the following technical benefits:

[0216] (1) It effectively balances the trade-off between exploring new solutions and using the current optimal solution. candidate Significantly higher than R base When the candidate layout has a higher routing rate, the probability P will increase, encouraging the algorithm to accept this better layout as the new basic layout. This promotes the exploration of new solutions.

[0217] At the same time, the temperature T cur of the simulated annealing algorithm gradually decreases over time, making the algorithm more inclined to accept the current optimal solution or a solution close to the optimal solution in the later stage of the search, thereby reducing unnecessary jumps between inferior solutions and improving optimization efficiency.

[0218] (2) By setting a threshold, the algorithm designer can control the algorithm's sensitivity to improvements in the routing rate. A smaller threshold will make the algorithm more likely to accept candidate layouts with slightly improved routing rates, thereby increasing the diversity of the solution; a larger threshold will make the algorithm more picky and only accept layouts with significantly improved routing rates, helping it converge to the global optimal solution more quickly.

[0219] (3) The Tori / Tcur term in the formula associates the acceptance probability P with the current temperature Tcur of the simulated annealing algorithm. In the early stage of the search, the temperature is high, and the algorithm is more likely to accept poor candidate layouts, thus jumping out of the local optimal solution; as the search progresses, the temperature gradually decreases, and the algorithm is more and more inclined to accept better layouts, which helps to stably approach the global optimal solution.

[0220] (4) Through this probabilistic selection mechanism, the algorithm is able to more intelligently select candidate layouts to update as the basic layout. This avoids blindly trying candidate layouts, thereby improving the efficiency of the optimization process.

[0221] (5) Since the algorithm considers multiple factors (such as routing rate differences, current temperature, thresholds, etc.) in the decision-making process, it has stronger adaptability to different types of design problems and constraints. This flexibility makes the algorithm more robust when facing complex and changing layout design problems.

[0222] The present application also provides a training method for a delivery rate prediction model, which comprises:

[0223] Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout;

[0224] Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout;

[0225] Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module;

[0226] Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample;

[0227] Based on the predicted value of the disposition rate, the disposition rate prediction model to be trained is trained.

[0228] The following combination Figure 2-Figure 6 , for the above application Figure 1 The embodiments are described below.

[0229] See also Figure 2 As described, for a certain target circuit layout, there are 5 circuit modules on it, represented by i, which is greater than or equal to 1 and less than or equal to 5 (xi1, yi1) is the coordinate of the lower left vertex, (xi2, yi2) is the coordinate of the upper right vertex, (xi3, yi3) is the center coordinate of the circuit module, (xi4, yi4) is the center coordinate of the first port in the circuit module as its position coordinate, and (xi4, yi4) is the center coordinate of the second port in the circuit module as its position coordinate.

[0230] To this end, a coordinate matrix is ​​formed as a characteristic matrix in the above manner;

[0231] See also Figure 3 The netlist records M1, M2, M3...M5, which represent 5 circuit modules respectively. Link1 represents line network 1, link2 represents line network 2, and the numbers represent the line ports. For example, the number 2 under M1 in link1 means that port 2 of M1 is in line network 1.

[0232] To this end, an association matrix is ​​generated in the above manner. If Mij=0, the i-th node belongs to the j-th hyperedge, indicating that circuit module i belongs to network j, where j is a positive number greater than or equal to 1, representing the number of networks.

[0233] Refer to the above Figure 1 The flow chart of the embodiment is as follows Figure 4 As shown. The transmission rate prediction model is taken as a hypergraph convolutional network, and the above linear layer and nonlinear layer constitute a multi-layer perceptron as an example for explanation.

[0234] See also Figure 5 , the training loss function obtained by running the above method on 28224 sets of circuit layout samples with an initial learning rate of 0.01 and a learning rate update step of 30 is shown in the figure.

[0235] After the training, the above method was run on 496 target circuit layouts with the following parameters: initial temperature of 100, cooling rate of 0.01, exit temperature of 10, number of iterations at each temperature of 10, and routing rate difference threshold of 0.002. The actual routing rate was obtained by running the actual router on the layout after and before optimization. Figure 6 As shown, orange is the routing rate of the layout optimized by the simulated annealing algorithm, blue is the routing rate of the corresponding layout before optimization, the red dotted line is the average routing rate of the optimized layout, and green is the average routing rate of the layout before optimization.

[0236] In terms of optimization efficiency, the efficiency is greatly improved because the hypergraph convolutional neural network is used to directly predict the routing rate instead of calculating the routing rate based on the actual routing of the router: under the same simulated annealing parameters, the optimization time for optimizing 486 current layouts using the hypergraph convolutional neural network is 1287s, while the optimization time using the actual router in the prior art is 238577s, which greatly shortens the optimization time. In terms of optimization effect, the simulated annealing method using the hypergraph convolutional neural network as the evaluation indicator has significantly improved the routing rate of 341 layouts after optimization; in contrast, the actual router in the prior art is used as the evaluation indicator, and a total of 325 layouts are significantly improved after optimization.

[0237] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for circuit layout based on predicted routing rate, It is characterized in that include: Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout; Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout; Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module; Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample; Based on the predicted value of the disposition rate, training the disposition rate prediction model to be trained; Based on the trained routing rate prediction model, a routing rate prediction value of a target circuit layout is calculated to optimize the layout of the target circuit layout.

2. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that The method of generating characteristic matrix samples according to the position coordinates of each circuit module and the position coordinates of the ports of each circuit module includes: forming a row vector or a column vector of the characteristic matrix samples with the position coordinates of each circuit module and the position coordinates of its ports to generate the characteristic matrix samples.

3. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that The netlist information generates a correlation matrix sample, including: parsing the netlist, obtaining a wire net describing a connection relationship between circuit modules, and generating a correlation matrix sample.

4. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that The generating of the association matrix sample comprises: mapping each circuit module to a node in a hypergraph, and mapping a wire net to a hyperedge in the hypergraph, so as to generate the association matrix sample.

5. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that The step of mapping each circuit module to a node in a hypergraph and mapping a wire net to a hyperedge in the hypergraph to generate an association matrix sample includes: Assigning a first identifier to each node, so as to assign a second identifier to each hyperedge using the first identifiers corresponding to all nodes; Fill all first identifiers in ascending order to the first column of the created initial matrix, and fill all second identifiers in ascending order to the first row of the initial matrix; According to the relationship between the circuit modules and the wire nets, values ​​are assigned to the elements at the intersection of the first column and the first row in the initial matrix to generate the association matrix sample.

6. A method for circuit layout based on predicted routing rate according to claim 5, It is characterized in that The assigning values ​​to the elements at the intersection of the first column and the first row in the initial matrix according to the relationship between the circuit modules and the wire nets to generate the association matrix sample includes: If there is a subordinate relationship between the circuit module and the line network, the first eigenvalue is assigned to the element at the intersection of the first identifier corresponding to the circuit module in the first column and the second identifier corresponding to the line network in the first row in the initial matrix; If there is no affiliation between the circuit module and the line network, the element at the intersection of the first identifier corresponding to the circuit module in the first column and the second identifier corresponding to the line network in the first row in the initial matrix is ​​assigned a second eigenvalue, which is different from the first eigenvalue.

7. A method for circuit layout based on predicted routing rate according to claim 6, It is characterized in that The first eigenvalue and the second eigenvalue are selected from 0 and 1, so that the incidence matrix sample is a 01 matrix.

8. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that The step of inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample includes: Inputting the association matrix sample into the routing rate prediction model to be trained to calculate the node degree matrix, the hyperedge weight matrix and the hyperedge degree matrix; Performing feature fusion on the node degree matrix, the hyperedge weight matrix, the hyperedge degree matrix, the association matrix sample and the feature matrix sample to obtain sample layout features; Calculating a predicted value of the routing rate of the circuit layout sample according to the layout features of the sample layout; Determine whether the predicted value of the routing rate meets the preset standard. If so, the training ends. Otherwise, input the new association matrix sample and the feature matrix sample into the routing rate prediction model to be trained after the model parameters are updated to update the routing rate prediction value of the circuit layout sample, and again determine whether the updated routing rate prediction value meets the preset standard. If so, the training ends. Otherwise, input the updated association matrix sample and the feature matrix sample into the routing rate prediction model to be trained after the model parameters are updated again to update the routing rate prediction value of the circuit layout sample, and so on until the updated routing rate prediction value meets the preset standard.

9. A method for circuit layout based on predicted routing rate according to claim 1, It is characterized in that If the target circuit layout has N basic layouts, the method further includes: Generate N extended layouts based on each basic layout, where N is an integer greater than or equal to 1; Determine the association matrix and feature matrix under each basic layout and each extended layout; Based on the trained routing rate prediction model, a routing rate prediction value of a target circuit layout is calculated to optimize the layout of the target circuit layout, including: For each basic layout and each extended layout, the corresponding association matrix and feature matrix are input into the trained routing rate prediction model to calculate the routing rate of the target circuit layout under each basic layout and each extended layout; The layout of the target circuit layout is optimized according to the routing rates of the target circuit layout under all basic layouts and all extended layouts.

10. A training method for a data transmission rate prediction model. It is characterized in that include: Determine the netlist information of the circuit layout sample under the current layout, so as to generate a correlation matrix sample according to the netlist information, wherein the correlation matrix sample is used to describe the current layout; Determine the position coordinates of each circuit module and the position coordinates of the port of each circuit module of the circuit layout sample under the current layout; Generate a feature matrix sample according to the position coordinates of each circuit module and the position coordinates of the port of each circuit module; Inputting the association matrix sample and the feature matrix sample into a routing rate prediction model to be trained to obtain a routing rate prediction value of the circuit layout sample; Based on the predicted value of the disposition rate, the disposition rate prediction model to be trained is trained.

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