Method for determining violation position and related equipment

Abstract

The embodiment of the invention provides a violation position determination method and related equipment, and the method comprises the steps: obtaining a verification result of a whole chip comprising the position information of a violation in the whole chip, and the layout information of each sub-module in the whole chip; based on the position information of the violation in the whole chip and the layout information of each sub-module in the whole chip, determining the sub-module with the violation in the whole chip; obtaining violation information of the sub-modules including position information and direction information of the sub-modules in the whole chip; determining a conversion matrix based on the direction information; calculating the position information of the violation in the sub-module according to the position information and the conversion matrix of the sub-module in the whole chip and the position information of the violation in the whole chip; wherein the conversion matrix comprises information for indicating the mirror image relation of the sub-modules in the whole chip. According to the embodiment of the invention, the specific position of the violation in the sub-module can be determined, so that the violation can be quickly positioned, and the violation can be quickly repaired.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and specifically to a method for determining a violation position and related equipment. Background Art

[0002] In large-scale chip design, the entire chip to be designed is usually divided into multiple modules according to the execution logic, and then the module-level design is carried out, and the modules are merged and integrated. After that, the integrated chip is physically verified and the violations that occur during the physical verification process are repaired to obtain a chip design that can realize the preset functions.

[0003] However, the repair process of violations in the prior art is too complicated. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a method for determining a violation location and related equipment to achieve rapid location of the violation, thereby achieving rapid repair of the violation.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a method for determining a violation location, comprising:

[0007] Obtaining a verification result of the entire chip and layout information of each submodule in the entire chip; wherein the verification result includes location information of the violation in the entire chip;

[0008] Based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determining the sub-module in the full chip where the violation exists;

[0009] Acquire violation information of the submodule, wherein the violation information includes position information and direction information of the submodule in the whole chip;

[0010] Based on the direction information, determining a transformation matrix;

[0011] The position information of the violation in the submodule is calculated based on the position information and conversion matrix of the submodule in the whole chip, as well as the position information of the violation in the whole chip; wherein the conversion matrix contains information indicating the mirror relationship of the submodule in the whole chip.

[0012] Optionally, the conversion matrix is ​​(a 0 0b), wherein a and b are used to indicate the mirror relationship of the submodule in the full chip.

[0013] Optionally, the step of determining a conversion matrix based on the direction information is specifically:

[0014] If the orientation of the submodule in the full chip is the same as the initial orientation of the submodule, the conversion matrix (a 00b) is (1 0 0 1);

[0015] If the orientation of the submodule in the full chip is mirrored along the X-axis with the initial orientation of the submodule, the transformation matrix (a 0 0b) is (1 0 0 -1);

[0016] If the orientation of the submodule in the full chip is mirrored along the Y axis with the initial orientation of the submodule, the transformation matrix (a 0 0b) is (-1 0 0 1);

[0017] If the orientation of the submodule in the full chip is mirrored along the X-axis and the Y-axis with respect to the initial orientation of the submodule, the transformation matrix (a 0 0b) is (-1 0 0 -1).

[0018] Optionally, the step of calculating the position information of the violation in the submodule according to the position information of the submodule in the full chip and the conversion matrix, and the position information of the violation in the full chip, comprises:

[0019] The position information of the violation in the submodule is calculated according to the following formula:

[0020]

[0021] Among them, (x0, y0) is used to indicate the position information of the sub-module in the whole chip; a and b are used to indicate the mirror relationship of the sub-module in the whole chip; (x1, y1) is used to indicate the position information of the violation in the whole chip; (tx, ty) is used to indicate the position information of the violation in the sub-module.

[0022] Optionally, after the step of calculating the position information of the violation in the submodule according to the position information of the submodule in the full chip and the conversion matrix, and the position information of the violation in the full chip, the step further includes:

[0023] The position information of the violation in the submodule is fed back to the submodule.

[0024] Optionally, the step of obtaining the violation information of the submodule includes:

[0025] Determine the hierarchical structure of the entire chip;

[0026] Extract the violation information of the submodule according to the hierarchical structure.

[0027] In a second aspect, an embodiment of the present application provides a device for determining a violation location, including:

[0028] A first acquisition module is used to acquire the verification result of the whole chip and the layout information of each submodule in the whole chip; wherein the verification result includes the location information of the violation in the whole chip;

[0029] A first determination module, configured to determine a submodule in the full chip where a violation exists based on location information of the violation in the full chip and layout information of each submodule in the full chip;

[0030] A second acquisition module, used for acquiring violation information of the submodule, wherein the violation information includes position information and direction information of the submodule in the whole chip;

[0031] A second determination module, configured to determine a transformation matrix based on the direction information;

[0032] A calculation module is used to calculate the position information of the violation in the sub-module according to the position information and transformation matrix of the sub-module in the whole chip, and the position information of the violation in the whole chip; wherein the transformation matrix contains information indicating the mirror relationship of the sub-module in the whole chip.

[0033] Optionally, also include:

[0034] The feedback module is used to feed back the position information of the violation in the submodule to the submodule.

[0035] In a third aspect, an embodiment of the present application provides an electronic device comprising at least one memory and at least one processor, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the method for determining the violation location as described in the first aspect above.

[0036] In a fourth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the method for determining the violation location as described in the first aspect above is implemented.

[0037] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising one or more computer executable instructions, which, when executed, implement the method for determining the violation location as described in the first aspect above.

[0038] An embodiment of the present application provides a method for determining a violation position and related equipment, wherein the method for determining a violation position comprises: obtaining a verification result of a full chip and layout information of each sub-module in the full chip; wherein the verification result comprises location information of the violation in the full chip; based on the location information of the violation in the full chip and layout information of each sub-module in the full chip, determining a sub-module in the full chip where a violation exists; obtaining violation information of the sub-module, wherein the violation information comprises location information and direction information of the sub-module in the full chip; determining a conversion matrix based on the direction information; calculating the location information of the violation in the sub-module according to the location information of the sub-module in the full chip and the conversion matrix, as well as the location information of the violation in the full chip; wherein the conversion matrix comprises information indicating a mirror relationship of the sub-module in the full chip.

[0039] It can be seen that the method for determining the location of the violation provided in the embodiment of the present application is to obtain the verification result of the full chip including the location information of the violation in the full chip, and the layout information of each sub-module in the full chip; then, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists. Further obtain the violation information of the sub-module, the violation information includes the location information and direction information of the sub-module in the full chip, and determine the conversion matrix based on the direction information. Thus, according to the location information and conversion matrix of the sub-module in the full chip, and the location information of the violation in the full chip, the location information of the violation in the sub-module is calculated, and then the specific location of the violation in the sub-module is determined to achieve rapid location and repair of the violation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figure 1 is an optional flow chart of a method for determining a violation location provided in an embodiment of the present application;

[0042] Figure 2 It is a structural diagram of an offense;

[0043] Figure 3 It is a schematic diagram of the structure of a submodule with violations provided in an embodiment of the present application;

[0044] Figure 4is a diagram of the correspondence between the direction information of the submodules provided in the embodiment of the present application and the conversion matrix;

[0045] Figure 5 is an optional flow chart of step S300 provided in an embodiment of the present application;

[0046] Figure 6 It is a structural diagram of a full-chip hierarchical structure provided in an embodiment of the present application;

[0047] Figure 7 It is a structural diagram of extracting violation information of the submodule provided in an embodiment of the present application;

[0048] Figure 8 is an optional structural diagram of a device for determining a violation position provided in an embodiment of the present application;

[0049] Fig. 9 It is an optional block diagram of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0051] As described in the background art, in large-scale chip design, the entire chip to be designed is usually divided into multiple modules according to logic, and then module-level design is performed, and the modules are merged and integrated. After that, the integrated chip is physically verified, and the violations that occur during the physical verification of the full chip are repaired to obtain a chip design that can achieve the preset function. However, the process of repairing violations in the prior art is too complicated.

[0052] The inventors analyzed that violations that occur during the full-chip physical verification process are usually reported at the full-chip level, but the actual repair work needs to be performed inside each module in the full chip. Since violations are usually reported at the full-chip level, it is impossible to determine the specific location of the violation in each module. Repairing violations usually requires manual inspection and determining the specific location information of the violation, making the repair process of the violation too complicated.

[0053] In order to solve the above problems, an embodiment of the present application provides a method for determining a violation position and related equipment, wherein the method for determining a violation position includes: obtaining a verification result of the whole chip and layout information of each sub-module in the whole chip; wherein the verification result includes the position information of the violation in the whole chip; based on the position information of the violation in the whole chip and the layout information of each sub-module in the whole chip, determining the sub-module in the whole chip where the violation exists; obtaining the violation information of the sub-module, wherein the violation information includes the position information and direction information of the sub-module in the whole chip; determining a transformation matrix based on the direction information; calculating the position information of the violation in the sub-module according to the position information of the sub-module in the whole chip and the transformation matrix, as well as the position information of the violation in the whole chip; wherein the transformation matrix includes information indicating the mirror relationship of the sub-module in the whole chip.

[0054] It can be seen that the method for determining the location of the violation provided in the embodiment of the present application is to obtain the verification result of the full chip including the location information of the violation in the full chip, and the layout information of each sub-module in the full chip; then, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists. Further obtain the violation information of the sub-module, the violation information includes the location information and direction information of the sub-module in the full chip, and determine the conversion matrix based on the direction information. Thus, according to the location information and conversion matrix of the sub-module in the full chip, and the location information of the violation in the full chip, the location information of the violation in the sub-module is calculated, and then the specific location of the violation in the sub-module is determined to achieve rapid location and repair of the violation.

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0056] refer to Figure 1 , Figure 1 FIG. 1 is an optional flow chart of a method for determining a violation location provided in an embodiment of the present application. Figure 1 As shown, the method for determining the violation position may include the following steps:

[0057] Step S100, obtaining the verification result of the whole chip and the layout information of each sub-module in the whole chip.

[0058] The verification result includes location information of the violation in the full chip, and the location information of the violation in the full chip indicates the exact location of the violation in the full chip design space.

[0059] The embodiment of the present application obtains the verification result of the whole chip by executing step S100, and the verification result includes the location information of the violation in the whole chip, so as to determine the sub-module in the whole chip where the violation exists based on the location information of the violation in the whole chip, thereby providing a basis for the subsequent calculation of the location information of the violation in the sub-module.

[0060] "Full chip" refers to the sum of all components and functions involved in the design, simulation, verification and manufacturing process of the entire chip in chip design. The full chip may include multiple levels of sub-modules.

[0061] In chip design, a violation usually refers to a situation where certain constraints or rules are not met during the design process, such as violating the minimum spacing, maximum overlap or other design rules during the placement and routing process. For example, in placement and routing, different components (such as transistors, capacitors, resistors, etc.) need to maintain a certain spacing between them to prevent electrical short circuits or interference. If the distance between two components is less than the specified minimum spacing, a minimum spacing violation will occur.

[0062] Specifically, refer to Figure 2 , Figure 2 is a structural diagram of an exception. Figure 2 As shown in the figure, there is a wire between module A and module B in the full chip. When module A and module B are verified separately, the net (connection) length may meet the requirements. However, during the full chip verification, due to the existence of other modules, the net length from module A to module B will increase significantly, resulting in signal delay, increased power consumption, breakdown effect and other problems, which will lead to violations. In the early stages of chip design, such violations are often unavoidable and there are huge numbers of them.

[0063] During the design phase, the full chip is usually divided into multiple sub-modules, each of which is responsible for implementing a specific function. These sub-modules have a clear layout on the full chip (i.e., the layout information of the sub-modules). The layout information of each sub-module in the full chip may include but is not limited to the location, size, and shape of the sub-module.

[0064] Continue to refer Figure 1 , execute step S200, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists.

[0065] In an optional implementation, the submodules in the full chip where the violation exists can be determined by comparing the location information of the violation in the full chip with the layout information of each submodule in the full chip. For example, the coordinates of the violation in the full chip are compared with the boundary coordinates of each submodule to determine whether the violation is inside or on the boundary of a submodule. If the coordinates of the violation are within the boundary of a submodule, the submodule is considered to be a submodule with a violation. If the violation happens to be on the boundary of the submodule, it is necessary to decide whether to regard the submodule as a submodule with a violation based on the specific circumstances (such as the division rules of the submodules, the scope of influence of the violation, etc.).

[0066] Specifically, refer to Figure 3 , Figure 3 Schematic diagram of the structure of the submodule with violation provided in the embodiment of the present application. Figure 3 As shown, during the design phase, the full chip is usually divided into multiple sub-modules, each of which is responsible for implementing a specific function. These sub-modules have a clear layout on the full chip, including the sub-module position, size, and shape. After obtaining the location information of the violation in the full chip and the layout information of each sub-module in the full chip, the coordinates of the violation in the full chip can be compared with the boundary coordinates of each sub-module to determine whether the violation is inside or on the boundary of a sub-module. For example Figure 3 In the example, the violation is inside the submodule in the upper right corner of the chip, which means that there is a violation in this submodule.

[0067] It should be noted that the above comparison of the coordinates of the violation in the whole chip with the boundary coordinates of each sub-module to determine the sub-module with the violation in the whole chip is only an example. In other embodiments, the sub-module with the violation in the whole chip can also be determined by other methods.

[0068] This example does not limit this.

[0069] Continue to refer Figure 1 , execute step S300 to obtain violation information of the submodule, where the violation information includes position information and direction information of the submodule in the whole chip.

[0070] In an optional implementation, the position information of the submodule in the full chip can be represented by a Cartesian coordinate system, in which each submodule can be accurately located by a two-dimensional coordinate (x, y). For example, the position information of a submodule in the full chip is (x0, y0). Among them, x0 is used to indicate the horizontal position of the submodule in the full chip (i.e., x0 is the horizontal coordinate of the submodule), and y0 is used to indicate the vertical position of the submodule in the full chip (i.e., y0 is the vertical coordinate of the submodule).

[0071] The Cartesian coordinate system provides an intuitive and accurate way to describe the location information of the submodule in the full chip. By using the Cartesian coordinate system, designers can easily determine the location information of the submodule.

[0072] It should be noted that the above-mentioned use of the Cartesian coordinate system to represent the position information of the sub-module in the whole chip is only an example. In other embodiments, the position information of the sub-module in the whole chip can also be represented by other methods, and the embodiments of the present application are not limited to this.

[0073] In an alternative example, reference Figure 4 , Figure 4 is a diagram showing the correspondence between the direction information of the submodules provided in the embodiment of the present application and the conversion matrix, such as Figure 4 As shown, the direction information of the submodule in the full chip may include: the direction of the submodule in the full chip is the same as the initial direction of the submodule (such as Figure 4 The direction of the submodule in the full chip is mirrored along the X-axis with the initial direction of the submodule (as shown in the graphic annotation corresponding to R0 in FIG. 1 ). Figure 4 The direction of the submodule in the full chip is mirrored along the Y axis with the initial direction of the submodule (as shown in the graphic annotation corresponding to MX in FIG. Figure 4 The direction of the submodule in the full chip is mirrored along the X-axis and Y-axis with the initial direction of the submodule (as shown in the graphic annotation corresponding to MY in FIG. 1 ); Figure 4 (as shown in the graphic annotation corresponding to R180 in FIG.

[0074] It should be noted that Figure 4 In the figure, the origin of the submodule is at the lower left corner as the initial direction of the submodule. In other embodiments, the initial direction of the submodule can be set according to actual conditions, and the embodiments of the present application are not limited to this.

[0075] also, Figure 4 The direction information of the submodule (R0, MX, MY and R180) is only an exemplary description of the corresponding graphics in the graphic annotation. For example, the corresponding relationship between MX and R0 can be understood as, after mirroring the graphic corresponding to R0 (the origin of the submodule is in the lower left corner) along the X-axis, the resulting graphic is the graphic corresponding to MX (the origin of the submodule is in the upper left corner); the corresponding relationship between MY and R0 can be understood as, after mirroring the graphic corresponding to R0 (the origin of the submodule is in the lower left corner) along the Y-axis, the resulting graphic is the graphic corresponding to MY (the origin of the submodule is in the lower right corner); the corresponding relationship between R180 and R0 can be understood as, after mirroring the graphic corresponding to R0 (the origin of the submodule is in the lower left corner) along the X-axis and the Y-axis, the resulting graphic is the graphic corresponding to R180 (the origin of the submodule is in the upper right corner).

[0076] In the specific implementation, refer to Figure 5 , Figure 5 is an optional flow chart of step S300 provided in the embodiment of the present application. Figure 5 As shown, the step of obtaining the violation information of the submodule may include:

[0077] Step S301, determining the hierarchical structure of the entire chip.

[0078] In large-scale chip design, the entire chip to be designed is usually divided into multiple modules according to logic, and then the module-level design is carried out, and the modules are merged and integrated. Specifically, the designer first synthesizes the functional requirements and specifications of each module, and then designs the circuit according to the characteristics and layout and wiring specifications of each module. Among them, the connection of the input and output interfaces of each module is called "top-level merging", and each module is completed independently from synthesis to automatic layout and wiring.

[0079] The combined integrated full chip may include multiple levels of sub-modules. Figure 6 , Figure 6 Schematic diagram of a full-chip hierarchical structure provided by an embodiment of the present application. Figure 5 As shown, the hierarchical structure of the full chip may include: a first-level module (for example, Figure 6 The secondary modules (e.g., Figure 6 The middle secondary module 21, the secondary module 22, the secondary module 23, the secondary module 24 and the secondary module 25) ... the final module (e.g., Figure 6 The final module n1, the final module n2, the final module n3 and the final module n4 are used to determine the hierarchical structure of the whole chip, so as to extract the violation information of the submodule according to the hierarchical structure.

[0080] Continue to refer Figure 5 , execute step S302, extracting the violation information of the sub-module according to the hierarchical structure.

[0081] In an optional implementation, the extracted violation information of the submodules may be rearranged to form a violation list clustered in a hierarchical structure. Figure 7 , Figure 7 Schematic diagram of the structure of extracting violation information of the submodule provided in the embodiment of the present application. Figure 7 As shown, the extracted violation information of the submodule is rearranged (such as Figure 7Violation a, Violation b, Violation c, Violation d, Violation e, Violation f, Violation g and Violation h) in .

[0082] It should be noted that, in the embodiment of the present application, the sub-modules with violations in the full chip can be processed in the manner described above, while the sub-modules without violations in the full chip do not need to be processed (for example Figure 7 The first-level module 12 and the second-level module 23).

[0083] Continue to refer Figure 1 , execute step S400 to determine a transformation matrix based on the direction information.

[0084] The conversion matrix includes information indicating the mirror relationship of the submodules in the full chip.

[0085] In an optional implementation, the conversion matrix may be (a 0 0b), wherein a and b are used to indicate the mirror relationship of the submodule in the full chip. In a specific implementation, the step of determining the conversion matrix based on the direction information is specifically as follows: if the direction of the submodule in the full chip is the same as the initial direction of the submodule, the conversion matrix (a 00b) is (1 0 0 1); if the direction of the submodule in the full chip is mirrored along the X axis with the initial direction of the submodule, the conversion matrix (a 0 0b) is (1 0 0 -1); if the direction of the submodule in the full chip is mirrored along the Y axis with the initial direction of the submodule, the conversion matrix (a 0 0b) is (-1 0 0 1); if the direction of the submodule in the full chip is mirrored along the X axis and the Y axis with the initial direction of the submodule, the conversion matrix (a 0 0b) is (-10 0 -1).

[0086] Specifically, refer to Figure 4 , if the direction of the submodule in the full chip is the same as the initial direction of the submodule (i.e., not mirrored), the conversion matrix (a 0 0b) is (1 0 0 1); if the direction of the submodule in the full chip is mirrored along the X axis with the initial direction of the submodule, the conversion matrix (a 00b) is (1 0 0 -1); if the direction of the submodule in the full chip is mirrored along the Y axis with the initial direction of the submodule, the conversion matrix (a 0 0b) is (-1 0 0 1); if the direction of the submodule in the full chip is mirrored along the X and Y axes with the initial direction of the submodule, the conversion matrix (a 0 0b) is (-1 0 0 -1).

[0087] Continue to refer Figure 1 , execute step S500, calculate the position information of the violation in the sub-module according to the position information of the sub-module in the whole chip and the conversion matrix, and the position information of the violation in the whole chip.

[0088] According to the position information and conversion matrix of the submodule in the whole chip, as well as the position information of the violation in the whole chip, the position information of the violation in the submodule is calculated, thereby determining the specific position of the violation in the submodule to achieve rapid positioning and repair of the violation.

[0089] In a specific implementation, the step of calculating the position information of the violation in the submodule according to the position information of the submodule in the full chip and the conversion matrix, and the position information of the violation in the full chip, may include:

[0090] The position information of the violation in the submodule is calculated according to the following formula:

[0091]

[0092] Among them, (x0, y0) is used to indicate the location information of the submodule in the full chip; a and b are used to indicate the mirror relationship of the submodule in the full chip; (x1, y1) is used to indicate the location information of the violation in the full chip; (tx, ty) is used to indicate the location information of the violation in the submodule. tx = (x1-x0) / a; ty = (y1-y0) / b.

[0093] It can be understood that, from the calculation results, 1 in the matrix does not participate in the calculation, so 1 in the matrix can be any value, and this application does not limit this.

[0094] In an optional implementation, after the step of calculating the position information of the violation in the sub-module based on the position information and transformation matrix of the sub-module in the whole chip and the position information of the violation in the whole chip, the step may also include: feeding back the position information of the violation in the sub-module to the sub-module to achieve rapid repair of the violation.

[0095] It can be seen that the method for determining the location of the violation provided in the embodiment of the present application is to obtain the verification result of the full chip including the location information of the violation in the full chip, and the layout information of each sub-module in the full chip; then, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists. Further obtain the violation information of the sub-module, the violation information includes the location information and direction information of the sub-module in the full chip, and determine the conversion matrix based on the direction information. Thus, according to the location information and conversion matrix of the sub-module in the full chip, and the location information of the violation in the full chip, the location information of the violation in the sub-module is calculated, and then the specific location of the violation in the sub-module is determined to achieve rapid location and repair of the violation.

[0096] In an optional implementation, the embodiment of the present application can also reversely infer the location information of the violation in the whole chip based on the location information of the violation in the submodule. For example, substitute x0, y0, a, b, tx and ty into the following matrix:

[0097]

[0098] Obtain x1=a*tx+x0; y1=b*ty+y0, and feed (x1, y1) back to the full chip level, so that the verification personnel can detect whether there is a violation at the position (x1, y1) in the full chip, and thus determine the risk factor of the violation in the submodule. Among them, (x0, y0) is used to indicate the position information of the submodule in the full chip; a and b are used to indicate the mirror relationship of the submodule in the full chip; (x1, y1) is used to indicate the position information of the violation in the full chip; (tx, ty) is used to indicate the position information of the violation in the submodule.

[0099] It can be understood that, from the calculation results, 1 in the matrix does not participate in the calculation, so 1 in the matrix can be any value, and this application does not limit this.

[0100] Because in the design process, some constraints are stricter at the module level and are relaxed accordingly at the full chip level. Therefore, violations verified within the sub-module may not appear during full chip verification. Therefore, if during the chip design process, the violations within the sub-module are back-annotated to the top level, if the violation is not shown in the full chip verification results, the risk can be released as soon as possible to avoid unnecessary worries and corrections.

[0101] It can be seen that the method for determining the location of the violation provided in the embodiment of the present application is to obtain the verification result of the full chip including the location information of the violation in the full chip, and the layout information of each sub-module in the full chip; then, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists. Further obtain the violation information of the sub-module, the violation information includes the location information and direction information of the sub-module in the full chip, and determine the conversion matrix based on the direction information. Thus, according to the location information and conversion matrix of the sub-module in the full chip, and the location information of the violation in the full chip, the location information of the violation in the sub-module is calculated, and then the specific location of the violation in the sub-module is determined to achieve rapid location and repair of the violation.

[0102] The following is an introduction to the device for determining the violation position provided in the embodiment of the present application. The device for determining the violation position described below can be considered as a software function module or a hardware function module required to implement the method for determining the violation position provided in the embodiment of the present application. The content of the device for determining the violation position described below can be referred to in correspondence with the content of the method described above.

[0103] In an optional implementation, Figure 8 The optional structural diagram of the device for determining the violation position provided in the embodiment of the present application is exemplarily shown, and the device for determining the violation position is used to implement the method for determining the violation position provided in the embodiment of the present application, such as Figure 8 As shown, the device for determining the violation position may include:

[0104] A first acquisition module 71 is used to acquire the verification result of the whole chip and the layout information of each submodule in the whole chip; wherein the verification result includes the location information of the violation in the whole chip;

[0105] A first determination module 72, configured to determine a submodule in the full chip where a violation exists based on location information of the violation in the full chip and layout information of each submodule in the full chip;

[0106] A second acquisition module 73, used for acquiring violation information of the submodule, wherein the violation information includes position information and direction information of the submodule in the whole chip;

[0107] A second determination module 74, configured to determine a conversion matrix based on the direction information;

[0108] The calculation module 75 is used to calculate the position information of the violation in the submodule according to the position information and transformation matrix of the submodule in the whole chip, and the position information of the violation in the whole chip; wherein the transformation matrix contains information indicating the mirror relationship of the submodule in the whole chip.

[0109] Optionally, the conversion matrix is ​​(a 0 0b), wherein a and b are used to indicate the mirror relationship of the submodule in the full chip.

[0110] Optionally, the first determining module 72 is used to determine a conversion matrix based on the direction information, specifically:

[0111] If the orientation of the submodule in the full chip is the same as the initial orientation of the submodule, the conversion matrix (a 00b) is (1 0 0 1);

[0112] If the orientation of the submodule in the full chip is mirrored along the X-axis with the initial orientation of the submodule, the transformation matrix (a 0 0b) is (1 0 0 -1);

[0113] If the orientation of the submodule in the full chip is mirrored along the Y axis with the initial orientation of the submodule, the transformation matrix (a 0 0b) is (-1 0 0 1);

[0114] If the orientation of the submodule in the full chip is mirrored along the X-axis and the Y-axis with respect to the initial orientation of the submodule, the transformation matrix (a 0 0b) is (-1 0 0 -1).

[0115] Optionally, the calculation module 75 is used to calculate the position information of the violation in the submodule according to the position information of the submodule in the whole chip and the conversion matrix, and the position information of the violation in the whole chip, including:

[0116] The position information of the violation in the submodule is calculated according to the following formula:

[0117]

[0118] Among them, (x0, y0) is used to indicate the position information of the sub-module in the whole chip; a and b are used to indicate the mirror relationship of the sub-module in the whole chip; (x1, y1) is used to indicate the position information of the violation in the whole chip; (tx, ty) is used to indicate the position information of the violation in the sub-module.

[0119] Optionally, the second acquisition module 73 is used to acquire the violation information of the submodule, including:

[0120] Determine the hierarchical structure of the entire chip;

[0121] Extract the violation information of the submodule according to the hierarchical structure.

[0122] Optionally, also include:

[0123] The feedback module 76 is used to feed back the location information of the violation in the submodule to the submodule.

[0124] It can be seen that the method for determining the location of the violation provided in the embodiment of the present application is to obtain the verification result of the full chip including the location information of the violation in the full chip, and the layout information of each sub-module in the full chip; then, based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determine the sub-module in the full chip where the violation exists. Further obtain the violation information of the sub-module, the violation information includes the location information and direction information of the sub-module in the full chip, and determine the conversion matrix based on the direction information. Thus, according to the location information and conversion matrix of the sub-module in the full chip, and the location information of the violation in the full chip, the location information of the violation in the sub-module is calculated, and then the specific location of the violation in the sub-module is determined to achieve rapid location and repair of the violation.

[0125] An embodiment of the present application also provides an electronic device, which may include at least one memory and at least one processor, wherein the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the method for determining the violation location provided in the embodiment of the present application.

[0126] As an optional implementation, refer to Fig. 9 , Fig. 9 is an optional block diagram of an electronic device provided in an embodiment of the present application. Fig. 9 As shown, the electronic device may include: at least one processor 10 , at least one communication interface 20 , at least one memory 30 and at least one communication bus 40 .

[0127] In the embodiment of the present application, the number of the processor 10 , the communication interface 20 , the memory 30 and the communication bus 40 is at least one, and the processor 10 , the communication interface 20 , and the memory 30 communicate with each other through the communication bus 40 .

[0128] Optionally, the processor 10 may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Neural-network Processing Unit), an FPGA (Field Programmable Gate Array), a TPU (Tensor Processing Unit), an AI chip, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement an embodiment of the present application.

[0129] Optionally, the communication interface 20 may be an interface of a communication module for performing network communication.

[0130] The memory 30 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory. The memory 30 stores one or more computer executable instructions, and the processor 10 calls the one or more computer executable instructions to execute the method for determining the violation location provided in the embodiment of the present application.

[0131] An embodiment of the present application further provides a storage medium, wherein the storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the method for determining the violation location provided in the embodiment of the present application is implemented.

[0132] An embodiment of the present application also provides a computer program product, which may include one or more computer executable instructions. When the one or more computer executable instructions are executed, the method for determining the violation location provided in the embodiment of the present application is implemented.

[0133] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0134] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for determining a violation position, characterized in that: include: Obtaining a verification result of the entire chip and layout information of each submodule in the entire chip; wherein the verification result includes location information of the violation in the entire chip; Based on the location information of the violation in the full chip and the layout information of each sub-module in the full chip, determining the sub-module in the full chip where the violation exists; Acquire violation information of the submodule, wherein the violation information includes position information and direction information of the submodule in the whole chip; Based on the direction information, determining a transformation matrix; The position information of the violation in the submodule is calculated based on the position information and conversion matrix of the submodule in the whole chip, as well as the position information of the violation in the whole chip; wherein the conversion matrix contains information indicating the mirror relationship of the submodule in the whole chip.

2. The method for determining a violation position according to claim 1, characterized in that: The conversion matrix is ​​(a 00b), where a and b are used to indicate the mirror relationship of the submodule in the full chip.

3. The method for determining a violation position according to claim 2, characterized in that: The step of determining the conversion matrix based on the direction information is specifically: If the orientation of the submodule in the full chip is the same as the initial orientation of the submodule, the conversion matrix (a 0 0b) is (1 0 0 1); If the orientation of the submodule in the full chip is mirrored along the X-axis with the initial orientation of the submodule, the transformation matrix (a0 0b) is (1 0 0-1); If the orientation of the submodule in the full chip is mirrored along the Y axis with the initial orientation of the submodule, the transformation matrix (a0 0b) is (-1 0 0 1); If the orientation of the submodule in the full chip is mirrored along the X-axis and the Y-axis with the initial orientation of the submodule, the transformation matrix (a 0 0b) is (-1 0 0-1).

4. The method for determining a violation position according to claim 3, characterized in that: The step of calculating the position information of the violation in the submodule according to the position information of the submodule in the whole chip and the conversion matrix, and the position information of the violation in the whole chip, comprises: The position information of the violation in the submodule is calculated according to the following formula: Among them, (x0, y0) is used to indicate the position information of the sub-module in the whole chip; a and b are used to indicate the mirror relationship of the sub-module in the whole chip; (x1, y1) is used to indicate the position information of the violation in the whole chip; (tx, ty) is used to indicate the position information of the violation in the sub-module.

5. The method for determining a violation position according to claim 1, characterized in that: After the step of calculating the position information of the violation in the submodule according to the position information of the submodule in the full chip and the conversion matrix, and the position information of the violation in the full chip, the method further includes: The position information of the violation in the submodule is fed back to the submodule.

6. The method for determining a violation position according to claim 1, characterized in that: The step of obtaining violation information of the submodule comprises: Determine the hierarchical structure of the entire chip; Extract the violation information of the submodule according to the hierarchical structure.

7. A device for determining a violation position, characterized in that: include: A first acquisition module is used to acquire the verification result of the whole chip and the layout information of each submodule in the whole chip; wherein the verification result includes the location information of the violation in the whole chip; A first determination module, configured to determine a submodule in the full chip where a violation exists based on location information of the violation in the full chip and layout information of each submodule in the full chip; A second acquisition module, used for acquiring violation information of the submodule, wherein the violation information includes position information and direction information of the submodule in the whole chip; A second determination module, configured to determine a transformation matrix based on the direction information; A calculation module is used to calculate the position information of the violation in the submodule according to the position information and transformation matrix of the submodule in the whole chip, and the position information of the violation in the whole chip; wherein the transformation matrix contains information indicating the mirror relationship of the submodule in the whole chip.

8. The device for determining a violation position according to claim 7, characterized in that: Also includes: The feedback module is used to feed back the position information of the violation in the submodule to the submodule.

9. An electronic device, characterized in that: The system comprises at least one memory and at least one processor, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the method for determining a violation position according to any one of claims 1 to 6.

10. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the method for determining the violation position according to any one of claims 1 to 6 is implemented.

11. A computer program product, characterized in that The method comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the method for determining the violation position according to any one of claims 1 to 6 is implemented.

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