Ferroelectric memory and data reading method and data writing method thereof

Abstract

The invention provides a ferroelectric memory and a data reading method and a data writing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of low storage density. The ferroelectric memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells arranged in an array, each memory cell stores n bits of data, each memory cell comprises a transistor and 2n-1 ferroelectric capacitors coupled with the transistor, and n is a positive integer greater than 1; a plurality of word lines, each word line being coupled to the memory cells arranged in rows in the memory cell array; and a plurality of bit lines, each bit line being coupled to the memory cells arranged in columns in the memory cell array. 2n storage states can be determined by using the polarization directions of the 2n-1 ferroelectric capacitors, and each storage state corresponds to one type of data, so that the 2n-1 ferroelectric capacitors store n-bit data, multi-state storage of the ferroelectric memory is realized, and the storage density of the ferroelectric memory is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a ferroelectric memory and a data reading method and a data writing method thereof. Background Art

[0002] With the rapid development of electronic technology, non-volatile transistor memory can be prepared by solution method and is compatible with integrated circuits, and has achieved great development. Non-volatile transistor memory includes NAND flash memory, NOR flash memory, resistance random access memory, phase change memory, magnetoresistive random access memory, ferroelectric memory, spin transfer torque random access memory, etc. Among them, ferroelectric memory has the most commercial value because of its advantages of high integration density, good repeatability and fast response speed. However, the storage density of ferroelectric memory is low. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a ferroelectric memory and a data reading method and a data writing method thereof, so as to improve the storage density of the ferroelectric memory.

[0004] According to some embodiments, a first aspect of the present disclosure provides a ferroelectric memory, comprising:

[0005] A memory cell array, wherein the memory cell array comprises a plurality of memory cells arranged in an array, each of the memory cells storing n-bit data, wherein each of the memory cells comprises: a transistor and 2 coupled to the transistor n - 1 ferroelectric capacitor, wherein n is a positive integer greater than 1;

[0006] A plurality of word lines, each of the word lines being coupled to the memory cells arranged in a row in the memory cell array;

[0007] A plurality of bit lines are provided, each of the bit lines being coupled to the memory cells arranged in columns in the memory cell array.

[0008] In some possible embodiments, each of the ferroelectric capacitors includes a first electrode plate and a second electrode plate that are arranged opposite to each other, and a dielectric layer filled between the first electrode plate and the second electrode plate;

[0009] 2 n - 1 said ferroelectric capacitors are arranged in sequence along a first direction, 2 n - 1 the first electrode plates are connected into an integrated structure, 2 n -1 the second electrode plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, and the dielectric layers have different thicknesses.

[0010] In some possible embodiments, along the first direction, 2n -1 The thickness of the dielectric layer of the ferroelectric capacitor increases sequentially.

[0011] In some possible embodiments, along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors are arranged in an arithmetic progression.

[0012] In some possible embodiments, 2 n -1 the second plate has the same potential, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

[0013] In some possible embodiments, each of the ferroelectric capacitors includes a first electrode plate and a second electrode plate that are arranged opposite to each other, and a dielectric layer filled between the first electrode plate and the second electrode plate;

[0014] 2 n - 1 said ferroelectric capacitors are arranged in sequence along a first direction, 2 n - 1 the first electrode plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, 2 n -1 of the second electrode plates are arranged at intervals.

[0015] In some possible embodiments, 2 n -1 The thickness of the dielectric layer is equal to that of 2 n -1 The coercive voltages of the ferroelectric capacitors are the same.

[0016] In some possible embodiments, 2 n -1 The length of the second electrode plate is the same.

[0017] In some possible embodiments, 2 n -1 The second plate potentials are different, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line

[0018] The ferroelectric memory provided by the embodiments of the present disclosure has at least the following advantages:

[0019] The ferroelectric memory provided by the embodiment of the present disclosure includes a memory cell array, a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells arranged in an array, each word line is coupled to a memory cell arranged in a row in the memory cell array, and each bit line is coupled to a memory cell arranged in a column in the memory cell array. Each memory cell includes a transistor and a 2 n -1 ferroelectric capacitor, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor can be determined by 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor stores n bits of data, thereby realizing polymorphic storage of the ferroelectric memory and improving the storage density of the ferroelectric memory.

[0020] According to some embodiments, a second aspect of the present disclosure provides a data reading method of a ferroelectric memory, which is applied to the ferroelectric memory as described above, and the data reading method includes:

[0021] Using bit lines and transistors, the corresponding 2 n - the first plates of the ferroelectric capacitors are all charged to a first voltage, wherein the first voltage causes the polarization direction of each of the ferroelectric capacitors to point to the first plate, and when the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows positive charge to the bit line;

[0022] The data in the storage unit is acquired according to the change of the charge amount of the bit line, wherein the storage unit stores n bits of the data.

[0023] The data reading method of the ferroelectric memory provided by the embodiment of the present disclosure has at least the following advantages:

[0024] The data reading method of the ferroelectric memory provided by the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage, each storage unit of the ferroelectric memory includes a transistor and a coupling transistor 2 n -1 ferroelectric capacitor, n is a positive integer greater than 1. n -1 The first plates of the ferroelectric capacitors are all charged to a first voltage. The first voltage makes the polarization direction of each ferroelectric capacitor point to the first plate. The polarization direction of the ferroelectric capacitor is flipped to flow positive charge to the bit line. The data in the storage unit can be obtained according to the change of the charge on the bit line, thereby realizing the reading of n-bit data and improving the storage density of the ferroelectric memory.

[0025] According to some embodiments, a third aspect of the present disclosure provides a method for writing data into a ferroelectric memory, which is applied to the ferroelectric memory as described above, and the method for reading data includes:

[0026] Using bit lines and transistors, the corresponding 2 n - charging a first plate of a ferroelectric capacitor to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor to point to the first plate, so as to initialize each ferroelectric capacitor;

[0027] A write voltage is applied to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to a type of data, some of the voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors to flip their polarization directions.

[0028] The data writing method of the ferroelectric memory provided by the embodiment of the present disclosure has at least the following advantages:

[0029] The data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage, each storage unit of the ferroelectric memory includes a transistor and a coupling transistor 2 n -1 ferroelectric capacitor, n is a positive integer greater than 1. n The first plates of the ferroelectric capacitors are all charged to a first voltage, and the first voltage makes the polarization direction of each ferroelectric capacitor point to the first plate, so that each ferroelectric capacitor is initialized. Then, different voltage values ​​of the write voltage are used, so that each voltage value corresponds to a kind of data, and some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors whose polarization directions are flipped, so as to realize the writing of n-bit data and improve the storage density of the ferroelectric memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the storage 1 of the ferroelectric capacitor in the related art;

[0031] Figure 2 It is a schematic diagram of the storage 0 of a ferroelectric capacitor in the related art;

[0032] Figure 3 is a schematic structural diagram of a ferroelectric memory in an embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of a polarization state in an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of the structure of a ferroelectric capacitor in an embodiment of the present disclosure;

[0035] Figure 6 for Figure 5The first storage state of the ferroelectric capacitor in;

[0036] Figure 7 for Figure 5 The second storage state of the ferroelectric capacitor in;

[0037] Figure 8 for Figure 5 The third storage state of the ferroelectric capacitor in;

[0038] Fig. 9 for Figure 5 The fourth storage state of the ferroelectric capacitor in;

[0039] Fig.10 is another structural schematic diagram of a ferroelectric capacitor in an embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of the connection between a transistor and a ferroelectric capacitor in an embodiment of the present disclosure;

[0041] Fig.12 for Fig.10 The first storage state of the ferroelectric capacitor in;

[0042] Fig.13 for Fig.10 The second storage state of the ferroelectric capacitor in;

[0043] Fig.14 for Fig.10 The third storage state of the ferroelectric capacitor in;

[0044] Fig.15 for Fig.10 The fourth storage state of the ferroelectric capacitor in;

[0045] Fig.16 is a flow chart of a method for reading data of a ferroelectric capacitor in an embodiment of the present disclosure;

[0046] Fig.17 for Figure 5 Schematic diagram of bit line precharging when reading ferroelectric capacitor data;

[0047] Fig.18 for Figure 5 A polarization direction change diagram of the first storage state of the ferroelectric capacitor;

[0048] Fig.19 for Figure 5 A diagram showing a change in polarization direction of a second storage state of a ferroelectric capacitor;

[0049] Fig. 20 for Figure 5 A diagram showing a change in polarization direction of a third storage state of a ferroelectric capacitor;

[0050] Fig.21 for Figure 5 A diagram showing a change in polarization direction of a fourth storage state of a ferroelectric capacitor;

[0051] Fig. 22 for Fig.10 Schematic diagram of bit line precharging when reading ferroelectric capacitor data;

[0052] Fig.23 for Fig.10 A polarization direction change diagram of the first storage state of the ferroelectric capacitor;

[0053] Fig.24 for Fig.10 A diagram showing a change in polarization direction of a second storage state of a ferroelectric capacitor;

[0054] Fig.25 for Fig.10 A diagram showing a change in polarization direction of a third storage state of a ferroelectric capacitor;

[0055] Fig.26 for Fig.10 A diagram showing a change in polarization direction of a third storage state of a ferroelectric capacitor;

[0056] Fig. 27 is a flow chart of a method for writing data into a ferroelectric capacitor in an embodiment of the present disclosure;

[0057] Fig.28 for Figure 5 Schematic diagram of bit line precharging when ferroelectric capacitor data is written;

[0058] Fig.29 for Figure 5 A diagram showing a change in polarization direction of a ferroelectric capacitor when a write voltage is a first preset value;

[0059] Fig.30 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a second preset value;

[0060] Fig.31 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a third preset value;

[0061] Fig.32 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a fourth preset value;

[0062] Fig.33 for Fig.10 Schematic diagram of bit line precharging when ferroelectric capacitor data is written;

[0063] Fig.34 for Fig.10 A diagram showing a change in polarization direction of a ferroelectric capacitor when a write voltage is a first preset value;

[0064] Fig.35 for Fig.10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a second preset value;

[0065] Fig.36 for Fig.10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a third preset value;

[0066] Fig.37 for Fig.10 A diagram showing the change in polarization direction of the ferroelectric capacitor when the write voltage is a fourth preset value.

[0067] Description of reference numerals:

[0068] 11-transistor; 12-ferroelectric capacitor;

[0069] 20-bit line; 30-word line;

[0070] 40-substrate; 50-gate dielectric layer;

[0071] 60-plug; 70-wire. DETAILED DESCRIPTION

[0072] The ferroelectric memory in the related art has a problem of storage density. The inventors have found that the reason is that the ferroelectric memory includes a plurality of storage cells, each of which is usually a 1T1C (Ferroelectric Cell) structure, which includes a transistor and a ferroelectric capacitor. Figure 1 and Figure 2 The polarization direction of ferroelectric capacitors is two, that is, there are two stable states. These two stable states are stored in the form of "0" or "1". Each storage unit can only store one bit of data, and the storage density is low.

[0073] To this end, the present disclosure provides a ferroelectric memory, which includes a plurality of memory cells, each of which includes a transistor and a 2 coupled transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor can be determined by 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor stores n bits of data, realizing polymorphic storage of the ferroelectric memory and improving the storage density of the ferroelectric memory.

[0074] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0075] See also Figure 3 The present disclosure provides a semiconductor structure, which includes a memory cell array, and a plurality of word lines 30 and a plurality of bit lines 20 electrically connected to the memory cell array. The memory cell array is used to store data, and includes a plurality of memory cells, which are arranged in an array and spaced apart, that is, the plurality of memory cells are arranged in a plurality of rows and columns, and the row direction ( Figure 3 X direction) and column direction ( Figure 3 The Y direction is perpendicular to the memory cell array to increase the storage density of the memory cell array.

[0076] A plurality of word lines 30 are arranged at intervals, and a plurality of bit lines 20 are arranged at intervals, and the extension direction of the plurality of word lines 30 intersects with the extension direction of the plurality of bit lines 20, for example, perpendicularly. Each word line 30 is coupled to memory cells arranged in rows in the memory cell array, that is, each word line 30 is coupled to a row of memory cells. Each bit line 20 is coupled to memory cells arranged in columns in the memory cell array, that is, each bit line 20 is coupled to a column of memory cells.

[0077] Continue reading Figure 3 Each storage unit stores n bits of data, and each storage unit includes a transistor 11 and 2 coupled to the transistor 11. n - 1 ferroelectric capacitor 12, n is a positive integer greater than 1. When the transistor 11 is turned on, the memory cell performs data writing or data reading.

[0078] Each ferroelectric capacitor 12 includes a first plate and a second plate that are arranged opposite to each other, and a dielectric layer filled between the first plate and the second plate. The first plate and the second plate are arranged on both sides of the dielectric layer, and the dielectric layer is made of ferroelectric material, that is, the second plate, the dielectric layer and the first plate are stacked in sequence. Figure 3 As shown, the second plate is the lower plate of the ferroelectric capacitor 12 , and the first plate is the upper plate of the ferroelectric capacitor 12 .

[0079] Due to 2 n Each of the ferroelectric capacitors 12 can be polarized according to 2 n -1 The polarization direction of a ferroelectric capacitor 12 can be determined by 2 nstorage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor 12 stores n bits of data. The storage state is 2 n -The number of ferroelectric capacitors 12 with polarization directions in a preset direction in one ferroelectric capacitor 12.

[0080] For example, see Figure 4 , when n is 2, the transistor 11 in each storage unit is connected to three ferroelectric capacitors 12, and the three ferroelectric capacitors 12 can determine four storage states to store 2-bit data. Among them, the ferroelectric capacitor 12 with the polarization direction pointing to the third direction can have 3, 2, 1 or 0, and accordingly, the three ferroelectric capacitors 12 correspond to data 00, 10, 01, 11 respectively. Figure 4 As shown, the polarization direction pointing to the third direction means that the polarization direction is upward, that is, the polarization direction points to the upper plate (first plate) of the ferroelectric capacitor 12. Of course, when n is 3, the transistor 11 in each storage unit is connected to 7 ferroelectric capacitors 12, and the three ferroelectric capacitors 12 can determine 8 storage states to store 3 bits of data.

[0081] It can be understood that when there are 3 ferroelectric capacitors 12 with polarization directions pointing to the third direction, that is, the three ferroelectric capacitors 12 are all polarized in the third direction (upward), and the three ferroelectric capacitors 12 correspond to 00, that is, the storage unit stores 00. When there are 2 polarization directions pointing to the third direction, that is, any two ferroelectric capacitors 12 of the three ferroelectric capacitors 12 are polarized in the third direction (upward), and the other ferroelectric capacitor 12 is polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 10, that is, the storage unit stores 10. When there is 1 polarization direction pointing to the third direction, that is, any one ferroelectric capacitor 12 of the three ferroelectric capacitors 12 is polarized in the third direction (upward), and the remaining two ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 01, that is, the storage unit stores 01. When the number of ferroelectric capacitors 12 with polarization directions pointing to the third direction is 0, that is, the three ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, the three ferroelectric capacitors 12 correspond to 11, that is, the storage unit stores 11. The three ferroelectric capacitors 12 have 4 different polarization modes, and thus have 4 storage states to store 2-bit data.

[0082] See also Figure 3 and Figure 5 In some possible embodiments, 2 n -1 ferroelectric capacitors 12 are arranged in sequence along the first direction, wherein 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n-1 dielectric layer forms an integrated structure, and 2 n -1 The thickness of the dielectric layer is different so that 2 n The coercive voltage of the -1 ferroelectric capacitor 12 is different, so it has n storage states.

[0083] It can be understood that, due to the different thicknesses of the dielectric layers, the second plates are spaced apart in the thickness direction of the dielectric layer, and the adjacent second plates are connected by connecting plates to form a whole. The dielectric layers are made of the same material, and the greater the thickness of the dielectric layer, the greater the coercive voltage of the ferroelectric capacitor 12, and the greater the external voltage required for its polarization direction to flip.

[0084] In some examples, along the first direction, 2 n -1 The thickness of the dielectric layer of the ferroelectric capacitor 12 increases successively, that is, 2 n -1 second electrode plates are connected in a step shape, the second electrode plates form a step surface, and the two ends of the connecting electrode plates are respectively connected to two adjacent second electrode plates. n The coercive voltages of the ferroelectric capacitors 12 are sequentially increased, thereby reducing the leakage current between the adjacent ferroelectric capacitors 12 .

[0085] Among them, along the first direction, 2 n The coercive voltages of the ferroelectric capacitors 12 are arranged in an arithmetic progression, that is, along the first direction 2 n -1 The coercive voltage gradient of the ferroelectric capacitor 12 increases. In this way, while reducing the leakage current, the coercive voltage of each ferroelectric capacitor 12 can also have a certain degree of differentiation, avoiding the erroneous flipping of the polarization direction of the ferroelectric capacitor 12. In the example where the storage unit includes three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 can be 0.5V, 1.5V, and 2.5V respectively.

[0086] Continue reading Figure 3 and Figure 5 , 2 n -1 second plates have the same potential, for example, connected to zero potential, that is, the external voltages of the ferroelectric capacitors 12 are the same. When the external voltage is greater than the coercive voltage, the polarization direction of the ferroelectric capacitor 12 is reversed. n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor 11, and the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20, so that data is written to the ferroelectric capacitor 12 by the bit line 20, or data in the ferroelectric capacitor 12 is read out to the bit line 20. The gate of the transistor 11 is connected to the corresponding word line 30, and the word line 30 controls the opening or closing of the transistor 11.

[0087] like Figure 3 and Figure 5 As shown, 2 n-1 first electrode plate is formed integrally and connected to the bit line 20 through the transistor 11, 2 n -1 second electrode plate is formed into one piece and connected to the same power line PL so that 2 n The voltage difference between the first and second plates arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has the same applied voltage, while 2 n -1 ferroelectric capacitor 12 has different coercive voltages. According to the relationship between the applied voltage and the coercive voltage, 2 n - The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0088] See also Figures 6 to 9 , 2 n -1 ferroelectric capacitor 12 with 2 n storage states, i.e., has 2 n There are four different polarization states, each storage state can correspond to one data, so as to store n-bit data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0089] like Figure 6 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the first plate, and this polarization state corresponds to 00. Figure 7 As shown, the polarization direction of two of the three ferroelectric capacitors 12 points to the first plate, and this polarization state corresponds to 10. Figure 8 As shown, the polarization direction of one of the three ferroelectric capacitors 12 points to the first electrode plate, and the polarization state corresponds to 01. Fig. 9 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the second electrode plate, and the polarization state corresponds to 11.

[0090] See also Fig.10 and Fig.11 In some other possible embodiments, 2 n - 1 ferroelectric capacitors 12 are arranged in sequence along the first direction, 2 n -1 first electrode plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n -1 second plates are arranged at intervals, so that the applied voltages of the ferroelectric capacitors 12 are different (for example, arranged equidistantly) and the applied voltages of the ferroelectric capacitors 12 remain unchanged, thereby having n storage states. In the example where the storage unit includes three ferroelectric capacitors 12, the applied voltages of the three ferroelectric capacitors 12 can be -1V, 0V, and 1V, respectively.

[0091] Among them, 2 n -1 dielectric layer thickness is equal to that of 2 n -1 The coercive voltage of each ferroelectric capacitor 12 is the same, which is convenient for manufacturing. Due to the coercive voltage of each ferroelectric capacitor 12, it is not necessary to distinguish each ferroelectric capacitor 12. By adjusting the external voltage of each ferroelectric capacitor 12, it is possible to control the writing of data into the storage unit or the reading of data from the storage unit. n The lengths of the second plates are the same so that the ferroelectric capacitors 12 are the same.

[0092] It can be understood that in order to achieve connection between the ferroelectric capacitors 12, a connecting plate is connected between two adjacent first plates along the first direction, and a connecting layer is connected between two adjacent dielectric layers, so that the first plates are integrated, the dielectric layers are integrated, and the second plates are arranged at intervals.

[0093] In order to realize data writing or data reading, such as Fig.11 As shown, 2 n -1 The second plate potentials are different, 2 n −1 first electrode plate is connected to one of the source and drain of the corresponding transistor 11 , the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20 , and the gate of the transistor 11 is connected to the corresponding word line 30 .

[0094] like Fig.10 As shown, 2 n -1 first electrode plate is formed integrally and connected to the bit line 20 through the transistor 11, 2 n -1 second plate is connected to different power lines, so that 2 n The voltage difference between the first and second plates arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has different applied voltages, and according to the relationship between the applied voltage and the coercive voltage, 2 n - The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0095] See also Figures 10 to 15 , 2 n -1 ferroelectric capacitor 12 with 2 n storage states, i.e., has 2 n There are four different polarization states, each storage state can correspond to a data, so as to store n bits of data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0096] like Fig.12As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the first plate, and this polarization state corresponds to 00. Fig.13 As shown, the polarization direction of two of the three ferroelectric capacitors 12 points to the first plate, and this polarization state corresponds to 10. Fig.14 As shown, the polarization direction of one of the three ferroelectric capacitors 12 points to the first electrode plate, and the polarization state corresponds to 01. Fig.15 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the second electrode plate, and the polarization state corresponds to 11.

[0097] The type and structure of the transistor 11 in the embodiment of the present disclosure are not limited. The transistor 11 may be a thin film transistor (TFT) to facilitate 3D stacking. The transistor 11 may also be a planar transistor, etc., which is compatible with the dynamic random access memory (DRAM) process.

[0098] For example, Fig.11 As shown, the transistor 11 includes an active region disposed in a substrate 40, a gate dielectric layer 50 located above the active region, and a gate located on the gate dielectric layer 50, and the word line 30 is used as the gate. The first plates of the ferroelectric capacitor 12 are connected to form an integral body and are connected to the active region through a plug 60, and the second plates of the ferroelectric capacitor 12 are respectively connected to wires 70 and connected to the peripheral circuit through the wires 70 to provide different voltage values ​​to the second plates of the ferroelectric capacitor 12 so that the second plates of the ferroelectric capacitor 12 are at different potentials.

[0099] In summary, the ferroelectric memory provided by the embodiment of the present disclosure includes a memory cell array, a plurality of word lines 30 and a plurality of bit lines 20. The memory cell array includes a plurality of memory cells arranged in an array. Each word line 30 is coupled to a memory cell arranged in a row in the memory cell array. Each bit line 20 is coupled to a memory cell arranged in a column in the memory cell array. Each memory cell includes a transistor 11 and a 2 coupled transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor 12 can be determined by 2 n storage states, each storage state corresponds to a data, so that 2 n - One ferroelectric capacitor 12 stores n-bit data, realizes polymorphic storage of the ferroelectric memory, and improves the storage density of the ferroelectric memory.

[0100] The present disclosure also provides a method for reading data from a ferroelectric memory, which is applied to the above-mentioned ferroelectric memory. Figure 3 , Figure 5 , Fig.10 and Fig.11 The specific structure of the ferroelectric memory can be found in the above embodiment, which will not be described here. Fig.16 , the data reading method comprises the following steps:

[0101] Step S100: Use bit lines and transistors to connect the corresponding 2 n The first plates of -1 ferroelectric capacitors are all charged to a first voltage, and the first voltage causes the polarization direction of each ferroelectric capacitor to point to the first plate. When the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows positive charge to the bit line.

[0102] The voltage on the bit line 20 is precharged to a first voltage, and the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n The first plates of the ferroelectric capacitors 12 are all charged to the first voltage, that is, the first plates of the ferroelectric capacitors 12 are all at the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate and the second plate is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 is directed to the first plate.

[0103] In 2 n -1 Before the first plate of the ferroelectric capacitor 12 is charged, 2 n -1 The polarization direction of the ferroelectric capacitor 12 can have multiple situations, so that 2 n -1 ferroelectric capacitor 12 is in different storage states to store data. n After the first plates of -1 ferroelectric capacitors 12 are charged, the polarization directions of these ferroelectric capacitors 12 all point to the first plates. If the polarization direction of each ferroelectric capacitor 12 does not change, no charge flows from the ferroelectric capacitor 12 to the bit line 20. If the polarization direction of any ferroelectric capacitor 12 is reversed, the charge of the ferroelectric capacitor 12 flows during the reversal process, and the positive charge flows from the ferroelectric capacitor 12 to the bit line 20, and the amount of the positive charge is positively correlated with the number of ferroelectric capacitors 12 that are reversed.

[0104] Step S200: acquiring data in a storage unit according to a change in the amount of charge of a bit line, wherein the storage unit stores n-bit data.

[0105] According to the change of the charge amount of the bit line 20, the data in the memory cell can be obtained. n -1 The polarization direction of a ferroelectric capacitor 12 can be determined by 2 n There are storage states, each storage state corresponds to one type of data, and the storage unit can store n bits of data.

[0106] In some examples, such as Figure 5 As shown, 2 n - 1 ferroelectric capacitors 12 are arranged in sequence along the first direction, 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n -1 dielectric layer forms an integrated structure, and 2 n -1 dielectric layer has different thickness. In order to facilitate the description of the data reading process of the ferroelectric memory, n is set to 2, that is, each storage unit has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, 1.5V respectively, and the external voltages of the second plates of the three ferroelectric capacitors 12 are all 0V.

[0107] See also Fig.17 , precharge the voltage of the bit line 20 to a first voltage, the absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage, for example, the first voltage can be -3 V. Turn on the word line 30 and the transistor 11, and the potentials of the first plates of the three ferroelectric capacitors 12 are all the first voltage, that is, all -3 V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization directions of the three ferroelectric capacitors 12 are all pointing to the first plate.

[0108] See also Fig.18 , before the word line 30 and the transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the first plate, the three ferroelectric capacitors 12 store 00. After the word line 30 and the transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0109] See also Fig.19 , before the word line 30 and the transistor 11 are turned on, if the polarization directions of the two ferroelectric capacitors 12 are both pointing to the first plate, the polarization direction of one ferroelectric capacitor 12 is pointing to the second plate, for example, the polarization direction of the first ferroelectric capacitor 12 is pointing to the second plate, and the three ferroelectric capacitors 12 store 10. After the word line 30 and the transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 is reversed, and the first plate of the ferroelectric capacitor 12 changes from positive charge to negative charge, which is equivalent to two positive charges flowing to the bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change, and do not contribute to the flow of charge, and a total of two positive charges flow to the bit line 20.

[0110] See also Fig. 20, before the word line 30 and the transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points to the first plate, the polarization directions of two ferroelectric capacitors 12 both point to the second plate, for example, the polarization direction of the third ferroelectric capacitor 12 points to the first plate, and the three ferroelectric capacitors 12 store 01. After the word line 30 and the transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 are reversed, and the first plates of the two ferroelectric capacitors 12 change from positive charge to negative charge, equivalent to 4 positive charges flowing to the bit line 20. The polarization direction of the other ferroelectric capacitor 12 does not change, and does not contribute to the flow of charge, and a total of 4 positive charges flow to the bit line 20.

[0111] See also Fig.21 Before the word line 30 and the transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the second plate, the three ferroelectric capacitors 12 store 11. After the word line 30 and the transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 are reversed, and a total of 6 equivalent positive charges flow to the bit line 20.

[0112] The positive charge flowing out to the bit line 20 changes the voltage or current on the bit line 20. According to the change of the charge amount on the bit line 20, the corresponding data can be read out. A total of four different storage states can be read out, that is, 2 bits of data can be read out. When the data is read, the data needs to be written back to the ferroelectric capacitor 12.

[0113] In other examples, 2 n - 1 ferroelectric capacitors 12 are arranged in sequence along the first direction, 2 n -1 first electrode plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n In order to explain the data reading process of the ferroelectric memory, n is set to 2, that is, each storage unit has three ferroelectric capacitors 12, the coercive voltage of the three ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates of the three ferroelectric capacitors 12 are -1V, 0V, and 1V respectively.

[0114] See also Fig. 22 , precharge the voltage of the bit line 20 to a first voltage, the absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage, for example, the first voltage can be -3 V. Turn on the word line 30 and the transistor 11, and the potentials of the first plates of the three ferroelectric capacitors 12 are all the first voltage, that is, all -3 V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization directions of the three ferroelectric capacitors 12 are all pointing to the first plate.

[0115] See also Fig.23, before the word line 30 and the transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the first plate, the three ferroelectric capacitors 12 store 00. After the word line 30 and the transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0116] See also Fig.24 , before the word line 30 and the transistor 11 are turned on, if the polarization directions of the two ferroelectric capacitors 12 are both pointing to the first plate, the polarization direction of one ferroelectric capacitor 12 is pointing to the second plate, for example, the polarization direction of the first ferroelectric capacitor 12 is pointing to the second plate, and the three ferroelectric capacitors 12 store 10. After the word line 30 and the transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 is reversed, and the first plate of the ferroelectric capacitor 12 changes from positive charge to negative charge, which is equivalent to two positive charges flowing to the bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change, and do not contribute to the flow of charge, and a total of two positive charges flow to the bit line 20.

[0117] See also Fig.25 , before the word line 30 and the transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points to the first plate, the polarization directions of two ferroelectric capacitors 12 both point to the second plate, for example, the polarization direction of the third ferroelectric capacitor 12 points to the first plate, and the three ferroelectric capacitors 12 store 01. After the word line 30 and the transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 are reversed, and the first plates of the two ferroelectric capacitors 12 change from positive charge to negative charge, equivalent to 4 positive charges flowing to the bit line 20. The polarization direction of the other ferroelectric capacitor 12 does not change, and does not contribute to the flow of charge, and a total of 4 positive charges flow to the bit line 20.

[0118] See also Fig.26 Before the word line 30 and the transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the second plate, the three ferroelectric capacitors 12 store 11. After the word line 30 and the transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 are reversed, and a total of 6 equivalent positive charges flow to the bit line 20.

[0119] The positive charge flowing out to the bit line 20 changes the voltage or current on the bit line 20. According to the change of the charge amount on the bit line 20, the corresponding data can be read out. A total of four different storage states can be read out, that is, 2 bits of data can be read out. When the data is read, the data needs to be written back to the ferroelectric capacitor 12.

[0120] In summary, the data reading method of the ferroelectric memory in the embodiment of the present disclosure is applied to a ferroelectric memory of polymorphic storage, wherein each storage unit of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1.n -1 The first plates of the ferroelectric capacitors 12 are all charged to a first voltage. The first voltage makes the polarization direction of each ferroelectric capacitor 12 point to the first plate. The polarization direction of the ferroelectric capacitor 12 is flipped to flow positive charge to the bit line 20. The data in the storage unit can be obtained according to the change in the charge amount of the bit line 20, thereby realizing the reading of n-bit data and improving the storage density of the ferroelectric memory.

[0121] The present disclosure also provides a method for writing data into a ferroelectric memory, which is applied to the ferroelectric memory. Figure 3 , Figure 5 , Fig.30 and Fig.31 The specific structure of the ferroelectric memory can be found in the above embodiment, which will not be described here. Fig. 27 , the data writing method may include the following steps:

[0122] Step a: Use bit lines and transistors to connect the corresponding 2 n - A first electrode plate of a ferroelectric capacitor is charged to a first voltage, and the first voltage causes the polarization direction of each storage capacitor to point to the first electrode plate, so as to initialize each ferroelectric capacitor.

[0123] The voltage on the bit line 20 is precharged to a first voltage, and the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n -1 The first plates of the ferroelectric capacitors 12 are all charged to the first voltage, that is, the potentials of the first plates of these ferroelectric capacitors 12 are all the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate and the second plate is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 is directed to the first plate, completing 2 n - Initialization of a ferroelectric capacitor 12.

[0124] Step b: Apply a write voltage to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to one type of data, some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors whose polarization directions flip.

[0125] A write voltage is applied to the bit line 20, and the corresponding 2 n -1 ferroelectric capacitor 12 writes data so that the memory cell stores data. The write voltage has a value of 2 n voltage values, each voltage value corresponds to 2 n -1 storage state of a ferroelectric capacitor 12, and corresponding to a data. The storage state refers to 2 n-1 polarization state of the ferroelectric capacitor 12, which can be 2 n -The number of ferroelectric capacitors 12 whose polarization direction points to the second electrode plate (or the first electrode plate) in one ferroelectric capacitor 12.

[0126] It is understandable that the write voltage is 2 n One of the voltage values ​​makes 2 n -1 ferroelectric capacitor 12 polarization direction does not change, that is, the number of ferroelectric capacitors 12 whose polarization direction is reversed is 0, and the other voltage value makes 2 n -1 The polarization directions of all ferroelectric capacitors 12 are reversed, that is, the number of ferroelectric capacitors 12 whose polarization directions are reversed is 2 n -1. The remaining voltage values ​​are 2 n The polarization directions of some of the ferroelectric capacitors 12 in the -1 ferroelectric capacitor 12 are reversed, and the number of the reversed ferroelectric capacitors 12 corresponding to each voltage value in the remaining voltage values ​​is different, ranging from 0 to 2. n Different voltage values ​​cause different numbers of ferroelectric capacitors 12 whose polarization directions are reversed, so that each voltage value corresponds to different data.

[0127] For example, when n is 2, the write voltage has 4 voltage values, which are the first preset value, the second preset value, the third preset value and the fourth preset value. Wherein, when the voltage value of the write voltage is the first preset value, the polarization direction of 0 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the second preset value, the polarization direction of 1 ferroelectric capacitor 12 is reversed. When the voltage value of the write voltage is the third preset value, the polarization direction of 2 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the fourth preset value, the polarization direction of 3 ferroelectric capacitors 12 is reversed.

[0128] In some examples, 2 n - 1 ferroelectric capacitors 12 are arranged in sequence along the first direction, 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n -1 dielectric layer forms an integrated structure, and 2 n -1 dielectric layer has different thickness. In order to facilitate the description of the data writing process of the ferroelectric memory, n is set to 2, that is, each storage unit has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, 1.5V respectively, and the voltage value of the external voltage of the second plate of the three ferroelectric capacitors 12 is 0V.

[0129] See also Fig.28, precharge the voltage of the bit line 20 to a first voltage, the absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage, for example, the first voltage can be -3 V. Turn on the word line 30 and the transistor 11, and the potentials of the first plates of the three ferroelectric capacitors 12 are all the first voltage, that is, all -3 V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization directions of the three ferroelectric capacitors 12 are all pointing to the first plate.

[0130] See also Fig.29 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the first preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the first preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of the three ferroelectric capacitors 12 all point to the first plate, and the polarization directions do not change, and the data 00 is stored. For example, the first preset value is 0V, and the difference between it and the voltage value 0V of the external voltage is less than the coercive voltage of each ferroelectric capacitor 12.

[0131] See also Fig.30 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the second preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the second preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. Among the three ferroelectric capacitors 12, only one ferroelectric capacitor 12 has an absolute value of the difference between the second preset value and the voltage value of the external voltage that is greater than the coercive voltage of the ferroelectric capacitor 12. The polarization direction of the ferroelectric capacitor 12 is reversed, and the polarization directions of the other two ferroelectric capacitors 12 remain unchanged, and data 10 is stored. For example, the second preset value is 1V, and the polarization direction of the ferroelectric capacitor 12 with a coercive voltage of 0.5V is reversed, and the polarization directions of the other two ferroelectric capacitors 12 remain unchanged.

[0132] See also Fig.31 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the third preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the third preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute value of the difference between the third preset value of two ferroelectric capacitors 12 and the voltage value of the external voltage is greater than the coercive voltage of the ferroelectric capacitor 12, and the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, and the data 01 is stored. For example, when the third preset value is 2V and the coercive voltage is 0.5V and 1V, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization direction of the other ferroelectric capacitor 12 remains unchanged.

[0133] See also Fig.32, a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a fourth preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the fourth preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute values ​​of the differences between the fourth preset values ​​of the three ferroelectric capacitors 12 and the voltage value of the external voltage are all greater than the coercive voltage, and the polarization directions of the three ferroelectric capacitors 12 are reversed to store data 11. For example, the third preset value is 3V, and the polarization directions of the ferroelectric capacitors 12 with coercive voltages of 0.5V, 1V, and 1.5V are reversed.

[0134] In other examples, 2 n - 1 ferroelectric capacitors 12 are arranged in sequence along the first direction, 2 n -1 first electrode plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n In order to explain the data writing process of the ferroelectric memory, n is set to 2, that is, each storage unit has 3 ferroelectric capacitors 12, the coercive voltage of the 3 ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates of the 3 ferroelectric capacitors 12 are -1V, 0V, and 1V respectively.

[0135] See also Fig.33 , precharge the voltage of the bit line 20 to a first voltage, the absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage, for example, the first voltage can be -3 V. Turn on the word line 30 and the transistor 11, and the potentials of the first plates of the three ferroelectric capacitors 12 are all the first voltage, that is, all -3 V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization directions of the three ferroelectric capacitors 12 are all pointing to the first plate.

[0136] See also Fig.34 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the first preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the first preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage values ​​of the external voltage, and the voltage values ​​of the external voltage are different. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than 1.5V, that is, they are all less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of the three ferroelectric capacitors 12 all point to the first plate, and the polarization directions do not change, and the data 00 is stored. For example, the first preset value is 0V, and the absolute values ​​of the differences between the first preset value and -1V, 0V, and 1V are all less than 1.5V.

[0137] See also Fig.35, a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the second preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the second preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. Among the three ferroelectric capacitors 12, only one ferroelectric capacitor 12 has an absolute value of the difference between the second preset value and the voltage value of the external voltage greater than the coercive voltage of the ferroelectric capacitor 12. The polarization direction of the ferroelectric capacitor 12 is reversed, and the polarization directions of the other two ferroelectric capacitors 12 remain unchanged, and the data 10 is stored. For example, the second preset value is 1V, and the polarization direction of the ferroelectric capacitor 12 with the voltage value of the external voltage of -1V is reversed, and the polarization directions of the other two ferroelectric capacitors 12 remain unchanged.

[0138] See also Fig.36 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the third preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the third preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute value of the difference between the third preset value of two ferroelectric capacitors 12 and the voltage value of the external voltage is greater than the coercive voltage of the ferroelectric capacitor 12, the polarization direction of the ferroelectric capacitor 12 is reversed, and the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, and the data 01 is stored. For example, the third preset value is 2V, the polarization directions of the ferroelectric capacitors 12 with the voltage values ​​of the external voltage of -1V and 0V are reversed, and the polarization direction of the ferroelectric capacitor 12 with the voltage value of the external voltage of 1V remains unchanged.

[0139] See also Fig.37 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a fourth preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the fourth preset values, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute values ​​of the differences between the fourth preset values ​​of the three ferroelectric capacitors 12 and the voltage value of the external voltage are all greater than the coercive voltage, and the polarization directions of the three ferroelectric capacitors 12 are reversed to store data 11. For example, when the third preset value is 3V, the polarization directions of the ferroelectric capacitors 12 with the voltage values ​​of the external voltage being -1V, 0V, and 1V are reversed.

[0140] In summary, the data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to a ferroelectric memory of polymorphic storage, wherein each storage unit of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1. n-1 The first plates of the ferroelectric capacitors 12 are all charged to a first voltage, and the first voltage makes the polarization direction of each ferroelectric capacitor 12 point to the first plate, so that each ferroelectric capacitor 12 is initialized. Then, different voltage values ​​of the write voltage are used, each voltage value corresponds to a type of data, and some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors 12 to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors 12 whose polarization direction flips, so as to realize the writing of n-bit data and improve the storage density of the ferroelectric memory.

[0141] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A ferroelectric memory, characterized in that: include: A memory cell array, wherein the memory cell array comprises a plurality of memory cells arranged in an array, each of the memory cells storing n-bit data, wherein each of the memory cells comprises: a transistor and 2 coupled to the transistor n - 1 ferroelectric capacitor, wherein n is a positive integer greater than 1; A plurality of word lines, each of the word lines being coupled to the memory cells arranged in a row in the memory cell array; A plurality of bit lines are provided, each of the bit lines being coupled to the memory cells arranged in columns in the memory cell array.

2. The ferroelectric memory according to claim 1, characterized in that: Each of the ferroelectric capacitors comprises a first plate and a second plate which are arranged opposite to each other, and a dielectric layer filled between the first plate and the second plate; 2 n - 1 said ferroelectric capacitors are arranged in sequence along a first direction, 2 n - 1 the first electrode plates are connected into an integrated structure, 2 n -1 the second electrode plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, and the thickness of each dielectric layer is different.

3. The ferroelectric memory according to claim 2, characterized in that: Along the first direction, 2 n -1 The thickness of the dielectric layer of the ferroelectric capacitor increases sequentially.

4. The ferroelectric memory according to claim 3, characterized in that: Along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors are arranged in an arithmetic progression.

5. The ferroelectric memory according to any one of claims 2 to 4, characterized in that: 2 n -1 the second plate has the same potential, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

6. The ferroelectric memory according to claim 1, wherein: Each of the ferroelectric capacitors comprises a first plate and a second plate which are arranged opposite to each other, and a dielectric layer filled between the first plate and the second plate; 2 n - 1 said ferroelectric capacitors are arranged in sequence along a first direction, 2 n - 1 the first electrode plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, 2 n -1 of the second electrode plates are arranged at intervals.

7. The ferroelectric memory according to claim 6, characterized in that: 2 n -1 The thickness of the dielectric layer is equal to that of 2 n -1 The coercive voltages of the ferroelectric capacitors are the same.

8. The ferroelectric memory according to claim 7, characterized in that: 2 n -1 The length of the second electrode plate is the same.

9. The ferroelectric memory according to any one of claims 6 to 8, characterized in that: 2 n -1 The second plate potentials are different, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

10. A method for reading data from a ferroelectric memory, characterized in that: Applied to the ferroelectric memory according to any one of claims 1 to 9, the data reading method comprises: Using bit lines and transistors, the corresponding 2 n - the first plates of the ferroelectric capacitors are all charged to a first voltage, wherein the first voltage causes the polarization direction of each of the ferroelectric capacitors to point to the first plate, and when the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows positive charge to the bit line; The data in the storage unit is acquired according to the change of the charge amount of the bit line, wherein the storage unit stores n bits of the data.

11. A method for writing data into a ferroelectric memory, characterized in that: Applied to the ferroelectric memory according to any one of claims 1 to 9, the data writing method comprises: Using bit lines and transistors, the corresponding 2 n - charging a first plate of a ferroelectric capacitor to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor to point to the first plate, so as to initialize each ferroelectric capacitor; A write voltage is applied to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to a type of data, some of the voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors to flip their polarization directions.

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