Asynchronous SRAM (Static Random Access Memory) address translation control circuit

Abstract

The invention discloses an asynchronous SRAM (Static Random Access Memory) address translation control circuit, which belongs to the field of semiconductor integrated circuits and comprises a transmission gate circuit, a latch loop and a delay module, the transmission gate circuit is connected between a pre node and the latch loops, and when high and low levels of an input signal are switched, the transmission gate circuit alternately transmits the voltage on the pre node to the two latch loops; the latch loop is connected between the transmission gate circuit and the output, latches the current level, and transmits the level to the output end as a clock output; the delay module adjusts the width of the output pulse and filters part of input burrs. According to the invention, pulse width adjustment can be carried out on an input pulse signal, and a certain anti-noise interference capability is possessed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to an asynchronous SRAM address conversion control circuit. Background Art

[0002] In recent years, the Internet, computers, big data and artificial intelligence have developed rapidly, and various terminal electronic products such as mobile phones, computers, mobile wearable devices, etc. have been continuously updated and iterated. Various application scenarios such as smart home appliances, virtual reality technology, and cloud services are constantly being developed. The development boom of the Internet of Things and high-performance computing has also brought opportunities for the transformation of embedded memory. The level of recent generation of ultra-large-scale integrated circuits and system-on-chips has been continuously improved, requiring a large number of memory IPs.

[0003] SRAM plays an important role in embedded memory due to its advantages such as fast read and write speed, good process compatibility, and easy compiler integration. Among them, asynchronous SRAM does not require input clock control and has the advantages of low power consumption, high speed and high reliability. Although asynchronous SRAM does not have an external input clock, each internal module needs to meet certain timing requirements. At present, some asynchronous SRAMs use address conversion monitoring circuits to generate internal clock signals. When the address changes, a valid pulse is generated to control the SRAM to achieve read and write operations.

[0004] The current address conversion monitoring module has the following problems: each address requires a delay unit and combinational logic to generate a pulse of effective width, which requires a large amount of chip area; due to the difference in the arrival time of each address, each address will generate an effective pulse width, and finally the final effective pulse is generated through the OR gate, so the final effective pulse width may change accordingly, and even generate certain glitch interference after the effective pulse, thereby affecting the normal read and write operations of the memory. Summary of the invention

[0005] The object of the present invention is to provide an asynchronous SRAM address conversion control circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides an asynchronous SRAM address conversion control circuit, comprising: a transmission gate circuit, a latch circuit and a delay module;

[0007] The transmission gate circuit is connected between the pre node and the latch loop, and when the input signal is converted between high and low levels, the transmission gate circuit alternately transmits the voltage on the pre node to the two latch loops respectively;

[0008] The latch circuit is connected between the transmission gate circuit and the output, latches the current level, and transmits the level to the output end as a clock output;

[0009] The delay module adjusts the output pulse width and filters part of the input glitches.

[0010] In one embodiment, the asynchronous SRAM address conversion control circuit includes PMOS transistors P1-P9, NMOS transistors N1-N9, transmission gates TG1 and TG2, and a delay module; and also includes an input terminal and an output terminal, the input signal is a, and the output signal is out;

[0011] The drain of the PMOS transistor P1 is connected to the node pre, the gate is connected to the node rst, and the source is connected to the power supply; the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the gate is connected to the node an, and the source is connected to the power supply; the drain of the PMOS transistor P3 is connected to the node net3, the gate is connected to the node net1, and the source is connected to the drain of the PMOS transistor P2; the drain of the PMOS transistor P4 is connected to the node out, the gate is connected to the node an, and the source is connected to the node net1; the drain of the PMOS transistor P5 is connected to the node out, the gate is connected to the node net3, and the source is connected to the power supply; the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P7, the gate is connected to the node a, and the source is connected to the power supply; the drain of the PMOS transistor P7 is connected to the node net3, the gate is connected to the node net2, and the source is connected to the drain of the PMOS transistor P6; the drain of the PMOS transistor P8 is connected to the node out, the gate is connected to the node a, and the source is connected to the node net2; the drain of the PMOS transistor P9 is connected to the node an, the gate is connected to the node a, and the source is connected to the power supply;

[0012] The drain of the NMOS transistor N1 is connected to the node pre, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N2 is connected to the source of the NMOS transistor N3, the gate is connected to the node a, and the source is connected to the ground; the drain of the NMOS transistor N3 is connected to the node net3, the gate is connected to the node net1, and the source is connected to the drain of the NMOS transistor N2; the drain of the NMOS transistor N4 is connected to the node net1, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N5 is connected to the node out, the gate is connected to the node net3, and the source is connected to the ground; the drain of the NMOS transistor N6 is connected to the source of the NMOS transistor N7, the gate is connected to the node an, and the source is connected to the ground; the drain of the NMOS transistor N7 is connected to the node net3, the gate is connected to the node net2, and the source is connected to the drain of the NMOS transistor N6; the drain of the NMOS transistor N8 is connected to the node net2, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N9 is connected to the node an, the gate is connected to the node a, and the source is connected to the ground;

[0013] One end of the transmission gate TG1 is connected to the node pre, and the other end is connected to the node net1; one end of the transmission gate TG2 is connected to the node pre, and the other end is connected to the node net2;

[0014] One end of the delay module is connected to the node out, and the other end is connected to the node rst.

[0015] In one embodiment, the input signal of the node a controls the transmission gates TG1 and TG2 to transmit the pre signal to the latch loop alternately during the high level period and the low level period of a;

[0016] Wherein, the PMOS transistor P2, the PMOS transistor P3, the NMOS transistor N2 and the NMOS transistor N3 form a first clocked inverter, the PMOS transistor P5 and the NMOS transistor N5 form a common inverter; the PMOS transistor P4, the first clocked inverter and the common inverter form a first latch loop;

[0017] PMOS transistor P6, PMOS transistor P7, NMOS transistor N6 and NMOS transistor N7 form a second clocked inverter, the PMOS transistor P8, the second clocked inverter and the common inverter form a second latch loop, and the level of the output terminal out is controlled by two latch loops.

[0018] In one embodiment, when the signal of the node rst is at a low level and the signal of the node a is at a high level, the transmission gate TG2 is turned on, net2 is pulled up to a high level, the transmission gate TG1 is not turned on, and the first latch loop is valid; when the signal of the node rst is at a low level and the signal of the node a is at a low level, the transmission gate TG1 is turned on, net1 is pulled up to a high level, the transmission gate TG2 is not turned on, and the second latch loop is valid; the two transmission gates and the latch loop work alternately, monitor the input pulse signal, and pull the output end high by pre-charging the latch.

[0019] In one embodiment, when the output of the output terminal out is at a high level, after passing through a delay module, the node rst will become a high level. At this time, no matter how the node a changes, the output terminal out is 0; by adjusting the delay module, the output pulse width is effectively adjusted to reduce the interference of input noise.

[0020] In one implementation, the transmission gates TG1 and TG2 are respectively composed of one PMOS transistor and one NMOS transistor.

[0021] The asynchronous SRAM address conversion control circuit provided by the present invention has the following beneficial effects:

[0022] (1) By detecting edge signals, an effective pulse width can be generated for asynchronous SRAM timing, without the need for a large pulse width signal to be input from the previous stage;

[0023] (2) By adjusting the time of the delay chain of the delay module, the effective width of the output out can be adjusted to avoid signal interference caused by the time difference of the input signal;

[0024] (3) Within the delay time twice after the edge is detected, even if there is noise interference, it will not affect the width of the output terminal out, and the noise interference can be effectively filtered. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural block diagram of address translation monitoring.

[0026] Figure 2 It is a structural diagram of the address conversion control circuit of the present invention.

[0027] Figure 3 This is a schematic diagram of the circuit operation with low input level.

[0028] Figure 4 This is the circuit operation diagram for the input rising edge.

[0029] Figure 5 It is a functional simulation diagram of the address conversion control circuit of the present invention. DETAILED DESCRIPTION

[0030] The following is a further detailed description of an asynchronous SRAM address conversion control circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] like Figure 1 As shown in the figure, after the address input passes through the XOR gate and the OR gate, a pulse is generated and input into the address conversion control circuit. Since the input time of each address is different, the output pulse width is different, and there is even glitch noise interference. The address conversion control circuit detects the edge of the input pulse, generates an effective and stable pulse, and outputs it to the asynchronous SRAM as the clock of the asynchronous SRAM to ensure its normal operation.

[0032] The present invention provides an asynchronous SRAM address conversion control circuit, such as Figure 2As shown, it includes: a transmission gate circuit, a latch circuit and a delay module. The transmission gate circuit is connected between the pre node and the latch circuit. When the input signal is high or low level, the transmission gate circuit alternately transmits the voltage on the pre node to the two latch circuits respectively; the latch circuit is connected between the transmission gate circuit and the output, latches the current level, and transmits the level to the output end as a clock output; the delay module adjusts the output pulse width and filters some input glitches.

[0033] Please continue to read for details Figure 2 The asynchronous SRAM address conversion control circuit is composed of 9 PMOS transistors (PMOS tube P1~PMOS tube P9), 9 NMOS transistors (NMOS tube N1~NMOS tube N9), two transmission gates (TG1 and TG2) and a delay module; it has 1 input end and 1 output end, the input signal is a, and the output signal is out.

[0034] The inverter composed of PMOS tube P9 and NMOS tube N9 is used to generate the opposite signal an of the input signal a, and the signals a and an jointly control the transmission gate and the latch circuit. Transmission gates TG1 and TG2 transmit the pre signal to the latch circuit. Since their control signals are opposite, only one transmission gate is in the open state at the same time. PMOS tube P2, PMOS tube P3, NMOS tube N2, and NMOS tube N3 form a clocked inverter 1, and PMOS tube P6, PMOS tube P7, NMOS tube N6, and NMOS tube N7 form a clocked inverter 2. PMOS tube P4, clocked inverter 1, PMOS tube P5, and NMOS tube N5 together form a latch circuit 1, which latches data when a is a high level. Transmission tube P8, clocked inverter 2, PMOS transistor P5, and NMOS transistor N5 together form a latch circuit 2, which latches data when a is a low level. Since the control signals are opposite, only one of latch circuit 1 and latch circuit 2 will be in the open state at the same time. The rst signal controls the pull-down NMOS tubes N4 and N8. As long as the rst signal is high, a path will be formed between the ground and out, pulling out low. The delay module delay is used to control the width of the generated pulse and the effective time of filtering noise.

[0035] like Figure 5 As shown, the output out is low level in the power-on reset state. Before the first rising edge of the input terminal arrives, a is low level. At this time, the circuit working diagram is as follows Figure 3As shown. The pre signal becomes high level under the action of the delay module and the inverter. The transmission gate TG1 is turned on, connecting the pre signal and net1 together, and net1 is precharged to a high level. The clocked inverter 1 and the PMOS tube P4 are in the off state, and the level of net1 cannot be transmitted to the output end out. At this time, the transmission gate TG2 is not turned on, and net2 cannot be precharged to a high level. The clocked inverter 2 and the PMOS tube P8 are turned on, and the low level is latched at this time, and the output of the out end is 0.

[0036] When the rising edge of input a arrives, a changes from low level to high level. The circuit working diagram at this time is as follows Figure 4 As shown. The transmission gate TG1 is closed, and the transmission gate TG2 is turned on, connecting the pre signal and net2 together. At this time, net2 is precharged to a high level. The clocked inverter 2 and the PMOS tube P8 are closed, while the clocked inverter 1 and the PMOS tube P4 are turned on, transmitting the precharged high level of net1 to the output end out and latching it, so a high level will be output at the rising edge. After the delay module has passed, the rst signal becomes a high level, which will directly pull the out end down. At this time, the out end becomes a low level, so the pulse width of the output end out is the width of the delay module. By controlling the width of the delay module delay, a clock can be accurately generated to control the asynchronous SRAM. Rst is the pulse of out delayed by the delay module, so the pulse width is consistent with out. During the period when rst is high, no matter how the input a changes, the output end out will remain at a low level, which avoids the interference of glitches on the output to a certain extent.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An asynchronous SRAM address conversion control circuit, characterized in that: include: Transmission gate circuit, latch circuit and delay module; The transmission gate circuit is connected between the pre node and the latch loop. When the input signal is switched between high and low levels, the transmission gate circuit alternately transmits the voltage on the pre node to the two latch loops respectively. The latch circuit is connected between the transmission gate circuit and the output, latches the current level, and transmits the level to the output end as a clock output; The delay module adjusts the output pulse width and filters part of the input glitches.

2. The asynchronous SRAM address conversion control circuit according to claim 1, characterized in that: The asynchronous SRAM address conversion control circuit includes PMOS transistors P1-P9, NMOS transistors N1-N9, transmission gates TG1 and TG2, and a delay module; in addition, it also includes an input terminal and an output terminal, the input signal is a, and the output signal is out; The drain of the PMOS transistor P1 is connected to the node pre, the gate is connected to the node rst, and the source is connected to the power supply; the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the gate is connected to the node an, and the source is connected to the power supply; the drain of the PMOS transistor P3 is connected to the node net3, the gate is connected to the node net1, and the source is connected to the drain of the PMOS transistor P2; the drain of the PMOS transistor P4 is connected to the node out, the gate is connected to the node an, and the source is connected to the node net1; the drain of the PMOS transistor P5 is connected to the node out, the gate is connected to the node net3, and the source is connected to the power supply; the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P7, the gate is connected to the node a, and the source is connected to the power supply; the drain of the PMOS transistor P7 is connected to the node net3, the gate is connected to the node net2, and the source is connected to the drain of the PMOS transistor P6; the drain of the PMOS transistor P8 is connected to the node out, the gate is connected to the node a, and the source is connected to the node net2; the drain of the PMOS transistor P9 is connected to the node an, the gate is connected to the node a, and the source is connected to the power supply; The drain of the NMOS transistor N1 is connected to the node pre, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N2 is connected to the source of the NMOS transistor N3, the gate is connected to the node a, and the source is connected to the ground; the drain of the NMOS transistor N3 is connected to the node net3, the gate is connected to the node net1, and the source is connected to the drain of the NMOS transistor N2; the drain of the NMOS transistor N4 is connected to the node net1, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N5 is connected to the node out, the gate is connected to the node net3, and the source is connected to the ground; the drain of the NMOS transistor N6 is connected to the source of the NMOS transistor N7, the gate is connected to the node an, and the source is connected to the ground; the drain of the NMOS transistor N7 is connected to the node net3, the gate is connected to the node net2, and the source is connected to the drain of the NMOS transistor N6; the drain of the NMOS transistor N8 is connected to the node net2, the gate is connected to the node rst, and the source is connected to the ground; the drain of the NMOS transistor N9 is connected to the node an, the gate is connected to the node a, and the source is connected to the ground; One end of the transmission gate TG1 is connected to the node pre, and the other end is connected to the node net1; one end of the transmission gate TG2 is connected to the node pre, and the other end is connected to the node net2; One end of the delay module is connected to the node out, and the other end is connected to the node rst.

3. The asynchronous SRAM address conversion control circuit according to claim 2, characterized in that: The input signal of the node a controls the transmission gates TG1 and TG2 to transmit the pre signal to the latch circuit alternately during the high level period and the low level period of a; Wherein, the PMOS transistor P2, the PMOS transistor P3, the NMOS transistor N2 and the NMOS transistor N3 form a first clocked inverter, the PMOS transistor P5 and the NMOS transistor N5 form a common inverter; the PMOS transistor P4, the first clocked inverter and the common inverter form a first latch loop; PMOS transistor P6, PMOS transistor P7, NMOS transistor N6 and NMOS transistor N7 form a second clocked inverter, the PMOS transistor P8, the second clocked inverter and the common inverter form a second latch loop, and the level of the output terminal out is controlled by two latch loops.

4. The asynchronous SRAM address conversion control circuit according to claim 3, characterized in that: When the signal of the node rst is low and the signal of the node a is high, the transmission gate TG2 is turned on, net2 is pulled up to a high level, the transmission gate TG1 is not turned on, and the first latch loop is valid; when the signal of the node rst is low and the signal of the node a is low, the transmission gate TG1 is turned on, net1 is pulled up to a high level, the transmission gate TG2 is not turned on, and the second latch loop is valid; the two transmission gates and the latch loop work alternately, monitor the input pulse signal, and pull the output end high by pre-charging latch.

5. The asynchronous SRAM address conversion control circuit according to claim 4, characterized in that: When the output of the output terminal out is at a high level, after passing through the delay module, the node rst will become a high level. At this time, no matter how the node a changes, the output terminal out is 0; by adjusting the delay module, the output pulse width is effectively adjusted to reduce the interference of input noise.

6. The asynchronous SRAM address conversion control circuit according to claim 2, characterized in that: The transmission gates TG1 and TG2 are respectively composed of a PMOS transistor and an NMOS transistor.

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