Level conversion circuits and chips

Abstract

The present invention discloses a level conversion circuit and chip for converting an input signal in a first voltage domain into an output signal in a second voltage domain. The level conversion circuit includes: a switch unit including a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating in the first voltage domain and connected to the second end of the first MOS transistor and the second end of the second MOS transistor; a conversion unit operating in the second voltage domain and connected to the first end of the first MOS transistor and the first end of the second MOS transistor; an output unit operating in the second voltage domain; and a clamping unit connected between the switch unit and a first low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage. The present invention reduces chip area and avoids power consumption caused by the DC current brought by the pull-down element.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a level conversion circuit and a chip. Background Art

[0002] Level shifters are common functional modules in DC / DC converters. They convert input signals from a first voltage domain to a second voltage domain and output an output signal. In a level shifter circuit where the second voltage domain is a floating voltage domain, the input signal needs to be transferred between the different voltage domains. The reference potential in the first voltage domain needs to be raised to a floating low-level signal in the second voltage domain via the level shifter circuit.

[0003] However, when the DC / DC converter is turned off, the first high level in the first voltage domain is powered off, and there is often a capacitor in the second voltage domain, which causes the holding time of the driving voltage in the second voltage domain to be prolonged, and the level conversion circuit is in a high impedance state. The driving voltage is also used to drive the logic link in the second voltage domain, such as the high-side driver. There is a risk that the driving voltage will easily cause logical confusion in the system; in the prior art, a pull-down element is added to the driving node that generates the driving voltage to ensure that when the DC / DC converter is turned off, the driving voltage is quickly pulled down to the second low voltage in the second voltage domain. However, the pull-down element not only increases the occupied area of ​​the entire chip, but also brings DC current when the level converter outputs a low-level signal, resulting in increased power consumption of the entire level conversion circuit.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a level conversion circuit. Summary of the Invention

[0005] The object of the present invention is to provide a level conversion circuit and chip, which can solve the technical problem of large chip area and high power consumption of the level conversion circuit in the prior art.

[0006] To achieve the above-mentioned object, a specific embodiment of the present invention provides the following technical solution: a level conversion circuit, configured to convert an input signal in a first voltage domain into an output signal in a second voltage domain, wherein the first voltage domain ranges from a first high voltage to a first low voltage, and the second voltage domain ranges from a second high voltage to a second low voltage, the level conversion circuit comprising:

[0007] The switch unit includes a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage;

[0008] an input unit operating between a first high voltage and a first low voltage in a first voltage domain, connected to the second end of the first MOS transistor and the second end of the second MOS transistor, respectively, and configured to turn on the first MOS transistor or the second MOS transistor according to an input signal;

[0009] a conversion unit operating between a second high voltage and a second low voltage in the second voltage domain, connected to the first end of the first MOS transistor and the first end of the second MOS transistor, respectively, and configured to generate a driving voltage at the driving node;

[0010] an output unit operating between a second high voltage and a second low voltage in the second voltage domain and connected to the driving node, the output unit being configured to generate an output signal according to the driving voltage;

[0011] The clamping unit is connected between the second end of the first MOS transistor and the second low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage.

[0012] In one or more embodiments of the present invention, the clamping unit includes a seventh MOS transistor, wherein the control terminal of the seventh MOS transistor is connected to the control signal, the first terminal is connected to the first low voltage, and the second terminal is connected to the second terminal of the first MOS transistor.

[0013] In the first state, the control signal controls the seventh MOS transistor to be turned off, and in the second state, the control signal controls the seventh MOS transistor to be turned on.

[0014] In one or more embodiments of the present invention, the seventh MOS transistor is an NMOS transistor, the control terminal is a gate, the first terminal is a source, and the second terminal is a drain, wherein:

[0015] In the first state, the control signal is a low level signal, and in the second state, the control signal is a high level signal.

[0016] In one or more embodiments of the present invention, the input unit includes a first inverter, a second inverter, a third MOS transistor and a fourth MOS transistor, wherein:

[0017] The first inverter and the second inverter respectively operate between a first high voltage and a first low voltage of the first voltage domain, an input terminal of the first inverter receives an input signal, and an input terminal of the second inverter is connected to an output terminal of the first inverter;

[0018] The control end of the third MOS transistor is connected to the output end of the first inverter, the first end is connected to the first low voltage, and the second end is connected to the second end of the first MOS transistor;

[0019] The control end of the fourth MOS transistor is connected to the output end of the second inverter, the first end is connected to the first low voltage, and the second end is connected to the second end of the first MOS transistor.

[0020] In one or more embodiments of the present invention, the conversion unit includes a first voltage stabilizing diode, a second voltage stabilizing diode, a fifth MOS transistor, and a sixth MOS transistor, wherein:

[0021] The first terminal of the first voltage stabilizing diode is connected to the second high voltage, and the second terminal is connected to the driving node;

[0022] The first end of the second voltage stabilizing diode is connected to a second high voltage;

[0023] The control end of the fifth MOS transistor is connected to the second end of the second voltage stabilizing diode, the first end is connected to the second high voltage, and the second end is connected to the driving node;

[0024] The control end of the sixth MOS transistor is connected to the driving node, the first end is connected to the second high voltage, and the second end is connected to the control end of the fifth MOS transistor.

[0025] In one or more embodiments of the present invention, the output unit includes a third inverter and a fourth inverter, wherein:

[0026] The third inverter and the fourth inverter respectively operate between the second high voltage and the second low voltage of the second voltage domain, the input end of the third inverter is connected to the driving node, the input end of the fourth inverter is connected to the output end of the third inverter, and the output end of the fourth inverter outputs the output signal.

[0027] In one or more embodiments of the present invention, the bias voltage satisfies: V bais =V S1 -V GS1 =V FLOAT -V GS1 , where V bais is the bias voltage, V S1 is the voltage at the first terminal of the first MOS tube, V GS1 is the voltage difference between the control terminal and the first terminal of the first MOS tube, V FLOAT The second lowest voltage.

[0028] In one or more embodiments of the present invention, the second high voltage, the driving voltage and the second low voltage satisfy the following conditions: V DRIVE =V PVCC -V FLOAT , where V DRIVE is the driving voltage, V PVCC is the second highest voltage, V FLOAT The second lowest voltage.

[0029] In one or more embodiments of the present invention, when the first high voltage is disconnected, the driving voltage and the second low voltage satisfy: V DRIVE =V S1 =V FLOAT .

[0030] Another aspect of the present invention further provides a chip, which includes the above-mentioned level conversion circuit.

[0031] Compared with the prior art, the level conversion circuit and chip of the present invention can realize, through the clamping unit and the control signal, that when the first high voltage is powered off, the control signal turns on the clamping unit, thereby clamping the driving voltage to the second low voltage, thereby ensuring that even if the first high voltage is powered off, the level conversion circuit still has an output signal and the output signal is at a low level. Compared with using a pull-down element, the present invention not only reduces the chip area but also avoids the power consumption caused by the DC current brought by the pull-down element. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 FIG. 4 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices to achieve the same or similar functional purpose, such as a connection through circuits or components such as switches and follower circuits. Furthermore, in the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0036] When the DC / DC converter is turned off, the first high level in the first voltage domain is powered off. In order to quickly pull down the driving voltage in the second voltage domain, the existing technology usually adds a pull-down element at the driving node that generates the driving voltage to ensure that when the DC / DC converter is turned off, the pull-down element can quickly pull down the driving voltage to the second low voltage in the second voltage domain. However, the pull-down element not only increases the occupied area of ​​the entire chip, but also when the level converter outputs a low-level signal, the pull-down element will bring in DC current, resulting in increased power consumption of the entire level conversion circuit.

[0037] In response to the above problems, Figure 1 As shown, a specific embodiment of the present invention discloses a level conversion circuit for converting an input signal PWM of a first voltage domain into an output signal LVL_OUT of a second voltage domain, wherein the range of the first voltage domain is a first high voltage V DD To the first low voltage V DGND , the range of the second voltage domain is the second high voltage V PVCC To the second low voltage V FLOAT , wherein the second voltage domain is a floating voltage domain, the level conversion circuit includes: an input unit 1, a switch unit 2, a conversion unit 3 and an output unit 4, wherein,

[0038] The switch unit 2 includes a first MOS transistor M1 and a second MOS transistor M2. The control terminal of the first MOS transistor M1 and the control terminal of the second MOS transistor M2 are both connected to the bias voltage V bais connected;

[0039] Input unit 1, operating at the first high voltage V in the first voltage domain DD With the first low voltage V DGND The input unit 1 is connected to the second end of the first MOS transistor M1 and the second end of the second MOS transistor M2 respectively, and is used to turn on the first MOS transistor M1 or the second MOS transistor M2 according to the input signal PWM;

[0040] The conversion unit 3 operates at the second high voltage V PVCCWith the second low voltage V FLOAT The first end of the first MOS transistor M1 and the first end of the second MOS transistor M2 are connected respectively. The conversion unit 3 is used to generate a driving voltage V at the driving node. DRIVE ;

[0041] Output unit 4, operates at the second high voltage V in the second voltage domain PVCC With the second low voltage V FLOAT The output unit 4 is connected to the driving node and is used to output the driving voltage V DRIVE Generate an output signal LVL_OUT;

[0042] The clamping unit 5 is connected between the switch unit 2 and the first low voltage V DGND In the first state, the first high voltage V DD The power is not turned off, the clamping unit 5 is disconnected, and in the second state, the first high voltage V DD When the power is turned off, the clamp unit 5 is turned on to turn the driving voltage V DRIVE Clamped to the second low voltage V FLOAT .

[0043] The first state is a state in which the level conversion circuit works normally. In this state, the level conversion circuit works normally. The first high voltage V DD The power is not turned off, and the level conversion circuit outputs the corresponding output signal LVL_OUT according to the input signal PWM; the second state is that the level conversion circuit is turned off, that is, the first high voltage V DD In the case of power failure, when the input signal PWM does not exist, the clamp unit 5 turns on the switch unit 2 and drives the voltage V DRIVE Clamped to the second low voltage V FLOAT , the output signal LVL_OUT of the level conversion circuit exists and is at a low level.

[0044] In one embodiment, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, the control end is the gate, the first end is the source, and the second end is the drain.

[0045] In one embodiment, the clamping unit 5 includes a seventh MOS transistor M7, wherein the control terminal of the seventh MOS transistor M7 is connected to the control signal OFF, the first terminal is connected to the first low voltage, and the second terminal is connected to the second terminal of the first MOS transistor.

[0046] In the first state, the control signal OFF turns off the seventh MOS transistor M7. In the second state, the control signal OFF turns on the seventh MOS transistor M7. Then, the seventh MOS transistor M7 pulls down the voltage of the second end of the first MOS transistor M1 to the first low voltage V DGND At this time, the voltage at the control end of the first MOS tube M1 is the bias voltage V bais, so the first MOS tube M1 is turned on; in this embodiment, the second high voltage V PVCC , driving voltage V DRIVE and the second low voltage V FLOAT Satisfy between: =V PVCC -V FLOAT , and the bias voltage V bais Satisfaction: V bais =V S1 -V GS1 =V FLOAT -V GS1 , where V S1 is the voltage at the first terminal of the first MOS tube, V GS1 is the voltage difference between the control terminal and the first terminal of the first MOS tube, V FLOAT is the second low voltage. Therefore, when the first MOS tube M1 is turned on, the driving voltage V DRIVE and the second low voltage V FLOAT Between: V DRIVE =V S1 =V FLOAT , and even if there is no input signal PWM, the second voltage domain can generate a driving voltage V DRIVE , and the driving voltage V DRIVE is clamped to the second low voltage V FLOAT .

[0047] In one embodiment, the seventh MOS transistor M7 is an NMOS transistor, the control terminal is a gate, the first terminal is a source, and the second terminal is a drain, wherein:

[0048] In the first state, the control signal OFF is a low level signal, and in the second state, the control signal OFF is a high level signal.

[0049] In one embodiment, the input unit 1 includes a first inverter U1, a second inverter U2, a third MOS transistor M3 and a fourth MOS transistor M4, wherein:

[0050] The first inverter U1 and the second inverter U2 operate at a first high voltage V DD and the first low voltage V DGND The input terminal of the first inverter U1 is connected to the input signal PWM, and the first inverter U1 is used to generate a first signal V according to the input signal PWM. A ;

[0051] The input end of the second inverter U2 is connected to the output end of the first inverter U1. The second inverter U2 is used to generate a first signal V A Generate a second signal V B ;

[0052] The control end of the third MOS tube M3 is connected to the output end of the first inverter U1, and the first end is connected to the first low voltage V DGND The second end is connected to the second end of the first MOS transistor M1;

[0053] The control end of the fourth MOS tube M4 is connected to the output end of the first inverter U2, and the first end is connected to the first low voltage V DGND The second end is connected to the second end of the first MOS transistor M1.

[0054] In the first state, the first high voltage V DD The power is not turned off, the input unit 1 works normally, and generates a first signal V inverse to the input signal PWM according to the input signal PWM. A and a second signal V in phase with the input signal PWM B , through the first signal V A and the second signal V B The first MOS transistor M1 or the second MOS transistor M2 is turned on; in the first state, the first high voltage V DD Power is off, and the input unit 1 cannot generate the first signal V according to the input signal PWM A and the second signal V B , and thus the first MOS tube M1 and the second MOS tube M2 cannot be turned on; in this embodiment, the third MOS tube M3 and the fourth MOS tube M4 are both NMOS tubes, the control end is the gate, the first end is the source, and the second end is the drain.

[0055] In one embodiment, the conversion unit 3 includes a first voltage stabilizing diode D1, a second voltage stabilizing diode D2, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein:

[0056] The first terminal of the first voltage stabilizing diode D1 is connected to the second high voltage V PVCC The second end is connected to the driving node;

[0057] The first end of the second voltage stabilizing diode D2 is connected to the second high voltage V PVCC connected;

[0058] The control end of the fifth MOS transistor M5 is connected to the second end of the second voltage stabilizing diode D2, and the first end is connected to the driving voltage V DRIVE The second end is connected to the driving node;

[0059] The control terminal of the sixth MOS transistor M6 is connected to the driving node, and the first terminal is connected to the second high voltage V PVCC The first end is connected to the control end of the fifth MOS transistor M5, and the second end is connected to the control end of the fifth MOS transistor M5.

[0060] The conversion unit 3 operates in the second voltage domain. In the first state, the first MOS transistor M1 is turned on through the third MOS transistor M3 or the second MOS transistor is turned on through the fourth MOS transistor M4, and the normal output driving voltage V DRIVE When the first MOS tube M1 is turned on, the driving voltage V DRIVE is the bias voltage V bais The voltage difference between the control terminal and the first terminal of the second MOS tube M2 is V GS2 The sixth MOS tube M6 is turned on, and the voltages of the control terminal and the first terminal of the fifth MOS tube M5 are both the second high voltage V PVCC At this time, the fifth MOS tube M5 is turned off, and the driving voltage V DRIVE The second low voltage V FLOAT When the second MOS tube M2 is turned on, the voltage at the control end of the fifth MOS tube M5 is the bias voltage V bais The voltage difference between the control terminal and the first terminal of the second MOS tube M2 is V GS2 The sum of the five MOS tubes M5 is turned on, and the driving voltage V DRIVE Pull up to the second high voltage V PVCC , the sixth MOS tube has the second high voltage V because the voltages of the control terminal and the first terminal are both PVCC And disconnected, at this time the driving voltage V DRIVE The second high voltage V PVCC In the second state, the third MOS tube M3 and the fourth MOS tube M4 are both turned off, and the seventh MOS tube M7 is turned on. The seventh MOS tube M7 pulls the voltage of the second end of the first MOS tube M1 down to the first low voltage V DGND , thereby turning on the first MOS tube M1, and then the first MOS tube M1 drives the voltage V DRIVE Clamped to the second low voltage V FLOAT , even if the input unit 1 is high voltage V DD The signal cannot be output when the power is off, and the driving signal V can also be generated in the second voltage domain DRIVE , and the driving signal is low.

[0061] In one embodiment, the fifth MOS transistor M5 and the sixth MOS transistor M6 are PMOS transistors, the control end is the gate, the first end is the source, and the second end is the drain.

[0062] In one embodiment, the output unit 4 includes a third inverter U3 and a fourth inverter U4, wherein:

[0063] The third inverter U3 operates at the second high voltage V PVCC and the second low voltage V FLOAT The input end of the third inverter U3 is connected to the driving node, and the third inverter U3 is used to generate a voltage according to the driving voltage V DRIVE Generate a third signal VC ;

[0064] The fourth inverter U4 input terminal is connected to the output terminal of the third inverter U3, and the fourth inverter U4 is used to generate a voltage according to the third signal V C Generates an output signal LVL_OUT.

[0065] In the first working state, the output signal LVL_OUT is equal to the driving voltage V DRIVE The second high voltage V PVCC Or the second low voltage V FLOAT , and in the second working state, the output signal LVL_OUT is the second low voltage V FLOAT .

[0066] Another aspect of the present invention further provides a chip including the above-mentioned level conversion circuit.

[0067] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0068] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A level conversion circuit for converting an input signal in a first voltage domain into an output signal in a second voltage domain, wherein the first voltage domain ranges from a first high voltage to a first low voltage, and the second voltage domain ranges from a second high voltage to a second low voltage, characterized in that: The level conversion circuit includes: The switch unit includes a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating between a first high voltage and a first low voltage in a first voltage domain, connected to the second end of the first MOS transistor and the second end of the second MOS transistor, respectively, and configured to turn on the first MOS transistor or the second MOS transistor according to an input signal; a conversion unit operating between a second high voltage and a second low voltage in the second voltage domain, connected to the first end of the first MOS transistor and the first end of the second MOS transistor, respectively, and configured to generate a driving voltage at the driving node; an output unit operating between a second high voltage and a second low voltage in the second voltage domain and connected to the driving node, the output unit being configured to generate an output signal according to the driving voltage; The clamping unit is connected between the second end of the first MOS transistor and the second low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage.

2. The level conversion circuit according to claim 1, wherein: The clamping unit includes a seventh MOS transistor, wherein the control end of the seventh MOS transistor is connected to the control signal, the first end is connected to the first low voltage, and the second end is connected to the second end of the first MOS transistor. In the first state, the control signal controls the seventh MOS transistor to be turned off, and in the second state, the control signal controls the seventh MOS transistor to be turned on.

3. The level conversion circuit according to claim 2, wherein: The seventh MOS transistor is an NMOS transistor, the control end is the gate, the first end is the source, and the second end is the drain, wherein: In the first state, the control signal is a low level signal, and in the second state, the control signal is a high level signal.

4. The level conversion circuit according to claim 1, wherein: The input unit includes a first inverter, a second inverter, a third MOS transistor and a fourth MOS transistor, wherein: The first inverter and the second inverter respectively operate between a first high voltage and a first low voltage of the first voltage domain, an input terminal of the first inverter receives an input signal, and an input terminal of the second inverter is connected to an output terminal of the first inverter; The control end of the third MOS transistor is connected to the output end of the first inverter, the first end is connected to the first low voltage, and the second end is connected to the second end of the first MOS transistor; The control end of the fourth MOS transistor is connected to the output end of the second inverter, the first end is connected to the first low voltage, and the second end is connected to the second end of the second MOS transistor.

5. The level conversion circuit according to claim 1, wherein: The conversion unit includes a first voltage stabilizing diode, a second voltage stabilizing diode, a fifth MOS transistor and a sixth MOS transistor, wherein: The first terminal of the first voltage stabilizing diode is connected to the second high voltage, and the second terminal is connected to the driving node; The first end of the second voltage stabilizing diode is connected to a second high voltage; The control end of the fifth MOS transistor is connected to the second end of the second voltage stabilizing diode, the first end is connected to the second high voltage, and the second end is connected to the driving node; The control end of the sixth MOS transistor is connected to the driving node, the first end is connected to the second high voltage, and the second end is connected to the control end of the fifth MOS transistor.

6. The level conversion circuit according to claim 1, wherein: The output unit includes a third inverter and a fourth inverter, wherein: The third inverter and the fourth inverter respectively operate between the second high voltage and the second low voltage of the second voltage domain, the input end of the third inverter is connected to the driving node, the input end of the fourth inverter is connected to the output end of the third inverter, and the output end of the fourth inverter outputs the output signal.

7. The level conversion circuit according to claim 1, wherein: The bias voltage satisfies: Vbais=VS1-VGS1=VFLOAT-VGS1, wherein Vbais is the bias voltage, VS1 is the voltage of the first end of the first MOS tube, VGS1 is the voltage difference between the control end and the first end of the first MOS tube, and VFLOAT is the second low voltage.

8. The level conversion circuit according to claim 7, wherein: The second high voltage, the driving voltage and the second low voltage satisfy the following relationship: VDRIVE=VPVCC-VFLOAT, wherein VDRIVE is the driving voltage, VPVCC is the second high voltage, and VFLOAT is the second low voltage.

9. The level conversion circuit according to claim 8, wherein: In the second state, the driving voltage and the second low voltage satisfy: VDRIVE=VS1=VFLOAT.

10. A chip, characterized in that: The chip includes the level conversion circuit according to any one of claims 1 to 9.

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