Page buffer, semiconductor device including same, and method of operating semiconductor device

Abstract

The invention relates to a page buffer, a semiconductor device including the same, and an operation method of the semiconductor device. The semiconductor device includes memory cells connected to word lines and bit lines. The semiconductor device also includes a line driving circuit configured to apply a program voltage to the word line. The semiconductor device further includes a page buffer including a plurality of latches including at least one dynamic latch and at least one static latch, and configured to control a voltage level of the bit line after the program operation starts. The semiconductor device additionally includes a control circuit configured to control the page buffer to program data already stored in the static latch into the memory cell or store data in the dynamic latch based on a temperature of the semiconductor device when a pause command is received during a program operation.

Description

Technical Field

[0001] Embodiments relate to integrated circuit technology, and more particularly, to a page buffer, a semiconductor device including the page buffer, and an operating method of the semiconductor device. Background Art

[0002] As electronic devices are reduced in size, have low power consumption and high performance, and are diversified, various electronic devices such as computers and portable communication devices require semiconductor devices that can store information. Semiconductor devices can be basically classified as volatile memory devices or non-volatile memory devices. Volatile memory devices have a fast data processing speed, but have a disadvantage in that the volatile memory device needs to be continuously supplied with power to maintain the data already stored in the volatile memory device. Non-volatile memory devices do not need to be continuously supplied with power to maintain the data already stored in the non-volatile memory device, but have a disadvantage in that the non-volatile memory device has a slower data processing speed.

[0003] Research on nonvolatile memory devices continues for increasing data storage capacity by increasing area efficiency and ensuring reliability of programming operations. Summary of the invention

[0004] In one embodiment, a semiconductor device may include: a memory cell connected to a word line and a bit line; a line driving circuit configured to apply a programming voltage to the word line; a page buffer including a plurality of latches including at least one dynamic latch and at least one static latch, and configured to control a voltage level of the bit line after a programming operation starts; and a control circuit configured to control the page buffer to program data already stored in the static latch into the memory cell or to store the data in the dynamic latch based on the temperature of the semiconductor device when a pause command is received during the programming operation.

[0005] In one embodiment, a page buffer may include a switch circuit that is controlled to connect or disconnect a bit line and a common node in response to a page buffer selection signal. The page buffer may also include at least one static latch and at least one dynamic latch that are connected to the common node and are each configured to store data corresponding to a voltage level of the common node or form the voltage level of the common node to a voltage level corresponding to data already stored in the static latch and the dynamic latch in response to a latch control signal. The data already stored in the static latch is programmed into the memory cell through the bit line or moved to the dynamic latch based on the temperature of the semiconductor device.

[0006] In one embodiment, a method for operating a semiconductor device may include the following steps: determining whether a programming operation has been completed; checking whether a pause command has been received while the programming operation has not been completed; when the pause command is received, controlling a page buffer so that data already stored in a latch of the page buffer is moved; and when a resume command is received, controlling the page buffer so that the moved data is returned. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure.

[0008] Figure 2 is a diagram illustrating a configuration of a page buffer included in a semiconductor device according to one embodiment of the present disclosure.

[0009] Figures 3 to 6 is a diagram for describing an operation of a page buffer included in a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 7 and Figure 8 is a flowchart for describing an operating method of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0012] Some embodiments of the present disclosure relate to a semiconductor device capable of performing a program suspend operation by using a page buffer including a dynamic latch and an operating method of the semiconductor device.

[0013] Area efficiency can be improved, and reliability of programming operations can also be improved.

[0014] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure.

[0015] Reference Figure 1 , a semiconductor device 100 according to one embodiment of the present disclosure may include a control circuit 110 , a line driving circuit 120 , a page buffer group 130 , and a cell string group 140 .

[0016] The control circuit 110 may program data into the cell string group 140 or erase data programmed into the cell string group 140 by controlling the line driving circuit 120 , the page buffer group 130 , and the cell string group 140 .

[0017] The line driving circuit 120 may drive the drain selection line DSL, the word lines WL0 to WLn-1, and the source selection line SSL to internal voltage levels, respectively, under the control of the control circuit 110. After the program operation starts, the line driving circuit 120 may apply a program voltage to at least one of the word lines WL0 to WLn-1 as an internal voltage under the control of the control circuit 110.

[0018] The page buffer group 130 may include a plurality of page buffers PB (130_0 to 130_m-1). The plurality of page buffers 130_0 to 130_m-1 may be connected to a plurality of bit lines BL0 to BLm-1, respectively, under the control of the control circuit 110. When the plurality of page buffers 130_0 to 130_m-1 are connected to the bit lines BL0 to BLm-1, respectively, under the control of the control circuit 110, the plurality of page buffers 130_0 to 130_m-1 may apply voltage levels corresponding to data already stored in the plurality of page buffers 130_0 to 130_m-1, respectively, to the bit lines BL0 to BLm-1. In addition, under the control of the control circuit 110, each of the plurality of page buffers 130_0 to 130_m-1 may sense data programmed into a memory cell through each of the bit lines BL0 to BLm-1 already connected to the plurality of page buffers 130_0 to 130_m-1.

[0019] The cell string group 140 may include a plurality of cell strings St_0 to St_m-1. The plurality of cell strings St_0 to St_m-1 may be connected between corresponding bit lines BL0 to BLm-1 and a source line CSL. Each of the plurality of cell strings St_0 to St_m-1 may include a drain select transistor DST, a plurality of cell transistors MC0 to MCn-1, and a source select transistor SST. In this case, the components of the plurality of cell strings St_0 to St_m-1 are the same except that the names of the signals input to the components or the lines connected to the components are different. Therefore, the components of the cell string St_0 among the plurality of cell strings St_0 to St_m-1 may be described as representative.

[0020] The cell string St_0 may include a drain select transistor DST, a plurality of cell transistors MC0 to MCn-1, and a source select transistor SST connected in series between a bit line BL0 and a source line CSL.

[0021] The drain select transistor DST may include a gate connected to the drain select line DSL, and a drain and a source connected to the bit line BL0 and the cell transistor MCn- 1 , respectively.

[0022] A plurality of cell transistors MC0 to MCn-1 may be connected in series between a drain select transistor DST and a source select transistor SST. A plurality of word lines WL0 to WLn-1 may be connected to the gates of the plurality of cell transistors MC0 to MCn-1, respectively. In this case, each of the plurality of cell transistors MC0 to MCn-1 may serve as a memory cell for storing data. Hereinafter, each of the plurality of cell transistors MC0 to MCn-1 may be named a memory cell.

[0023] The source select transistor SST may include a gate connected to a source select line SSL, and a drain and a source connected to the cell transistor MC0 and a source line CSL, respectively.

[0024] The semiconductor device 100 constructed as described above according to one embodiment of the present disclosure may, when receiving a suspend command during a program operation, program some of the data already stored in the page buffer into the memory cell or periodically refresh the page buffer based on the temperature of the semiconductor device 100. Thereafter, when receiving a program resume command, the semiconductor device 100 may return the data programmed into the memory cell when the suspend command was received to the page buffer or terminate the refresh operation, and may subsequently perform the suspended program operation.

[0025] Figure 2 is a diagram illustrating a configuration of a page buffer included in a semiconductor device according to an embodiment of the present disclosure. Except that the names of signals input to the components or lines connected to the components are different, Figure 1 The plurality of page buffers 130_0 to 130_m-1 shown in FIG. 1 may have the same internal components. Therefore, the description of the components of each of the plurality of page buffers 130_0 to 130_m-1 may be used. Figure 2 The components of the page buffer PB shown in are replaced.

[0026] Reference Figure 2 , the page buffer PB may include a plurality of latches 11 , 12 , 13 , 14 , 15 , and 21 and a switch circuit 31 .

[0027] A plurality of latches 11, 12, 13, 14, 15 and 21 may be connected to a common node Node_so in common. Each of the plurality of latches 11, 12, 13, 14, 15 and 21 may form the voltage level of the common node Node_so to a voltage level corresponding to the data already stored in each latch or store data corresponding to the voltage level of the common node Node_so in response to a latch control signal L_ctrl provided by the control circuit 110. That is, each of the plurality of latches 11, 12, 13, 14, 15 and 21 may output the data already stored in each latch to the common node Node_so in response to the latch control signal L_ctrl or may receive and store the data of the common node Node_so. In this case, at least one latch (e.g., latch 21) among the plurality of latches 11, 12, 13, 14, 15 and 21 may be a dynamic latch, and the remaining latches may be static latches. The dynamic latch may have fewer transistors than the static latch, and a refresh operation may be required to maintain data already stored in the dynamic latch. The page buffer PB may include at least one dynamic latch to improve the area efficiency of the page buffer PB, and a refresh operation may be performed to maintain data already stored in the dynamic latch. In one embodiment of the present disclosure, only a semiconductor device including a page buffer having one dynamic latch is described, but the present disclosure is not limited to this example.

[0028] The plurality of latches 11, 12, 13, 14, 15, and 21 may include first to fifth static latches (11, 12, 13, 14, and 15) and a dynamic latch 21. In addition to the operation of storing data in response to the latch control signal L_ctrl, the first static latch 11 at a position closest to the bit line BL may also perform the following operations: applying a voltage corresponding to the data already stored in the first static latch 11 to the bit line BL or sensing a voltage level of the bit line BL.

[0029] In addition, the fifth static latch 15 at the farthest position from the bit line BL can perform the following operations: store data sent from outside the page buffer PB and send the stored data to other latches 11, 12, 13, 14 and 21, or receive data already stored in other latches 11, 12, 13, 14 and 21 and output the received data to the outside of the page buffer PB.

[0030] The switch circuit 31 can electrically connect or disconnect the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel provided by the control circuit 110. For example, when the page buffer selection signal PB Sel is enabled, the switch circuit 31 can electrically connect the bit line BL and the common node Node_so. In addition, when the page buffer selection signal PB Sel is disabled, the switch circuit 31 can electrically separate the bit line BL and the common node Node_so.

[0031] The switch circuit 31 may include a transistor N having a gate to which the page buffer selection signal PB Sel is input, and a drain and a source connected to the bit line BL and the common node Node_so, respectively.

[0032] Figures 3 to 6 is a diagram for describing an operation of a page buffer included in a semiconductor device according to one embodiment of the present disclosure.

[0033] Figure 3 is a diagram for describing data movement and a program operation between static latches included in a page buffer PB. Figure 3 An operation of storing the data already stored in the third static latch 13 in the first static latch 11 is illustrated only as an example to describe the data movement between the static latches, but the present disclosure is not limited to this example.

[0034] Reference Figure 3, in response to the latch control signal L_ctrl, the third static latch 13 may form the voltage level of the common node Node_so to a voltage level corresponding to the data already stored in the third static latch 13. That is, as shown in the direction of the first arrow 1, the third static latch 13 may send the data already stored in the third static latch 13 to the common node Node_so. The first static latch 11 may store data corresponding to the voltage level of the common node Node_so in response to the latch control signal L_ctrl. That is, as shown in the direction of the second arrow 2, the first static latch 11 may receive and store the data of the third static latch 13 sent through the common node Node_so. Thereafter, when the switch circuit 31 connects the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel, the first static latch 11 may provide a voltage corresponding to the data already stored in the first static latch 11 to the bit line BL via the common node Node_so and the switch circuit 31 in response to the latch control signal L_ctrl. That is, as shown in the direction of the third arrow 3, the first static latch 11 can provide a voltage corresponding to the stored data to the bit line BL. In this case, the voltage provided by the first static latch 11 can be transmitted to the memory cell MC through the bit line BL. Data corresponding to the voltage level of the bit line BL can be programmed into the memory cell MC.

[0035] Figure 4 is a diagram for describing data movement and read operations between static latches included in the page buffer PB. Figure 4 Only an operation of storing data already stored in the first static latch 11 in the third static latch 13 is illustrated as an example to describe data movement between static latches, but the present disclosure is not limited to this example.

[0036] Reference Figure 4, the switch circuit 31 may connect the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel. When the bit line BL and the common node Node_so are connected by the switch circuit 31, the first static latch 11 may sense and store the data that has been programmed into the memory cell MC in response to the latch control signal L_ctrl. That is, as shown in the direction of the first arrow 1, the data that has been programmed into the memory cell MC may be sensed and stored in the first static latch 11. Thereafter, the switch circuit 31 may separate the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel. The first static latch 11 may form the voltage level of the common node Node_so to a voltage level corresponding to the data that has been stored in the first static latch 11 in response to the latch control signal L_ctrl. That is, as shown in the direction of the second arrow 2, the first static latch 11 may send the data that has been stored in the first static latch 11 to the common node Node_so. The third static latch 13 can store data corresponding to the voltage level of the common node Node_so in response to the latch control signal L_ctrl. That is, as shown in the direction of the third arrow 3, the third static latch 13 can receive and store the data sent by the first static latch 11 through the common node Node_so. As in the data movement operation between the first static latch 11 and the third static latch 13, after the read operation starts, the data of the third static latch 13 can be moved to the fifth static latch 15. The fifth static latch 15 can output the data stored in the fifth static latch 15 to the outside of the page buffer PB.

[0037] Figure 5 is a diagram for describing data movement and a program operation between a static latch and a dynamic latch included in a page buffer PB. Figure 5 Only an operation of storing the data stored in the dynamic latch 21 in the first static latch 11 is illustrated as an example to describe data movement between the static latch and the dynamic latch, but the present disclosure is not limited to this example.

[0038] Reference Figure 5, the dynamic latch 21 may form the voltage level of the common node Node_so to a voltage level corresponding to the data already stored in the dynamic latch 21 in response to the latch control signal L_ctrl. That is, as shown in the direction of the first arrow 1, the dynamic latch 21 may send the data already stored in the dynamic latch 21 to the common node Node_so. The first static latch 11 may store data corresponding to the voltage level of the common node Node_so in response to the latch control signal L_ctrl. That is, as shown in the direction of the second arrow 2, the first static latch 11 may receive and store the data sent by the dynamic latch 21 through the common node Node_so. Thereafter, when the switch circuit 31 connects the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel, the first static latch 11 may provide a voltage corresponding to the data already stored in the first static latch 11 to the bit line BL via the common node Node_so and the switch circuit 31 in response to the latch control signal L_ctrl. That is, as shown in the direction of the third arrow 3, the first static latch 11 can provide a voltage corresponding to the stored data to the bit line BL. In this case, the voltage provided by the first static latch 11 can be transmitted to the memory cell MC through the bit line BL. Data corresponding to the voltage level of the bit line BL can be programmed into the memory cell MC.

[0039] Figure 6 is a diagram for describing data movement and read operations between a dynamic latch and a static latch included in a page buffer PB. Figure 6 Only an operation of storing data already stored in the first static latch 11 in the dynamic latch 21 is illustrated as an example to describe data movement between the dynamic latch and the static latch, but the present disclosure is not limited to this example.

[0040] Reference Figure 6, the switch circuit 31 may connect the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel. When the bit line BL and the common node Node_so are connected by the switch circuit 31, the first static latch 11 may sense and store the data that has been programmed into the memory cell MC in response to the latch control signal L_ctrl. That is, as shown in the direction of the first arrow 1, the data that has been programmed into the memory cell MC may be sensed and stored in the first static latch 11. Thereafter, the switch circuit 31 may separate the bit line BL and the common node Node_so in response to the page buffer selection signal PB Sel. The first static latch 11 may form the voltage level of the common node Node_so to a voltage level corresponding to the stored data in response to the latch control signal L_ctrl. That is, as shown in the direction of the second arrow 2, the first static latch 11 may send the stored data to the common node Node_so. The dynamic latch 21 may store data corresponding to the voltage level of the common node Node_so in response to the latch control signal L_ctrl. That is, as shown in the direction of the third arrow 3, the dynamic latch 21 can receive and store the data transmitted through the common node Node_so of the first static latch 11. Similar to the data movement operation between the first static latch 11 and the dynamic latch 21, after the read operation starts, the data of the dynamic latch 21 can be moved to the fifth static latch 15. The fifth static latch 15 can output the data stored in the fifth static latch 15 to the outside of the page buffer PB.

[0041] As described above, data movement between the plurality of latches 11, 12, 13, 14, 15, and 21 included in the page buffer PB can be performed through the intermediary of the common node Node_so, regardless of the type of latch (i.e., static or dynamic). It has been described that data movement between latches is performed during programming and reading operations as an example. However, even during another operation other than programming and reading operations, data movement through the common node Node_so between latches can be performed.

[0042] Figure 7 and Figure 8 is a flowchart for describing an operating method of a semiconductor device according to an embodiment of the present disclosure.

[0043] Reference Figure 7According to an embodiment of the present disclosure, an operating method of a semiconductor device may include a programming operation step S10, a programming completion determination step S20, a pause command reception check step S30, a latch data movement step S40, another operation execution step S50, a resume command reception check step S60, and a latch data return step S70.

[0044] The program operation step S10 may include the steps of receiving a program command and providing a program pulse to the memory cell. In this case, a program target level of the memory cell may be adjusted based on data transmitted by the page buffer PB through the bit line BL.

[0045] The program completion determination step S20 may include a step of determining whether a voltage level of a threshold voltage of a memory cell on which a program operation is being performed is greater than a program target level.

[0046] When the voltage level of the threshold voltage of the memory cell being programmed is greater than the program target level, it may be determined that the program operation has been completed (Yes), and the operating method of the semiconductor device according to one embodiment of the present disclosure may be terminated.

[0047] However, when the voltage level of the threshold voltage of the memory cell being programmed is not greater than the program target level in the program completion determination step S20, it may be determined that the program operation has not been completed (No), and the suspend command reception check step S30 may be performed.

[0048] The suspend command reception checking step S30 may include a step of checking whether a program suspend command has been received in a state in which a program operation is being performed.

[0049] When it is checked in the suspend command reception check step S30 that the program suspend command has not been received, the program operation step S10 may be performed. Therefore, in the operating method of the semiconductor device according to one embodiment of the present disclosure, when the reception of the program suspend command is not checked in the suspend command reception check step S30, the program operation step S10 of supplying a program pulse to the memory cell may be repeatedly performed until the programming into the memory cell is completed.

[0050] When it is checked in the suspend command reception checking step S30 that the program suspend command has been received (Yes), the latch data moving step S40 may be performed.

[0051] The latch data moving step S40 may include a step of moving data already stored in a plurality of latches included in the page buffer PB. In this case, the latch data moving step S40 may include a data moving step between static latches and a data moving step from a static latch to a dynamic latch. In addition, the latch data moving step S40 may also include a dynamic latch refresh operation step. For example, if another operation execution step S50 includes performing a read operation, the latch data moving step S40 may include a data moving step between static latches, wherein the data already stored in the first static latch 11 sensing the data programmed into the memory cell MC is moved to one of the other static latches 12, 13, and 14. In this case, the static latch that will store the data of the first static latch 11 may be a latch that has sent data to the memory cell MC (that is, a latch that has stored the programming data). In addition, the latch data moving step S40 may include a step of moving the data of the static latch to the memory cell or the dynamic latch based on the temperature of the semiconductor device and a dynamic latch refresh operation step of refreshing the dynamic latch based on the temperature of the semiconductor device. In this case, the dynamic latch refresh operation step may be a step performed in a state where data has been stored in the dynamic latch. In addition, the refresh cycle of the dynamic latch may be different based on the temperature of the semiconductor device.

[0052] The other operation performing step S50 may include a step of performing an operation other than the program operation in a state where the program operation has been suspended but not completed. For example, the other operation performing step S50 may include a step of performing a read operation.

[0053] The resume command reception check step S60 may include a step of checking whether a resume command indicating that the suspended program operation is executed again has been received. For example, the resume command reception check step S60 may include checking whether a command indicating that the suspended program operation is executed again has been received because the operation of another operation execution step S50 has been completed.

[0054] When reception of the resume command is not checked in the resume command reception checking step S60 (No), it may be determined that the operation performed in the another operation execution step S50 has not been completed, and another operation execution step S50 may be performed.

[0055] When the reception of the resume command is checked in the resume command reception checking step S60 (YES), the latch data return step S70 may be performed.

[0056] The latch data return step S70 may include the step of storing the data that has been moved in the latch data movement step S40 in the latch before the data is moved. If the data of the first static latch 11 has been moved to the second static latch 12 in the latch data movement step S40, the latch data return step S70 may include the step of moving the data of the second static latch 12 to the first static latch 11. In addition, if the data of the first static latch 11 has been moved to the memory cell MC in the latch data movement step S40, the latch data return step S70 may include the step of moving the data of the memory cell MC to the first static latch 11. In this case, a detailed description of the data movement operation between the plurality of latches included in the page buffer PB and the operation of programming the data of the dynamic latch 21 into the memory cell may be described with reference to Figures 3 to 6 When the latch data return step S70 is completed, the program operation S10 that has been suspended in response to the suspend command may be resumed.

[0057] Figure 8 is used to describe more specifically Figure 7 Flowchart of latch data moving step S40 in FIG.

[0058] Reference Figure 8 According to an embodiment of the present disclosure, an operating method of a semiconductor device may include a temperature checking step S41, a first selection step S42, a memory cell programming step S43, a step of moving data to a dynamic latch S44, a second selection step S45, a first cycle refresh step S46, and a second cycle refresh step S47.

[0059] The temperature checking step S41 may include a step of checking the temperature of the semiconductor device.

[0060] The first selection step S42 may include a step of selecting a step S43 of moving the data of the static latch to the memory cell or a step S44 of moving the data of the static latch to the dynamic latch based on the temperature of the semiconductor device. For example, when it is determined in the first selection step S42 that the temperature is a high temperature, the step S43 of programming the data of the static latch into the memory cell may be performed. When it is determined in the first selection step S42 that the temperature is not a high temperature, the step S44 of moving the data of the static latch to the dynamic latch may be performed. More specifically, for example, when the temperature is higher than a reference temperature of 60 degrees in the first selection step S42, it may be determined that the temperature is a high temperature (yes), and the memory cell programming step S43 may be performed. When the temperature is equal to or lower than the reference temperature of 60 degrees in the first selection step S42, it may be determined that the temperature is not a high temperature (no), and the step S44 of moving the data to the dynamic latch may be performed.

[0061] The memory cell programming step S43 may include a step of programming the data already stored in the static latch into the memory cell MC. For example, the memory cell programming step S43 may include a step of transmitting the data already stored in the first static latch 11 to the memory cell MC.

[0062] The step S44 of moving data to the dynamic latch may include the step of storing the data already stored in the static latch in the dynamic latch. In this case, the dynamic latch may maintain the data already stored in the dynamic latch through a refresh operation.

[0063] The second selection step S45 may be a step performed to maintain data in the dynamic latch, and may include a step of selecting a refresh cycle of the dynamic latch based on the temperature of the semiconductor device.

[0064] When the temperature is determined to be the medium temperature in the second selection step S45, that is, when the temperature is determined to be higher than the reference temperature of 25 degrees (Yes), the first cycle refresh step S46 of refreshing the dynamic latch 21 every first cycle may be performed.

[0065] When the temperature is determined to be low in the second selection step S45, that is, when the temperature is determined to be equal to or lower than the reference temperature of 25 degrees (No), a second cycle refresh step S47 of refreshing the dynamic latch 21 every second cycle may be performed.

[0066] The first cycle refresh step S46 may include a step of refreshing the dynamic latch 21 every first cycle shorter than the second cycle.

[0067] The second cycle refresh step S47 may include a step of refreshing the dynamic latch 21 every second cycle which is longer than the first cycle.

[0068] As the temperature of the semiconductor device becomes higher, the dynamic latch may require a refresh operation with a short period to maintain data already stored in the dynamic latch.

[0069] As described above, if the data already stored in the page buffer needs to be maintained until the resume command is received after receiving the suspend command in the programming operation state, the semiconductor device according to one embodiment of the present disclosure can maintain the data of the static latch before receiving the suspend command by storing the data of the static latch in the memory cell or the dynamic latch based on the temperature of the semiconductor device and performing a refresh operation on the dynamic latch. Therefore, when the programming operation that has been suspended is performed again in response to the reception of the resume command, the programming operation can be performed subsequently.

[0070] Therefore, the semiconductor device according to one embodiment of the present disclosure can improve the stability of the program operation since the program operation can be stably performed although the program operation is suspended and then resumed, thereby improving the area efficiency of the page buffer.

[0071] Although the embodiments according to the technical spirit of the present disclosure have been described above with reference to the accompanying drawings, the embodiments have been provided to describe only the embodiments according to the concept of the present disclosure, and the present disclosure is not limited by the embodiments. A person of ordinary skill in the art to which the present disclosure belongs can replace, modify and change the embodiments in various ways without departing from the technical spirit of the present disclosure written in the claims. It can be said that such replacement, modification and change belong to the scope of the present disclosure.

[0072] CROSS-REFERENCE TO RELATED APPLICATIONS

[0073] This application claims priority to Korean Patent Application No. 10-2023-0077987, filed on Jun. 19, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a memory cell connected to a word line and a bit line; a line driving circuit that applies a programming voltage to the word line; a page buffer including a plurality of latches including at least one dynamic latch and at least one static latch and controlling a voltage level of the bit line after a program operation starts; as well as A control circuit controls the page buffer to program the data already stored in the static latch into the memory cell or to store the data in the dynamic latch based on the temperature of the semiconductor device when a pause command is received during the program operation.

2. The semiconductor device according to claim 1, wherein The control circuit: When the suspend command is received, controlling the page buffer to program the data already stored in the static latch into the memory cell when the temperature is higher than a specific temperature, storing the data already stored in the static latch in the dynamic latch when the temperature is equal to or lower than the specific temperature, and A refresh operation of the dynamic latch is controlled so that the data already stored in the dynamic latch is maintained.

3. The semiconductor device according to claim 2, wherein: The control circuit controls the dynamic latch to perform the refresh operation having a long period as the temperature becomes lower when the temperature is equal to or lower than the specific temperature.

4. The semiconductor device according to claim 1, wherein The control circuit controls the page buffer to store the data, which has been programmed into the memory cell, in the static latch when receiving a resume command instructing to perform the program operation again.

5. A method for operating a semiconductor device, the method comprising the following steps: Determining whether the programming operation has been completed; checking whether a pause command is received when the programming operation is not completed; When the suspend command is received, controlling the page buffer so that data already stored in the latch of the page buffer is moved; as well as When a restore command is received, the page buffer is controlled so that the moved data is returned.

6. The operating method according to claim 5, wherein: The latch of the page buffer includes at least one dynamic latch and at least one static latch, and The step of controlling the page buffer so that the data is moved includes programming the data already stored in the static latch into a memory cell when the temperature of the semiconductor device is higher than a reference temperature.

7. The operating method according to claim 6, wherein: The step of controlling the page buffer so that the moved data is returned includes controlling the page buffer so that the data programmed into the memory cell is stored in the static latch.

8. The operating method according to claim 6, further comprising the following steps: When the temperature is equal to or lower than the reference temperature, moving the data already stored in the static latch to the dynamic latch; as well as The dynamic latch is controlled to perform a refresh operation.

9. The operating method according to claim 8, wherein: The step of controlling the dynamic latch to perform the refresh operation includes controlling the dynamic latch to perform the refresh operation having a long period as the temperature becomes lower.

10. A page buffer, comprising: a switch circuit controlled to connect or disconnect the bit line and the common node in response to a page buffer selection signal; as well as at least one static latch and at least one dynamic latch, the at least one static latch and the at least one dynamic latch being connected to the common node and each storing data corresponding to a voltage level of the common node or forming the voltage level of the common node to a voltage level corresponding to data already stored in the static latch and the dynamic latch in response to a latch control signal, The data stored in the static latch is programmed into a memory cell through the bit line or moved to the dynamic latch based on the temperature of the semiconductor device.

11. The page buffer according to claim 10, wherein: The static latch programs the stored data into the memory cell when the temperature is higher than a reference temperature, or moves the stored data to the dynamic latch when the temperature is equal to or lower than the reference temperature, under the control of a control circuit.

12. The page buffer according to claim 11, wherein: The dynamic latch performs a refresh operation having a long period as the temperature becomes lower under the control of the control circuit when the temperature is equal to or lower than the reference temperature.

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