Memory device allowing rewrite program operation and method of operating same

Abstract

The invention relates to a memory device allowing a rewrite program operation and an operating method thereof. The memory device includes: a memory cell array including memory cells coupled between a word line and a plurality of bit lines; and a control unit suitable for performing a program operation on the memory cell according to an incremental step pulse programming (ISPP) method until the program operation is successfully performed, the program operation repeating a program loop including a voltage application operation and a verify operation, the control unit repeatedly performs a program loop by setting a voltage level of an initial program pulse to be applied to a word line in a voltage application operation included in the initial program loop among the repeated program loops to one of a first level and a second level according to whether a program operation is a rewrite operation, and wherein the second level is lower than the first level by the first set level.

Description

Technical Field

[0001] Various embodiments of the present invention relate to a memory device, and more particularly, to a memory device that allows a rewrite operation and a method for operating the memory device. Background Art

[0002] A memory system is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory systems are classified into volatile memory devices and non-volatile memory devices. A volatile memory device is a memory device in which the data stored therein is lost when the power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device in which the data stored therein is retained even when the power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is mainly classified into NOR type memory and NAND type memory.

[0003] A cell of a nonvolatile memory device is an element on which electrical program / erase operations can be performed. A nonvolatile memory device can perform program and erase operations on a cell by changing a threshold voltage of the cell as electrons move by a strong electric field applied to a thin oxide film of the cell.

[0004] Herein, a programming operation may include a normal programming operation that moves a voltage level of a nonvolatile memory cell having a threshold voltage level of an erased state to one of a plurality of threshold voltage levels, and an overwrite operation that performs a programming operation again on a nonvolatile memory cell whose reliability is expected to be degraded due to failure of a normal programming operation to be normally completed or a nonvolatile memory cell whose reliability is expected to be degraded due to degradation of retention characteristics caused by a sudden power off (SPO) even if the normal programming operation is completed. Summary of the invention

[0005] Embodiments of the present invention are directed to a memory device capable of minimizing distribution degradation of program target memory cells during a rewrite operation and a method of operating the memory device.

[0006] The technical problems to be solved in the embodiments of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned above can also be clearly understood by ordinary technicians in the field to which the present invention belongs from the following description.

[0007] According to one embodiment of the present invention, a memory device may include: a memory cell array including memory cells connected between a word line and a plurality of bit lines; and a control unit adapted to perform a programming operation on the memory cell according to an incremental step pulse programming (ISPP) method until the programming operation is successfully performed, the programming operation repeating a programming loop including a voltage application operation and a verification operation. The control unit may repeatedly perform the programming loop by setting the voltage level of the initial programming pulse to one of a first level and a second level according to whether the programming operation is a rewrite operation. The initial programming pulse may be applied to the word line in a voltage application operation included in an initial programming loop in a repeated programming loop. The second level may be a first setting level lower than the first level.

[0008] According to another embodiment of the present invention, a method for operating a memory device including a memory cell connected between a word line and a plurality of bit lines may include the following steps: performing a programming operation on the memory cell according to an incremental step pulse programming (ISPP) method until the programming operation is successfully performed, the programming operation repeating a programming loop including a voltage application operation and a verification operation; and checking whether the programming operation is a rewrite operation. The repeatedly performed steps may include: setting a voltage level of an initial programming pulse to one of a first level and a second level according to whether the programming operation is a rewrite operation. The initial programming pulse may be a voltage application operation to be included in an initial programming loop in a repeated programming loop to be applied to the word line. The second level may be a first setting level lower than the first level.

[0009] According to another embodiment of the present invention, a method for operating a memory device may include the following steps: according to an incremental step pulse programming (ISPP) scheme, reducing at least one of a voltage level and an increment of a programming pulse in proportion to the number of times a programming operation has succeeded on a memory cell group; and according to the ISPP scheme, performing a programming operation based on the reduced voltage level and increment. During at least an initial programming loop and subsequent programming loops within the programming operation, the programming pulse may be provided to the memory cell group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a memory device according to one embodiment of the present invention.

[0011] Figure 2 An example of an embodiment of the present invention is shown in Figure 11 and 2. A normal programming operation performed according to an incremental step pulse programming (ISPP) method in the memory device shown in FIG.

[0012] Figure 3A and Figure 3B An example of an embodiment of the present invention is shown in Figure 1 0048. The rewrite operation performed in the memory device shown in FIG.

[0013] FIG. 4A to FIG. 4C An example of an embodiment of the present invention is shown in Figure 1 Another rewrite operation performed in the memory device shown in FIG.

[0014] Figure 5 This is an example of an embodiment according to the present invention. Figure 1 0 is a block diagram of a control unit among the constituent elements of a memory device shown in FIG.

[0015] Figure 6 The invention is described in one embodiment according to the present invention. Figure 1 A flowchart showing the sequence of programming operations performed in a memory device is shown in FIG.

[0016] Figure 7 is a graph illustrating distribution of memory cells according to a program operation. DETAILED DESCRIPTION

[0017] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0018] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to mean any such features included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0019] In this disclosure, the terms "comprises," "comprising," "having," and "containing" are open ended. As used in the appended claims, these terms specify the presence of the recited elements and do not preclude the presence or addition of one or more other elements. These terms in the claims do not preclude the device from including additional components (e.g., interface units, circuits, etc.).

[0020] In the present disclosure, various units, circuits or other components may be described or stated as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when a specified block / unit / circuit / component is currently inoperable (e.g., neither turned on nor activated), the block / unit / circuit / component may be referred to as being configured to perform a task. Blocks / units / circuit / components used with the "configured to" language include hardware, such as circuits, memories storing executable programming instructions to implement operations, and the like. In addition, "configured to" may include a general structure (e.g., a general circuit) that is manipulated by software and / or firmware (e.g., an FPGA or a general processor executing software) to operate in a manner capable of performing the tasks to be processed. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) that implements or performs one or more tasks.

[0021] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) hardware circuit implementations only (e.g., implementations only in analog and / or digital circuits); (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of (multiple) processors, or (ii) (multiple) processors / software (including (multiple) digital signal processors), software, and (multiple) memory portions that operate together to enable a device such as a mobile phone or server to perform various functions; and (c) circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware for operation, even if the software or firmware is not physically present. This definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claims). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of only a processor (or multiple processors) or a portion of a processor, and its (or their) accompanying software and / or firmware. The term "circuit" or "logic" also covers (for example, and if applicable to a particular claim element) an integrated circuit for a storage device.

[0022] As used herein, the terms "first", "second", "third", etc. are used as labels for nouns preceding the terms, and do not imply any type of ordering (e.g., spatially, temporally, logically, etc.). The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. In addition, although various elements may be identified using terms in this article, these elements are not limited by these terms. These terms are used to distinguish an element from another element having the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0023] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude additional factors that may affect the determination. That is, the determination may be based only on those factors or at least in part on those factors. For example, the phrase "A is determined based on B." Although in this case, B is a factor that affects the determination of A, this phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0024] In this article, an item of data, a data item, a data entry or an entry of data can be a bit sequence. For example, a data item can include the content of a file, a part of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a part of a video or audio signal, metadata or any other entry that can be represented by a bit sequence. According to one embodiment, a data item can include a discrete object. According to another embodiment, a data item can include an information unit in a transmission packet between two different components.

[0025] Figure 1 is a block diagram illustrating a memory device according to one embodiment of the present invention.

[0026] Figure 2 An example of an embodiment of the present invention is shown in Figure 1 1 and 2. A normal programming operation performed according to an incremental step pulse programming (ISPP) method in the memory device shown in FIG.

[0027] Reference Figure 1 , a memory device 150 according to an embodiment of the present disclosure may include a memory cell array 201 and a control unit 202 .

[0028] The memory cell array 201 may include a plurality of memory blocks (not illustrated). Each memory block may include a plurality of memory cells (not illustrated). One memory block may include a plurality of pages.

[0029] A storage block may be understood as a group of nonvolatile memory cells from which data is removed together by an erase operation. Each of the storage blocks may include a page (not illustrated) in which nonvolatile memory cells are grouped from a logical perspective (such as storing data together during a programming operation or outputting data together during a read operation). For example, a storage block may include multiple pages. A page may include multiple nonvolatile memory cells.

[0030] From a physical perspective different from a logical perspective such as a program operation or a read operation, one memory block may include a plurality of word lines (WL<1:n>). One word line may include a plurality of nonvolatile memory cells.

[0031] In this case, according to the number of bits that can be stored or expressed in one nonvolatile memory cell, one word line can correspond to at least one page. For example, when a nonvolatile memory cell is a single-level cell (SLC) storing one data bit, one word line can correspond to one page. When a nonvolatile memory cell is a dual-level cell (DLC) storing two data bits, one word line can correspond to two pages. When a nonvolatile memory cell is a triple-level cell (TLC) storing three data bits, one word line can correspond to three pages. When a nonvolatile memory cell is a quad-level cell (QLC) storing four data bits, one word line can correspond to four pages. In this way, when a nonvolatile memory cell is a multi-level cell storing five or more data bits, one word line can correspond to five or more pages.

[0032] The control unit 202 may perform a programming operation on a selected area of ​​the memory cell array 201. The control unit 202 may perform a programming operation on a word line selected as a programming target among a plurality of word lines (hereinafter referred to as a "programming word line") and a selected memory cell connected between a plurality of bit lines (hereinafter referred to as a "programming cell"). That is, the control unit 202 may program the memory cell selected as the programming target so that the memory cell has one of a plurality of programming states.

[0033] In one embodiment, the programming state of a single-level cell (SLC) storing one data bit can be divided into two programming states based on one threshold voltage level. The programming state of a multi-level cell (MLC) storing two data bits can be divided into four programming states based on three threshold voltage levels. The programming state of a triple-level cell (TLC) storing three data bits can be divided into eight programming states based on seven threshold voltage levels. The programming state of a quad-level cell (QLC) storing four data bits can be divided into sixteen programming states based on fifteen threshold voltage levels.

[0034] Reference Figure 1as well as Figure 2 The programming operation may include a plurality of programming loops PL1 to PL7. That is, the control unit 202 may program the memory cell selected as the programming target by repeatedly performing the plurality of programming loops PL1 to PL7 one by one in a set order until the programming operation is completed, so that the memory cell has one of a plurality of programming states (see Figure 1 10). In addition, if the program operation is not successful within a preset number of program loops, the control unit 202 may determine the program operation as a failure.

[0035] Herein, each of the programming loops PL1 to PL7 may include: a voltage application operation VIO, which applies a programming pulse PGM<1:7> to the programming word line to change the threshold voltage level of the programming unit; and a verification operation VER, which verifies what programming state the programming unit is in by applying a verification voltage V<1:3> corresponding to the target level to the programming word line.

[0036] Whenever each of the plurality of programming loops PL1 to PL7 is executed, the potential level of the programming voltage may increase. That is, in the programming operation, as each of the plurality of programming loops PL1 to PL7 is repeatedly executed, the level of the programming voltage may increase according to an incremental step pulse programming (ISPP) method. The number of applications, the voltage level, and the voltage application time of the programming voltage used in each of the plurality of programming loops PL1 to PL7 may be determined in various forms.

[0037] According to one embodiment of the present invention, Figure 2 It is seen that the voltage level of the program pulse PGM1 may be set to the first level D1 in the initial program loop PL1 among the program loops PL1 to PL7 and increases by the third level D3 as each of the program loops PL1 to PL7 is repeated.

[0038] In addition, the memory device 150 according to one embodiment of the present invention may perform a rewrite operation. A program operation in the memory device 150 according to one embodiment of the present invention may be divided into a normal program operation and a rewrite operation.

[0039] Herein, a normal program operation may refer to an operation of storing data in a program memory cell that does not store data. It may refer to an operation of moving a voltage level of a program memory cell having a threshold voltage level of an erased state to one of a plurality of threshold voltage levels.

[0040] Reference Figure 7According to one embodiment of the present invention, a programming cell in an erase state ERASE in which no data is stored may be in a state having a threshold voltage lower than a first verification voltage V1. In this state, when a normal programming operation NORMAL PRORAM for storing 2-bit data in the programming cell is performed, the threshold voltage level of the programming cell may be one of four threshold voltage levels distinguished according to the first to third verification voltages V<1:3>. That is, through the normal programming operation NORMAL PRORAM, the programming cell may have the following states, ERASE, PG1, PG2, and PG3, which have a threshold voltage level lower than the first verification voltage V1, a threshold voltage level equal to or greater than the first verification voltage V1 and lower than the second verification voltage V2, a threshold voltage level equal to or greater than the second verification voltage V2 and lower than the third verification voltage V3, and a threshold voltage level equal to or greater than the third verification voltage V3.

[0041] The rewrite operation may refer to an operation of performing the program operation again on a program cell that has stored data. The retention characteristic of the program cell may be improved by performing the rewrite operation on a program cell having one threshold voltage level among a plurality of threshold voltage levels.

[0042] Specifically, the control unit 202 according to one embodiment of the present invention may set the voltage level of the initial programming pulse PGM1 applied to the programming word line in the voltage application operation VIO included in the initial programming loop PL1 among the programming loops PL1 to PL7 repeated according to the ISPP method for the programming unit to one of the first level D1 and the second level D2, depending on whether the programming operation for the programming unit is a rewrite operation. In this case, the second level D2 may be a level lower than the first level D1 by the first setting level Va.

[0043] In addition, the control unit 202 sets the increment from the voltage level of the initial programming pulse to the voltage level of the second programming pulse to one of the third level D3 and the fourth level D4 according to whether the programming operation for the programming unit is a rewrite operation. The initial programming pulse and the second programming pulse may be applied to the programming word line in the voltage application operation VIO respectively included in the initial programming loop and the second programming loop among the programming loops PL1 to PL7 repeated according to the ISPP method for the programming unit. In this case, the fourth level D4 may be lower than the third level D3 by the second setting level Vb. In addition, the second programming loop may be a programming loop repeated after the initial programming loop. For example, when the initial programming loop is the first programming loop PL1 to be performed, the second programming loop may be the second programming loop PL2 to be performed. For another example, when the initial programming loop is the second programming loop PL2 to be performed, the second programming loop may be the third programming loop PL3 to be performed.

[0044] Specifically, the control unit 202 may check whether the programming operation for the programming unit is a rewrite operation (see Figure 1 20). The control unit 202 may check whether the program operation for the program unit is a rewrite operation based on a program count value (not shown) corresponding to a program address (not shown) input from the outside to control the program operation for the program unit.

[0045] Herein, the control unit 202 may manage a program count value for each of a plurality of pages included in the memory cell array 201. In addition, whenever a program operation for a programming unit is successfully performed, the control unit 202 may increase the program count value. Regardless of whether the program operation for the programming unit is a normal programming operation or a rewrite operation, the control unit 202 may increase the program count value for the programming unit in response to a successful programming operation. In addition, in the case of a page selected as a target of an erase operation, the control unit 202 may initialize a program count value corresponding to the erased page in response to a successful erase operation.

[0046] According to one embodiment, in the case of a programming unit that does not store data, the programming count value may be "0". Since the programming count value is "0", the control unit 202 may perform a normal programming operation as a programming operation for the programming unit. When the normal programming operation for the programming unit is successfully performed, the control unit 202 may increase the programming count value to "1".

[0047] According to another embodiment, in the case of a programming unit storing data, the programming count value may be "1" or greater. Since the programming count value is equal to or greater than "1", the control unit 202 may perform a rewrite operation as a programming operation for the programming unit. When the rewrite operation for the programming unit is successfully performed, the control unit 202 may increase the programming count value to "2" or greater.

[0048] Furthermore, when the program operation for the program unit is not a rewrite operation, the control unit 202 may set the voltage level of the initial program pulse PGM1 applied to the program word line in the voltage applying operation VIO included in the initial program loop PL1 among the program loops PL1 to PL7 repeated according to the ISPP method for the program unit to the first level D1 (see Figure 1 30 in the above).

[0049] Furthermore, when the program operation for the program unit is a rewrite operation, the control unit 202 may set the voltage level of the initial program pulse PGM1 applied to the program word line in the voltage applying operation VIO included in the initial program loop PL1 among the program loops PL1 to PL7 repeated according to the ISPP method for the program unit to the second level D2 (see Figure 1 40 in FIG. 40). In this case, the second level D2 may be a level lower than the first level D1 by the first setting level Va.

[0050] In addition, when the programming operation for the programming unit is a rewrite operation, the control unit 202 may adjust the first setting level Va according to the programming count value corresponding to the programming unit. The control unit 202 may increase the first setting level Va in proportion to the programming count value corresponding to the programming unit. For example, the first setting level Va corresponding to the case where the programming count corresponding to the programming unit is "2" may be greater than the first setting level Va corresponding to the case where the programming count value corresponding to the programming unit is "1".

[0051] When the program operation for the program unit is not a rewrite operation, the control unit 202 may set the increment from the voltage level of the initial program pulse to the voltage level of the second program pulse to the third level D3 (see Figure 1 50). The initial program pulse and the second program pulse may be applied to the program word line in voltage applying operations VIO respectively included in the initial program loop and the second program loop among program loops PL1 to PL7 repeated according to the ISPP method for the program cell.

[0052] When the program operation for the program unit is a rewrite operation, the control unit 202 may set the increment from the voltage level of the initial program pulse to the voltage level of the second program pulse to the fourth level D4 (see Figure 1In this case, the fourth level D4 may be lower than the third level D3 by a second setting level Vb.

[0053] When the programming operation for the programming unit is a rewrite operation, the control unit 202 may adjust the second setting level Vb according to the programming count value corresponding to the programming unit. The control unit 202 may increase the second setting level Vb in proportion to the programming count value corresponding to the programming unit. For example, the second setting level Vb corresponding to the case where the programming count corresponding to the programming unit is "2" may be greater than the second setting level Vb corresponding to the case where the programming count value corresponding to the programming unit is "1".

[0054] In addition, when the programming operation for the programming unit is a rewrite operation, the control unit 202 may switch the blind option to a disabled state (see Figure 1 of 70).

[0055] Then, when the programming operation for the programming unit is successfully performed, the control unit 202 may switch the blind option to an enabled state (see Figure 1 80). Regardless of whether the program operation for the program unit is a normal program operation or a rewrite operation, the control unit 202 may switch the blind option to an enabled state in response to a successful program operation.

[0056] Herein, the blind option may mean an option for minimizing the number of verification voltages used in the verification operation VER of each of the programming loops PL1 to PL7. Since it is difficult to quickly increase the threshold voltage of the programming cell in the initial programming loop among the programming loops PL1 to PL7, it may mean an option of not using a high-level verification voltage in the verification operation VER. When the blind option is enabled, the time required for the verification operation VER in each of the programming loops PL1 to PL7 can be minimized, and thus the time required for the programming operation can be shortened.

[0057] The default state of the blind option may be an enabled state. The default state may be a state in which a normal programming operation is performed when the blind option is enabled. Therefore, since the blind option has been enabled at the moment when the normal programming operation starts, the operation of enabling the blind option in response to a successful programming operation in the control unit 202 (see Figure 1 80) in may be an operation to keep the blind option enabled.

[0058] On the other hand, in the case of a rewrite operation, since the program operation is performed again on a program cell having one of a plurality of threshold voltage levels, the blind option may need to be switched to a disabled state. Furthermore, since the blind option is switched to a disabled state for the rewrite operation, when the rewrite operation is successfully performed, the blind option needs to be switched back to an enabled state. Therefore, the control unit 202 may enable the operation of the blind option in response to a successful program operation (see Figure 1 80) to switch the blind option to an enabled state in response to a successful rewrite operation.

[0059] According to one embodiment, in the above Figure 2 , it can be seen that the blind option is in an enabled state. In the first programming loop PL1 and the second programming loop PL2, the verification operation VER can be performed using only the first verification voltage V1 having the lowest level. In addition, in the third programming loop PL3 and the fourth programming loop PL4, the verification operation VER can be performed using only the first verification voltage and the second verification voltage V<1:2>. In addition, in the fifth programming loop PL5 and the sixth programming loop PL6, the verification operation VER can be performed using only the second verification voltage and the third verification voltage V<2:3>. In addition, in the seventh programming loop PL7, the verification operation VER can be performed using only the third verification voltage V3. In this way, in a state where the blind option is enabled, for each programming loop, the verification operation VER can be performed using only the minimum number of set verification voltages.

[0060] According to one embodiment, it can be seen that the blind option is Figure 3A and Figure 3B as well as FIG. 4A to FIG. 4C is disabled in the , which is described below. Figure 2 By comparing the state where the blind option is enabled as described in FIG. 1 , it can be seen that the number of verification voltages used in the verification operation VER included in each of the program loops PL1 to PL7 increases. Figure 3A and Figure 3B as well as FIG. 4A to FIG. 4C In the first to fourth programming loops PL1 to PL4, the verification operation VER may be performed using the first verification voltage and the second verification voltage V<1:2>. In addition, in the fifth to seventh programming loops PL5 to PL7, the verification operation VER may be performed using the second verification voltage and the third verification voltage V<2:3>. In this way, in a state where the blind option is disabled, the verification operation VER may be performed using at least a minimum number of set verification voltages for each programming loop.

[0061] As described above, the number of verification voltages used in each programming loop when the blind option is disabled can be set to be larger than the number of verification voltages used in each programming loop when the blind option is enabled. Herein, which verification voltage is used in each programming loop when the blind option is enabled and which verification voltage is used in each programming loop when the blind option is disabled can be determined and adjusted by the designer.

[0062] Figure 3A and Figure 3B An example of an embodiment of the present invention is shown in Figure 1 0048. The rewrite operation performed in the memory device shown in FIG.

[0063] Reference Figure 3A as well as Figure 2 , it can be seen that the control unit 202 can set the level of the programming pulse PGM1 included in the initial programming loop PL1 among the programming loops PL1 to PL7 to one of the first level D1 and the second level D2 according to whether the programming operation for the programming unit is a rewrite operation.

[0064] Specifically, in Figure 2 In the example, the control unit 202 may perform a normal programming operation in response to the program count value "0". Therefore, the control unit 202 may set the voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 to the first level D1 in response to the normal programming operation, and as each of the program loops PL1 to PL7 is repeated, the voltage level of the program pulse may increase by the third level D3.

[0065] exist Figure 3A , the control unit 202 may perform a rewrite operation in response to the program count value being equal to or greater than "1" and less than a predetermined number. Therefore, it can be seen that the control unit 202 may set the voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 to the second level D2 which is lower than the first level D1 by the first setting level Va in response to the rewrite operation, and the voltage level of the program pulse increases by the third level D3 as each of the program loops PL1 to PL7 is repeated.

[0066] Reference Figure 3B as well as Figure 3A , it can be seen that even in a state where the programming operation for the programming cell is a rewrite operation, the first setting level Va indicating how much lower the second level D2 is set compared to the first level D1 is adjusted in proportion to the program count value.

[0067] Specifically, it can be seen that Figure 3AIn the embodiment, the control unit 202 performs a rewrite operation in response to the program count value being equal to or greater than "1" and less than a predetermined number, and Figure 3B In the embodiment, a rewrite operation is performed in response to the program count value being equal to or greater than a predetermined number. Figure 3A Compared with the first setting level Va determined in Figure 3B The first setting level Va determined in .

[0068] Therefore, the control unit 202 may respond to Figure 3A The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is set to be higher than that in response to Figure 3B The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is relatively high due to the rewrite operation of the program word line.

[0069] As mentioned above, it can be seen that even if Figure 3A and Figure 3B Both correspond to a rewrite operation, but a voltage level of a program pulse PGM1 applied to a program word line in an initial program loop PL1 among program loops PL1 to PL7 may be differently set according to a program count value.

[0070] In addition, refer to Figure 3B , just like in Figure 3A , it can be seen that as each of the program loops PL1 to PL7 is repeated, the voltage level of the program pulse increases by the third level D3.

[0071] Reference Figure 2 , Figure 3A and Figure 3B It can be seen that although the voltage level of the programming pulse PGM1 applied to the programming word line in the initial programming loop PL1 among the programming loops PL1 to PL7 is set differently, as each of the programming loops PL1 to PL7 is repeated, the operation of increasing the voltage level of the programming pulse by the third level D3 is performed identically.

[0072] FIG. 4A to FIG. 4C An example of an embodiment of the present invention is shown in Figure 1 Another example of a rewrite operation performed in a memory device is shown in FIG.

[0073] Reference Figure 4A as well as Figure 2, it can be seen that the level of the programming pulse PGM1 included in the initial programming loop PL1 among the programming loops PL1 to PL7 is selected as one of the first level D1 and the second level D2 according to whether the programming operation for the programming unit is a rewrite operation. In addition, it can be seen that the control unit 202 can set the increment from the voltage level of the initial programming pulse to the voltage level of the second programming pulse to one of the third level D3 and the fourth level D4 according to whether the programming operation for the programming unit is a rewrite operation. The initial programming pulse and the second programming pulse can be applied to the programming word line in the voltage application operation VIO respectively included in the initial programming loop and the second programming loop among the programming loops PL1 to PL7 repeated according to the ISPP method for the programming unit.

[0074] Specifically, in Figure 2 In the example, the control unit 202 may perform a normal programming operation in response to the program count value "0". Therefore, the control unit 202 may set the voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 to the first level D1 in response to the normal programming operation, and increase the voltage level of the program pulse by the third level D3 as each of the program loops PL1 to PL7 is repeated.

[0075] exist Figure 4A , the control unit 202 may perform a rewrite operation in response to the program count value being equal to or greater than "1" and less than a predetermined number. Therefore, it can be seen that the control unit 202 sets the voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 to the second level D2 which is lower than the first level D1 by the first setting level Va in response to the rewrite operation, and as each of the program loops PL1 to PL7 is repeated, the voltage level of the program pulse increases by the fourth level D4 which is lower than the third level D3 by the second setting level Vb.

[0076] Reference Figure 4B as well as Figure 4A , it can be seen that even in a state where the programming operation for the programming cell is a rewriting operation, the first setting level Va indicating how much smaller the second level D2 is set compared to the first level D1 is adjusted in proportion to the program count value.

[0077] Specifically, it can be seen that Figure 4A In the embodiment, the control unit 202 performs a rewrite operation in response to the program count value being equal to or greater than "1" and less than a predetermined number, and Figure 4B In the embodiment, a rewrite operation is performed in response to the program count value being equal to or greater than a predetermined number. Figure 4ACompared with the first setting level Va determined in Figure 4B The first setting level Va determined in .

[0078] Therefore, the control unit 202 may respond to Figure 4A The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is set to be higher than that in response to Figure 4B The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is relatively high due to the rewrite operation of the program word line.

[0079] As mentioned above, it can be seen that although Figure 4A and Figure 4B Both correspond to a rewrite operation, but a voltage level of a program pulse PGM1 applied to a program word line in an initial program loop PL1 among program loops PL1 to PL7 may be differently set according to a program count value.

[0080] In addition, refer to Figure 4B , just like in Figure 4A , it can be seen that as each of the program loops PL1 to PL7 is repeated, the voltage level of the program pulse increases by the fourth level D4.

[0081] Reference Figure 4A and Figure 4B It can be seen that although the voltage level of the programming pulse PGM1 applied to the programming word line in the initial programming loop PL1 among the programming loops PL1 to PL7 is set differently, as each of the programming loops PL1 to PL7 is repeated, the operation of increasing the voltage level of the programming pulse by the fourth level D4 is performed identically.

[0082] Reference Figure 4C as well as Figure 4A It can be seen that even in a state where the programming operation for the programming unit is a rewrite operation, the first setting level Va indicating how much lower the second level D2 is set compared to the first level D1 and the second setting level Vb indicating how much lower the fourth level D4 is set compared to the third level D3 are adjusted in proportion to the programming count value.

[0083] Specifically, it can be seen that Figure 4A In the embodiment, the control unit 202 performs a rewrite operation in response to the program count value being equal to or greater than "1" and less than a predetermined number, and Figure 4C In the embodiment, a rewrite operation is performed in response to the program count value being equal to or greater than a predetermined number. Figure 4A Compared with the first setting level Va determined in Figure 4C In addition, Figure 4A Compared with the second setting level Vb determined in Figure 4C The second setting level Vb determined in . Herein, the degree to which the first setting level Va increases may be unrelated to the degree to which the second setting level Vb increases. The first setting level Va and the second setting level Vb may increase independently only in proportion to the programming count value without any restriction therebetween.

[0084] Therefore, the control unit 202 may respond to Figure 4A The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is set to be higher than that in response to Figure 4C The voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 is relatively high due to the rewrite operation of the program word line.

[0085] In addition, the control unit 202 may adjust the voltage level of the programming pulse in response to each of the programming loops PL1 to PL7. Figure 4A The fourth level D4 is set to be higher than the voltage level of the programming pulse as each of the programming loops PL1 to PL7 responds to the rewriting operation of Figure 4C The rewriting operation is repeated and the fourth level D4 which increases accordingly is relatively high.

[0086] As mentioned above, it can be seen that although Figure 4A and Figure 4C Both correspond to a rewrite operation, but the voltage level of the program pulse PGM1 applied to the program word line in the initial program loop PL1 among the program loops PL1 to PL7 can be set differently according to the program count value. In addition, it can be seen that although Figure 4A and Figure 4C Both correspond to a rewrite operation, but an increment of a voltage level of a program pulse may be differently set according to a program count value as program loops PL1 to PL7 are performed.

[0087] Figure 5 This is an example of an embodiment according to the present invention. Figure 1 0 is a block diagram of a control unit among the constituent elements of a memory device shown in FIG.

[0088] Reference Figure 5, the memory device 150 may include a memory cell array 201 and a control unit 202. The control unit 202 may include a control circuit unit 309 and a control logic unit 304. The control circuit unit 309 may include a page buffer unit 302, a check unit 303, a data input / output circuit 305, a voltage supply circuit 306, and an address decoder 307. In addition, the control circuit unit 309 may include a count storage unit 311, a program controller 312, and an option controller 313.

[0089] The memory cell array 201 may include a plurality of memory blocks MEMORY BLOCK<1:6>. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the address decoder 307 through row lines RL. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the page buffer unit 302 through bit lines BL1 to BLm. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells.

[0090] The row line RL may include at least one source select line (not illustrated), a plurality of word lines (not illustrated), and at least one drain select line (not illustrated).

[0091] The control circuit unit 309 may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array 201. The control circuit unit 309 may drive the memory cell array 201. For example, the control circuit unit 309 may apply various operation voltages to the row lines RL and the bit lines BL1 to BLm, or discharge the applied voltages. The control circuit unit 309 may perform a program operation on a programming cell in response to the control of the control logic unit 304. In particular, the control circuit unit 309 may perform a rewrite operation as well as a normal program operation on a programming cell in response to the control of the control logic unit 304.

[0092] The address decoder 307 among the control circuit unit 309 may be connected to the memory cell array 201 through the row lines RL.

[0093] The address decoder 307 may be configured to operate in response to the control of the control logic unit 304. The address decoder 307 may receive the address RADD from the control logic unit 304.

[0094] The address decoder 307 may be configured to decode the block address of the received address RADD. The address decoder 307 may select at least one memory block from the memory block MEMORY BLOCK<1:6> according to the decoded block address. The address decoder 307 may be configured to decode the row address of the received address RADD. The address decoder 307 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 307 may apply the operating voltage Vop supplied from the voltage supply circuit 306 to the selected word line.

[0095] The voltage supply circuit 306 , which may be included in the control circuit unit 309 , may be configured to generate a plurality of operation voltages Vop by using an external power supply voltage. The voltage supply circuit 306 may operate in response to the control of the control logic unit 304 .

[0096] In one implementation, the voltage supply circuit 306 may regulate an external supply voltage and generate an internal supply voltage.

[0097] In one implementation, the voltage supply circuit 306 may generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage.

[0098] The voltage supply circuit 306 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and generate the plurality of operating voltages Vop by selectively activating the plurality of pumping capacitors in response to control of the control logic unit 304 .

[0099] The generated operating voltages Vop may be supplied to the memory cell array 201 by the address decoder 307. For example, the voltage supply circuit 306 may adjust a level and a supply time of each of the operating voltages Vop in response to the operation signal OP_SIG.

[0100] For example, the voltage supply circuit 306 may generate a programming voltage PGM<1:7>, a pass voltage, a verification voltage VRY<1:7>, a read voltage, an erase voltage, etc. as an operation voltage VOP, and supply the generated operation voltage VOP to the address decoder 307. For example, during a programming operation, the voltage supply circuit 306 may generate a programming voltage, a pass voltage, and a verification voltage as an operation voltage VOP in response to an operation signal OP_SIG, and supply the generated operation voltage VOP to the address decoder 307. In this case, the programming voltage may be a voltage supplied to a programming word line, and the pass voltage may be a voltage supplied to a word line that is not selected as a programming target. The voltage supply circuit 306 may adjust the supply time of each operation voltage VOP according to the operation signal OP_SIG. For example, the voltage supply circuit 306 may adjust the output time of each of the programming voltage, the pass voltage, and the verification voltage according to the operation signal OP_SIG, and output the voltage according to the adjusted time.

[0101] The page buffer unit 302 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 201 through a plurality of bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may operate in response to control of the control logic unit 304 .

[0102] The plurality of page buffers PB1 to PBm may transfer data DATA with the data input / output circuit 157. During a program operation, the plurality of page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 157 and the data lines DL.

[0103] After the program operation starts, the plurality of page buffers PB1 to PBm may store data DATA received from the outside through the data input / output circuit 305, and may transmit a program enable voltage or a program disable voltage to the bit lines BL1 to BLm in response to the stored data DATA. For example, the program enable voltage may be 0V, and the program disable voltage may be a power supply voltage.

[0104] After the read operation starts, the plurality of page buffers PB1 to PBm may sense data DATA based on voltages or currents of bit lines BL1 to BLm determined according to threshold voltages of memory cells of a selected page and may transmit the sensed data DATA to the data input / output circuit 305 through data lines DL.

[0105] After the erase operation starts, the plurality of page buffers PB1 to PBm may float the bit lines BL1 to BLm or may apply a voltage of 0V to the bit lines BL1 to BLm.

[0106] The data input / output circuit 305 may include a plurality of input / output buffers (not illustrated) receiving data DATA input thereto. During a program operation, the data input / output circuit 305 may receive data DATA to be stored from the outside. During a read operation, the data input / output circuit 305 may output data DATA transmitted from a plurality of page buffers PB1 to PBm included in the page buffer unit 302 to the outside.

[0107] After the read operation or the verification operation starts, the inspection unit 303 of the control circuit unit 309 may generate a reference current in response to the verification reference signal VRYBIT generated by the control logic unit 304, may compare the sensing voltage VPB received from the page buffer unit 302 with the reference voltage generated from the reference current, and may output a pass signal PASS or a fail signal FAIL to the control logic unit 304. For example, when the level of the sensing voltage VPB is higher than or equal to the level of the reference voltage, the inspection unit 303 may output the pass signal PASS to the control logic unit 304. When the level of the sensing voltage VPB is lower than the level of the reference voltage, the inspection unit 303 may output the fail signal FAIL to the control logic unit 304.

[0108] The control logic unit 304 may be connected to the address decoder 307, the voltage supply circuit 306, the page buffer unit 302, the data input / output circuit 305, and the check unit 303 included in the control circuit unit 309. The control logic unit 304 may be configured to control the overall operation of the memory device 150. The control logic unit 304 may operate in response to a command CMD from an external device.

[0109] The control logic unit 304 may control the control circuit unit 309 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic unit 304 may generate an operation signal OPSIG, an address RADD, a read and write control signal PBSIGNALS, and a verification reference signal VRYBIT in response to the command CMD and the address ADDR. The control logic unit 304 may output the operation signal OPSIG to the voltage supply circuit 306, may output the address RADD to the address decoder 307, may output the read and write control signal PBSIGNALS to the page buffer unit 302, and may output the verification reference signal VRYBIT to the inspection unit 303. In addition, the control logic unit 304 may determine whether the verification operation has passed or failed in response to a pass signal or a fail signal PASS / FAIL output by the inspection unit 303.

[0110] Specifically, the count storage section 311 included in the control logic unit 304 may store program count values ​​of a plurality of pages included in the memory cell array 201. Therefore, the count storage section 311 may store a program count value corresponding to a program address indicating a program cell.

[0111] The program controller 312 included in the control logic unit 304 may control a program operation with respect to the program unit.

[0112] Furthermore, the program controller 312 may check whether a program operation for a program unit is a rewrite operation according to a program count value OVC corresponding to the program unit stored in the count storage section 311 .

[0113] In addition, the program controller 312 may set the voltage level of the initial program pulse PGM1 applied to the program word line in the voltage application operation VIO included in the initial program loop PL1 among the program loops PL1 to PL7 to one of the first level D1 and the second level D2, depending on whether the program operation for the program unit is a rewrite operation. Herein, the second level D2 may be a level lower than the first level D1 by the first setting level Va.

[0114] In addition, the program controller 312 may set the increment from the voltage level of the initial programming pulse to the voltage level of the second programming pulse to one of the third level D3 and the fourth level D4 according to whether the programming operation for the programming unit is a rewrite operation. The initial programming pulse and the second programming pulse may be applied to the programming word line in the voltage application operation VIO respectively included in the initial programming loop and the second programming loop among the programming loops PL1 to PL7 repeated according to the ISPP method for the programming unit. Herein, the fourth level D4 may be a level lower than the third level D3 by the second setting level Vb. In addition, the second programming loop may be a programming loop repeated after the initial programming loop.

[0115] In addition, whenever a programming operation on a programming unit is successfully performed, the programming controller 312 may increase the programming count value stored in the count storage unit 311. Regardless of whether the programming operation on the programming unit is a normal programming operation or a rewrite operation, the programming controller 312 may increase the programming count value for the programming unit in response to a successful programming operation. Herein, the programming controller 312 may generate a signal UP corresponding to a successful programming operation on the programming unit and transmit it to the count storage unit 311. The count storage unit 311 may increase the programming count value in response to the output signal UP of the programming controller 312.

[0116] Furthermore, when the program operation for the program unit is a rewrite operation, the program controller 312 may adjust the first setting level Va according to the program count value corresponding to the program unit. The program controller 312 may increase the first setting level Va in proportion to the program count value corresponding to the program unit.

[0117] When the program operation for the program unit is a rewrite operation, the program controller 312 may adjust the second setting level Vb according to the program count value corresponding to the program unit. The program controller 312 may increase the second setting level Vb in proportion to the program count value corresponding to the program unit.

[0118] The option controller 313 included in the control unit 202 may control whether to enable the blind option in response to the output signal SBC of the program controller 312. When the program operation for the program unit is a rewrite operation, the program controller 312 may output the signal SBC having a value for disabling the blind option to the option controller 313. In addition, the program controller 312 may output the signal SBC having a value for enabling the blind option to the option controller 313 in response to a successful program operation on the program unit.

[0119] Figure 6 The invention is described in one embodiment according to the present invention. Figure 1 A flowchart showing the sequence of programming operations performed in a memory device is shown in FIG.

[0120] Reference Figure 6 , in operation S10 , a program command and a program address may be input to the memory device 150 .

[0121] In operation S20 , it may be checked whether a program count value corresponding to a program address is “0”.

[0122] When the program count value is "0" in operation S20 ("Yes" in operation S20), a program operation for a program unit indicated by a program address may be performed in operation S50. When the program count value is "0" in operation S20 ("Yes" in operation S20), there is no need to perform a rewrite operation, and thus a normal program operation may be performed through operation S50.

[0123] In operation S60 , in response to completion of the normal program operation in operation S50 , the program count value may be increased by 1. In addition, since the blind option is never disabled before the normal program operation is performed in operation S50 , the blind option may remain enabled in operation S70 .

[0124] When the program count value is not "0" in operation S20 ("No" in operation S20), a rewrite operation needs to be performed. Therefore, in operation S30, the blind option may be disabled.

[0125] In operation S40 after operation S30 , according to the program count value, the voltage level of the initial program pulse PGM1 may be set, and an increment of the voltage level may be set in each of the program loops PL1 to PL7 .

[0126] After operation S40 , in operation S50 , a rewrite operation may be performed on a program unit indicated by a program address.

[0127] In operation S60, a program count value corresponding to the program unit may be increased by 1 in response to completion of the rewrite operation in operation S50. In addition, in operation S70, a blind option may be enabled in response to completion of the rewrite operation in operation S50. Since the blind option has been disabled by operation S30 before the rewrite operation is performed in operation S50, the blind option may be switched to an enabled state by operation S70.

[0128] According to one embodiment of the present invention, the level of a program pulse applied to a program target word line in an initial program loop may be adjusted according to whether the operation is a rewrite operation.

[0129] Furthermore, according to an embodiment of the present invention, the amount by which the level of a program pulse applied to a program target word line in an initial program loop is adjusted may vary according to the number of repetitions of a rewrite operation.

[0130] Furthermore, according to one embodiment of the present invention, the increment of the voltage level of the program pulse may be adjusted in repeated program loops according to whether the operation is a rewrite operation.

[0131] In addition, according to an embodiment of the present invention, the amount of increment of the voltage level of the program pulse adjusted in the repeated program loop may vary according to the number of repetitions of the rewrite operation.

[0132] According to one embodiment of the present invention, whether to disable the blind option may be selected according to whether the operation is a rewrite operation.

[0133] In this way, degradation of the distribution of memory cells to be programmed in a rewrite operation can be minimized.

[0134] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

[0135] CROSS-REFERENCE TO RELATED APPLICATIONS

[0136] This application claims priority to Korean Patent Application No. 10-2023-0078006, filed on June 19, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a memory cell array comprising memory cells coupled between a word line and a plurality of bit lines; as well as a control unit adapted to perform a programming operation on the memory cell according to an incremental step pulse programming (ISPP) method until the programming operation is successfully performed, the programming operation repeating a programming loop including a voltage applying operation and a verification operation, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of a first level and a second level according to whether the program operation is a rewrite operation, wherein the initial programming pulse is to be applied to the word line in the voltage applying operation included in an initial programming loop in the repeated programming loops, and The second level is lower than the first level by a first setting level.

2. The memory device according to claim 1, wherein: The control unit also repeatedly performs the program loop by setting an increment from the voltage level of the initial program pulse to a voltage level of a second program pulse to one of a third level and a fourth level according to whether the program operation is the rewrite operation, wherein the second programming pulse is to be applied to the word line in the voltage applying operation included in a second programming loop after the initial programming loop among the repeated programming loops, and The fourth level is lower than the third level by a second setting level.

3. The memory device according to claim 2, wherein: The control unit sets the voltage level of the initial program pulse to the second level and sets the increment to the fourth level when the program operation is the rewrite operation.

4. The memory device according to claim 2, wherein: The control unit is also suitable for: In response to success of the program operation, increasing a program count value corresponding to a value indicating a program address of the memory cell, and It is checked whether the program operation is the rewrite operation according to the program count value.

5. The memory device according to claim 4, wherein: The control unit is further adapted to adjust the first setting level and the second setting level according to the program count value when the programming operation is the rewriting operation.

6. The memory device according to claim 1, wherein: The control unit is further adapted to set a blind option to a disabled state before the programming operation starts when the programming operation is the rewrite operation and to set the blind option to an enabled state in response to a successful programming operation.

7. The memory device according to claim 2, wherein: The control unit comprises: a count storage section adapted to store a program count value corresponding to a value indicating a program address of the memory cell; and A programming controller, wherein the programming controller is suitable for: checking whether the programming operation is the rewriting operation according to the programming count value, setting the voltage level of the initial programming pulse, and Set the increment.

8. The memory device according to claim 7, wherein: The program controller is further adapted to increment the program count value in response to a successful program operation.

9. The memory device according to claim 7, wherein: The program controller is further adapted to increase the first setting level and the second setting level in proportion to the program count value when the program operation is the rewrite operation.

10. The memory device according to claim 7, wherein: The program controller is further adapted to output a signal to disable a blind option when the program operation is the rewrite operation, and to output a signal to enable the blind option in response to a successful program operation.

11. The memory device according to claim 10, wherein: The control unit further includes an option controller adapted to control whether the blind option is enabled in response to an output signal of the programming controller.

12. A method for operating a memory device, the memory device comprising a memory cell coupled between a word line and a plurality of bit lines, the method comprising the steps of: performing a programming operation on the memory cell according to an incremental step pulse programming (ISPP) method until the programming operation is successfully performed, the programming operation repeating a programming loop including a voltage applying operation and a verification operation; as well as checking whether the programming operation is a rewrite operation, The repeatedly executed steps include: setting the voltage level of the initial programming pulse to one of a first level and a second level according to whether the programming operation is the rewriting operation, wherein the initial programming pulse is to be applied to the word line in the voltage applying operation included in an initial programming loop in the repeated programming loops, and The second level is lower than the first level by a first setting level.

13. The method according to claim 12, wherein: The step of executing further includes: setting an increment from the voltage level of the initial programming pulse to the voltage level of the second programming pulse to one of a third level and a fourth level according to whether the programming operation is the rewrite operation, wherein the second programming pulse is applied to the word line in the voltage applying operation included in a second programming loop after the initial programming loop among the repeated programming loops, and The fourth level is lower than the third level by a second setting level.

14. The method according to claim 13, in, When the programming operation is the rewriting operation, the voltage level of the initial programming pulse is set to the second level, and Wherein, when the programming operation is not the rewriting operation, the voltage level of the initial programming pulse is set to the first level.

15. The method according to claim 14, in, When the programming operation is the rewriting operation, the increment is set to the fourth level, and Wherein, when the programming operation is not the rewriting operation, the increment is set to the third level.

16. The method according to claim 15, further comprising the steps of: incrementing a program count value corresponding to a value indicating a program address of the memory cell in response to a successful program operation, Whether the program operation is the rewrite operation is checked based on the program count value.

17. The method according to claim 16, further comprising the steps of: When the program operation is the rewrite operation, the first setting level is increased in proportion to the program count value.

18. The method according to claim 16, further comprising the steps of: When the program operation is the rewrite operation, the second setting level is increased in proportion to the program count value.

19. The method according to claim 12, further comprising the steps of: When the programming operation is the rewrite operation, setting the blind option to a disabled state before the programming operation starts; as well as The blind option is set to an enabled state in response to a successful programming operation.

20. A method for operating a memory device, the method comprising the following steps: reducing at least one of a voltage level and an increment of a programming pulse in proportion to the number of times a programming operation has succeeded on a group of memory cells according to an incremental step pulse programming (ISPP) scheme; as well as According to the ISPP scheme, the programming operation is performed based on a reduced voltage level and an increment, Wherein, the programming pulses are provided to the group of memory cells at least during each of an initial programming loop and subsequent programming loops within the programming operation.

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