Preparation method for reducing reverse leakage current of silicon carbide diode
By forming a protective oxide layer and P-type doped region in the silicon carbide diode, combined with the design of Schottky contact electrode and passivation layer, the problem of insufficient reliability of the silicon carbide diode in high-voltage and high humidity environment is solved, and the problem of insufficient reliability of the silicon carbide diode in high-voltage and high humidity environment is realized. High reliability and stable operation of the device.
Patent Information
- Application Number
- CN202411317288.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-20
AI Technical Summary
The existing silicon carbide diodes have insufficient reliability in high-voltage and high humidity environments, resulting in device failure, making it difficult to meet users' requirements for high reliability and stable operation.
By growing a silicon carbide epitaxial layer on a silicon carbide substrate, and forming an oxide layer and an oxidation protrusion layer with a thickness of not less than 40 nm thereon, Al ion implantation and sacrificial oxidation etching are performed to form a P-type doping region, and then through Chemical vapor deposition method forms field oxygen and forms Schottky contact electrodes and passivation layers at the terminal to improve the reverse leakage current performance of the device.
It effectively reduces the reverse leakage current of the silicon carbide diode, improves the reliability of the device, can operate stably in a high-voltage and high humidity environment, and meets the requirements of high reliability.
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Figure CN119170500A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a preparation method for reducing reverse leakage current of a silicon carbide diode. Background Art
[0002] Today, power devices based on silicon (Si) materials have approached the theoretical limit determined by the characteristics of the material itself as their structural design and manufacturing processes have become increasingly perfect. Therefore, the potential for further improvement and enhancement of Si device design and process is very limited. On the other hand, the development of technologies such as navigation, aviation, aerospace, high-speed rail transportation, and smart grids has put forward higher requirements for the performance of power devices. At the same time, due to the increasing prominence of energy crisis and environmental problems, there is an urgent need to solve the problems of how to reduce energy waste and alleviate environmental pollution. As a result, the application fields such as hybrid electric vehicles, solar energy and wind power generation have also put forward new requirements for power devices. In the process of the advancement of silicon carbide devices, efficient device design methods, stable and low-cost wafer production processes, and the behavioral characteristics and reliability of devices under abnormal conditions all need to be carefully studied, and silicon carbide diodes are an excellent platform for studying these problems.
[0003] The most popular silicon carbide diodes on the market are Junction Barrier Schottky diode (JBSdiode) and Merged PiN Schottky diode (MPS diode). They have achieved a good balance between forward conduction, reverse blocking performance and surge and avalanche reliability. Therefore, many researchers have conducted in-depth research on them, and many manufacturers have developed mature commercial products.
[0004] With the continuous update and iteration of device performance, users are no longer satisfied with only focusing on the static performance of the device, and the reliability of the device is also of concern to users. Therefore, the reliability of the device has become particularly prominent. Especially for some customers who have special requirements for reliability, they will use the industry's most stringent AEC-Q101 standard to evaluate the products of different manufacturers, especially in some high-voltage and high-humidity (85°C, 85%RH, 80%VR) environments may cause device failure. Therefore, the development of a device that improves the high reliability of the HV-H3TRB device and meets the requirements of stable operation of silicon carbide diodes in high-voltage and high-humidity environments is a technical problem that needs to be solved urgently in the industry. Summary of the invention
[0005] In view of the above problems, the present invention provides a preparation method for reducing the reverse leakage current of a silicon carbide diode, which can meet the requirements of stable operation in a high-voltage and high-humidity environment and improve the reliability of the device.
[0006] The technical solution of the present invention is: A preparation method for reducing reverse leakage current of a silicon carbide diode comprises the following steps: Step 1, growing a silicon carbide epitaxial layer on a silicon carbide substrate; Step 2, forming an oxide layer and an oxide protrusion layer with a thickness of not less than 40 nm on the silicon carbide epitaxial layer; Specifically, an initial oxide layer is formed on the silicon carbide epitaxial layer, and the Al ion implantation area on the oxide layer is etched through an etching process, and Al ion implantation is performed after etching; after the etching process, the thickness of the oxide layer with a flat cross section is not less than 40nm, and the thickness of the area etched on the side, that is, the oxide protrusion layer, is 0.2um~0.5um; Step 3: high temperature annealing and sacrificial oxidation etching; then ion implantation is performed to form a P-type doped region; Step 4, forming field oxygen on the P-type doping region 2 and the P-type doping region 3 at the terminal by chemical vapor deposition; Step 5, sputtering metal on the P-type doping region 1 and the P-type doping region 2, and forming a Schottky contact electrode after annealing; Step 6, depositing a front thickened metal on the Schottky contact electrode as an anode lead; Step 7: Make a passivation layer at the device terminal position, starting from the left side of the terminal and ending at the chip dicing road; Step eight, sequentially fabricating a back ohmic contact electrode and a thickened metal on the back side of the silicon carbide substrate.
[0007] Specifically, in step three, the thickness of the sacrificial oxide etching is not less than 50 nm.
[0008] Specifically, in step three, the P-type doping region includes a plurality of P-type doping regions one, a plurality of P-type doping regions two and a plurality of P-type doping regions three.
[0009] Specifically, in step three, the depth of the P-type doping region is 0.5um-1um.
[0010] Specifically, in step five, the Schottky annealing temperature is 400°C-500°C.
[0011] Specifically, the passivation layer in step seven includes an inorganic passivation layer and an organic passivation layer of different dielectrics.
[0012] Specifically, the inorganic passivation layer includes a first SiO 2 layer, SiN layer and the second SiO 2 layer.
[0013] Specifically, the first SiO 2 Layer and second SiO 2 The thickness of each layer is not less than 200 nm; The thickness of the SiN layer is not less than 600 nm.
[0014] Specifically, the organic passivation layer is a polyimide layer.
[0015] Specifically, in step 2, etching is performed in the area to be implanted with Al ions, and the etching depth is 0.2 um to 0.5 um.
[0016] In the present invention, by changing the preparation process method, before aluminum ion implantation, an oxide layer is formed on the silicon carbide epitaxial layer by a deposition method to protect the epitaxial layer from damage during ion implantation, and after the implantation, sacrificial oxidation over-etching is performed to make the surface of the entire epitaxial layer smoother, so that the reverse leakage current of the entire device is smaller, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a structural schematic diagram of step S100 of the present invention; Figure 2 is a structural schematic diagram of step S200 of the present invention; Figure 3 is a schematic structural diagram of step S300 of the present invention; Figure 4 is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S600 of the present invention; Figure 8 is a schematic diagram of the structure of step S700 of the present invention; Fig. 9 is a structural schematic diagram of step S800 of the present invention; Fig.10 is a structural schematic diagram of step S900 of the present invention; In the figure, 1 is a silicon carbide substrate, 2 is a silicon carbide epitaxial layer, 3 is an oxide layer, and 31 is an oxide protrusion layer. 4 is a P-type doping region, 4a is a P-type doping region 1, 4b is a P-type doping region 2, 4c is a P-type doping region 3, 5 is field oxygen, 6 is a Schottky contact electrode, 7 is the front thickened metal, 8 is an inorganic passivation layer, 8a is a first SiO 2 layer, 8b is a SiN layer, 8c is a second SiO 2 layer, 9 is an organic passivation layer, 10 is a back ohmic contact electrode, and 11 is a thickened metal. DETAILED DESCRIPTION
[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0019] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0020] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0021] Reference below Figure 1-10 describe the invention; A preparation method for reducing reverse leakage current of a silicon carbide diode comprises the following steps: Step 1, such as Figure 1 As shown, a silicon carbide epitaxial layer 2 is grown on a silicon carbide substrate 1; Step 2, such as Figure 2 As shown, before ion implantation, an initial oxide layer is formed on the silicon carbide epitaxial layer 2 by deposition, and etching is performed in the area to be implanted with Al ions to form Figure 2 Structure, Al ion implantation is performed after etching; the implantation temperature is 450℃-550℃, the implantation energy is 20KV-500KV, and in order to ensure the appropriate implantation morphology, it is generally divided into multiple implantations; The primary oxide layer includes an oxide layer 3 having a thickness of not less than 40 nm and an oxide protrusion layer 31; Specifically, an initial oxide layer is formed on the silicon carbide epitaxial layer 2, and the Al ion to be implanted area on the oxide layer 3 is etched through an etching process, and Al ions are implanted after etching; after the etching process, the thickness of the oxide layer 3 with a flat cross section is not less than 40nm, and the area etched on the side, that is, the oxide protrusion layer 31, is 0.2um~0.5um thick; The oxide layer 3 is a protection before ion implantation, protecting the silicon carbide epitaxial layer from damage caused by implantation, especially at the terminal position. Interface state problems can cause leakage current to increase. The thickness is not less than 40nm based on the energy considerations of the implanter. A medium-speed flow implanter is currently used. When deviations occur in the alignment window, if the thickness is less than 40nm, there is a risk of failure to provide protection.
[0022] Step three, high temperature annealing is performed after the implantation is completed, and sacrificial oxidation etching is performed after the annealing is completed, and the etching thickness is not less than 50nm; that is, the surface of the implanted part is overetched to make the interface bonding better.
[0023] After sacrificial oxide etching, ion implantation is performed to form a P-type doped region 4. Figure 3 As shown; The thickness of the sacrificial oxide etching is not less than 50 nm, that is, the surface of the implanted part is overetched, so that the interface bonding is better.
[0024] The depth of the P-type doping region 4 is 0.5 um to 1 um.
[0025] The activation temperature after ion implantation is relatively high, at 1600-1800°C, and the time is 10-30 minutes. In order to prevent the precipitation of silicon atoms in high-temperature silicon carbide and cause surface carbonization, a carbon film is sputtered for protection before high-temperature annealing.
[0026] Step 4, forming a field oxide 5 on the P-type doping region 2 4b and the P-type doping region 3 4c at the terminal by chemical vapor deposition; Figure 4 As shown; Step 5: sputtering metal on the P-type doping region 1 4a and the P-type doping region 2 4b, and forming a Schottky contact electrode 6 after annealing. The Schottky annealing temperature is generally 400°C-500°C; Figure 5 As shown; Step 6: deposit a front thickened metal 7 on the Schottky contact electrode 6 as an anode lead; Figure 6 As shown; Step 7: Make a passivation layer at the device terminal position. The passivation layer starts from the left side of the terminal and ends at the chip dicing road. The passivation layer can be made of two layers of different media. The lower layer is an inorganic passivation layer 8 and the upper layer is an organic passivation layer 9, which plays the role of isolating water vapor and protecting the terminal; refer to Figure 7 and Figure 8 As shown; The inorganic passivation layer 8 includes a first SiO 2 layer 8a, SiN layer 8b and the second SiO 2 Layer 8c.
[0027] Step 8: fabricating a back ohmic contact electrode 10 on the back side of the silicon carbide substrate 1; Fig. 9 As shown; Step nine, depositing thickened metal 11 on the ohmic contact electrode 10 to form a cathode, completing the device manufacturing, refer to Fig.10 shown.
[0028] In step 2 of the present case, before ion implantation, a protective oxide layer 3 is formed on the silicon carbide epitaxial layer by deposition, and its thickness is not less than 40nm, which plays a role in protecting the epitaxial layer 2 and reducing the reverse leakage current of the device; P-type implantation is high-temperature implantation of aluminum ions, the injection temperature is 450℃-550℃, the injection energy is 20KV-500KV, and in order to ensure the appropriate implantation morphology, it is generally divided into multiple implantations.
[0029] The structure of the silicon carbide diode in this case includes a thickened metal 11, a back ohmic contact electrode 10, a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2 arranged in sequence from bottom to top; the thickness of the thickened metal 11 ranges from 1um to 2um.
[0030] The top surface of the silicon carbide epitaxial layer 2 is provided with a plurality of P-type doping regions 1 4a, a P-type doping region 2 4b and a plurality of P-type doping regions 3 4c extending downward; the P-type doping region 2 4b is located in the middle region of the silicon carbide epitaxial layer 2; The top surfaces of the P-type doping region 2 4b and the plurality of P-type doping regions 3 4c are provided with a horizontally extending field oxide 5; The top surfaces of the P-type doping region 1 4a and the P-type doping region 2 4b are provided with Schottky contact electrodes 6 climbing to the top surface of the field oxide 5; The top surface of the Schottky contact electrode 6 is provided with a front thickening metal 7; A passivation layer is provided on the field oxide 5 and the front thickened metal.
[0031] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. A method for reducing reverse leakage current of a silicon carbide diode, characterized in that: The following steps are involved: Step 1: growing a silicon carbide epitaxial layer (2) on a silicon carbide substrate (1); Step 2: forming an oxide layer (3) and an oxide protrusion layer (31) with a thickness of not less than 40 nm on the silicon carbide epitaxial layer (2); Specifically, a primary oxide layer is formed on the silicon carbide epitaxial layer (2), and an etching process is performed on the oxide layer (3) in the area to be implanted with Al ions, and Al ions are implanted after etching; after the etching process, the oxide layer (3) with a flat cross section has a thickness of not less than 40 nm, and the area etched on the side, i.e., the oxide protrusion layer 31, has a thickness of 0.2 μm to 0.5 μm; Step 3: high temperature annealing and sacrificial oxidation etching; Then, ion implantation is performed to form a P-type doped region (4); Step 4, forming field oxide (5) on the P-type doping region 2 (4b) and the P-type doping region 3 (4c) at the terminal by chemical vapor deposition; Step 5, sputtering metal on the P-type doping region 1 (4a) and the P-type doping region 2 (4b), and forming a Schottky contact electrode (6) after annealing; Step 6, depositing a front thickened metal (7) on the Schottky contact electrode (6) as an anode lead; Step 7: Make a passivation layer at the device terminal position, starting from the left side of the terminal and ending at the chip dicing road; Step eight: sequentially fabricating a back ohmic contact electrode (10) and a thickened metal (11) on the back side of the silicon carbide substrate (1).
2. A method for reducing reverse leakage current of a silicon carbide diode according to claim 1, characterized in that: In step three, the thickness of the sacrificial oxide etching is not less than 50 nm.
3. The method for reducing reverse leakage current of a silicon carbide diode according to claim 1, characterized in that: In step three, the P-type doping region (4) includes a plurality of P-type doping regions one (4a), a P-type doping region two (4b) and a plurality of P-type doping regions three (4c).
4. The method for reducing reverse leakage current of a silicon carbide diode according to claim 1, characterized in that: In step 3, the depth of the P-type doped region (4) is 0.5 um to 1 um.
5. The method for reducing reverse leakage current of a silicon carbide diode according to claim 1, characterized in that: In step 5, the Schottky annealing temperature is 400°C-500°C.
6. The method for reducing reverse leakage current of a silicon carbide diode according to claim 1, characterized in that: In step seven, the passivation layer includes an inorganic passivation layer (8) and an organic passivation layer (9) of different dielectrics.
7. A method for reducing reverse leakage current of a silicon carbide diode according to claim 6, characterized in that: The inorganic passivation layer (8) comprises a first SiO2 layer (8a), a SiN layer (8b) and a second SiO2 layer (8c) which are arranged in sequence from bottom to top.
8. A method for reducing reverse leakage current of a silicon carbide diode according to claim 7, characterized in that: The thickness of the first SiO2 layer (8a) and the second SiO2 layer (8c) is not less than 200 nm respectively; The thickness of the SiN layer (8b) is not less than 600 nm.
9. The method for reducing reverse leakage current of a silicon carbide diode according to claim 6, characterized in that: The organic passivation layer (9) is a polyimide layer.
10. The method for reducing reverse leakage current of a silicon carbide diode according to claim 6, characterized in that: In step 2, etching is performed in the area to be implanted with Al ions, and the etching depth is 0.2um~0.5um.