Semiconductor structure and forming method of semiconductor structure
By forming channel regions of different widths in the semiconductor structure and selectively applying stress layers, the problem of static SRAM leakage in the prior art is solved, the device performance is optimized and the risk of excessive leakage current is reduced.
Patent Information
- Application Number
- CN202310730250.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-19
- Publication Date
- 2024-12-20
AI Technical Summary
The prior art is difficult to effectively reduce SRAM static leakage, affecting the low-power performance of semiconductor structures.
By forming the first and second gate structures in the semiconductor structure, each having channel regions of different widths, and forming initial stress layers in the corresponding regions, the unnecessary stress layers are selectively removed, and the width of the channel region is relatively small only. Large areas retain stress layers to provide appropriate stresses and optimize device performance.
It provides appropriate stress to devices that require stress, improves electron mobility, avoids negative impacts on devices that do not require stress, optimizes the performance of semiconductor structures, and reduces the problem of large leakage current.
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Figure CN119170502A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art
[0002] With the development of technology, ultra-low power consumption platforms are the first choice for wireless RF chips such as IOT, WIFI, and Bluetooth, and their low power consumption performance is the main reference indicator for customers. The power consumption in CMOS circuits is divided into dynamic power consumption and static power consumption. Reducing dynamic power consumption is generally achieved by reducing the operating voltage. SRAM static leakage accounts for the main part of static power consumption, so how to reduce SRAM static leakage through process optimization has become the main issue in the development of ultra-low power consumption platforms and have a certain degree of competitiveness. Summary of the invention
[0003] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.
[0004] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a first gate structure on the first region, the substrate at the bottom of the first gate structure having a first channel region, the first channel region having a first width in a direction parallel to the substrate surface; forming a second gate structure on the second region, the substrate at the bottom of the second gate structure having a second channel region, the second channel region having a second width in a direction parallel to the substrate surface, the first width being greater than the second width; forming an initial stress layer on the substrate surface, the top surface and side wall surfaces of the first gate structure, and the top surface and side wall surfaces of the second gate structure; removing the initial stress layer on the top surface and side wall surfaces of the second gate structure, and the surface of the second region, and forming a stress layer on the surface of the first region, and the top surface and side wall surfaces of the first gate structure.
[0005] Optionally, before forming the initial stress layer, it also includes: forming a first source-drain doped region in the first area on both sides of the first gate structure, the first channel region is located between the first source-drain doped regions on both sides of the first gate structure, and the first width is the width between the first source-drain doped regions; forming a second source-drain doped region in the second area on both sides of the second gate structure, the second channel region is located between the second source-drain doped regions on both sides of the second gate structure, and the second width is the width between the second source-drain doped regions.
[0006] Optionally, the first source-drain doped region and the second source-drain doped region have the same conductivity type.
[0007] Optionally, the conductivity type of the first source-drain doping region and the second source-drain doping region includes N type.
[0008] Optionally, the stress layer includes a tensile stress layer; the material of the tensile stress layer includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
[0009] Optionally, the conductivity type of the first source-drain doping region and the second source-drain doping region includes P type.
[0010] Optionally, the stress layer includes a compressive stress layer; and the material of the compressive stress layer includes silicon germanium.
[0011] Optionally, the stress layer has a thickness range of less than 1000 angstroms.
[0012] Optionally, the first width is in the range of: greater than or equal to 1 micron.
[0013] Optionally, the second width is in the range of less than 1 micron.
[0014] Optionally, the method for removing the initial stress layer on the top surface and sidewall surfaces of the second gate structure, and the surface of the second region includes: providing an initial layout, the initial layout including a first region and a second region corresponding to the substrate; obtaining an area of the second region on the initial layout; obtaining an exposure layout based on the area of the second region on the initial layout; forming a photoresist layer on the initial stress layer; exposing and developing the photoresist layer based on a mask generated by the exposure layout, removing the photoresist layer on the second region, exposing the top surface and sidewall surfaces of the second gate structure, and the surface of the initial stress layer on the surface of the second region; removing the initial stress layer exposed on the second region, and forming a stress layer on the surface of the first region, and the top surface and sidewall surfaces of the first gate structure.
[0015] Optionally, the substrate also includes a third region; and also includes: forming a third gate structure located on the third region and forming third source-drain doped regions located in the third region on both sides of the third gate structure, wherein the third source-drain doped regions have a conductivity type opposite to that of the first source-drain doped regions and the second source-drain doped regions, and the initial stress layer is also located on the top surface and side wall surface of the third gate structure; while removing the initial stress layer on the top surface and side wall surface of the second gate structure and the surface of the second region, the top surface and side wall surface of the third gate structure and the initial stress layer on the surface of the third region are also removed.
[0016] Optionally, the process of removing the top surface and sidewall surfaces of the second gate structure and the initial stress layer on the surface of the second region includes: a wet etching process or a dry etching process.
[0017] Optionally, the method further includes: performing annealing treatment on the stress layer; and removing the stress layer after annealing the stress layer.
[0018] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a first gate structure located on the first region, the substrate at the bottom of the first gate structure having a first channel region, the first channel region having a first width in a direction parallel to the substrate surface; a second gate structure located on the second region, the substrate at the bottom of the second gate structure having a second channel region, the second channel region having a second width in a direction parallel to the substrate surface, the first width being greater than the second width; and a stress layer located on the surface of the first region, and on the top surface and sidewall surface of the first gate structure.
[0019] Optionally, it also includes: a first source-drain doped region located in the first area on both sides of the first gate structure, the first channel region is located between the first source-drain doped regions on both sides of the first gate structure, and the first width is the width between the first source-drain doped regions; a second source-drain doped region located in the second area on both sides of the second gate structure, the second channel region is located between the second source-drain doped regions on both sides of the second gate structure, and the second width is the width between the second source-drain doped regions.
[0020] Optionally, the first source-drain doped region and the second source-drain doped region have the same conductivity type.
[0021] Optionally, the conductivity type of the first source-drain doping region and the second source-drain doping region includes N type.
[0022] Optionally, the stress layer includes a tensile stress layer; the material of the stress layer includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
[0023] Optionally, the conductivity type of the first source-drain doping region and the second source-drain doping region includes P type.
[0024] Optionally, the stress layer includes a compressive stress layer; and the material of the compressive stress layer includes silicon germanium.
[0025] Optionally, the stress layer has a thickness range of less than 1000 angstroms.
[0026] Optionally, the first width is in the range of: greater than or equal to 1 micron.
[0027] Optionally, the second width is in the range of less than 1 micron.
[0028] Optionally, the substrate also includes a third region; and also includes: a third gate structure located on the third region and third source-drain doped regions located in the third region on both sides of the third gate structure, wherein the third source-drain doped regions have a conductivity type opposite to that of the first source-drain doped regions and the second source-drain doped regions.
[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0030] According to the technical solution of the present invention, the first width of the first channel region at the bottom of the first gate structure is greater than the second width of the second channel region at the bottom of the second gate structure, and an initial stress layer is first formed on the substrate surface, the top surface and sidewall surface of the first gate structure, and the top surface and sidewall surface of the second gate structure, and then the initial stress layer on the top surface and sidewall surface of the second gate structure and the surface of the second region is removed, and a stress layer is formed on the surface of the first region and the top surface and sidewall surface of the first gate structure. The stress layer only exists on the surface of the first region with a larger channel region width, and the top surface and sidewall surface of the first gate structure, so that stress can be selectively provided to the device on the first region where stress needs to be provided, avoiding the situation where the stress layer has a negative impact on the device on the second region where stress does not need to be provided, thereby optimizing the performance of the semiconductor structure.
[0031] Furthermore, the conductivity type of the first source-drain doped region and the second source-drain doped region includes an N type, and the stress layer includes a tensile stress layer. The first width of the first channel region at the bottom of the first gate structure is greater than the second width of the second channel region at the bottom of the second gate structure, and the stress layer only provides tensile stress for the NMOS in the first region with a larger channel width, so as to improve the mobility of electrons in the device on the first region, avoid the stress layer providing tensile stress for the NMOS in the second region with a smaller channel width, prevent the negative effect of causing excessive leakage current, and optimize the performance of the semiconductor structure.
[0032] Furthermore, the conductivity type of the first source-drain doped region and the second source-drain doped region includes a P type, and the stress layer includes a compressive stress layer. The first width of the first channel region at the bottom of the first gate structure is greater than the second width of the second channel region at the bottom of the second gate structure, and the stress layer only provides compressive stress for the PMOS in the first region with a larger channel width, so as to improve the mobility of electrons in the device on the first region, avoid the stress layer providing compressive stress for the PMOS in the second region with a smaller channel width, prevent the negative effect of excessively large leakage current, and optimize the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figures 1 to 4 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION
[0034] As described in the background art, how to achieve low power consumption performance through process optimization is an issue that needs to be solved urgently.
[0035] Specifically, stress memorization technology (SMT) is a commonly used method for improving the performance of NMOS devices at 40nm and below nodes. The stress layer technology specifically includes: first depositing a stress layer that can provide tensile stress on the surface of the NMOS device, and then annealing. During annealing, the stress layer can generate tensile stress in the channel of the NMOS device, and finally remove the stress layer, but the tensile stress in the channel will be maintained consistently. This tensile stress can increase the mobility of electrons, thereby increasing the current under the same leakage conditions.
[0036] However, not all NMOS devices require the tensile stress layer. A stress layer capable of providing tensile stress is formed on the surface of some NMOS devices, which may cause a negative effect of excessive leakage current on the NMOS devices, thereby affecting the performance of such NMOS devices.
[0037] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, wherein the first width of the first channel region at the bottom of the first gate structure is greater than the second width of the second channel region at the bottom of the second gate structure, an initial stress layer is first formed on the substrate surface, the top surface and sidewall surface of the first gate structure, and the top surface and sidewall surface of the second gate structure, and then the initial stress layer on the top surface and sidewall surface of the second gate structure and the surface of the second region is removed, and a stress layer is formed on the surface of the first region and the top surface and sidewall surface of the first gate structure. The stress layer only exists on the surface of the first region with a larger channel region width, and the top surface and sidewall surface of the first gate structure, so that stress can be selectively provided to the device on the first region where stress needs to be provided, avoiding the situation where the stress layer has a negative impact on the device on the second region where stress does not need to be provided, thereby optimizing the performance of the semiconductor structure.
[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0039] Figures 1 to 4 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.
[0040] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II.
[0041] In this embodiment, the substrate 100 is made of silicon.
[0042] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0043] Please continue to refer to Figure 1 A first gate structure 101 and first source-drain doped regions 103 located in the first region I on both sides of the first gate structure 101 are formed on the first region I, a first channel region (not shown) is provided in the substrate 100 at the bottom of the first gate structure 101, the first channel region is located between the first source-drain doped regions 103 on both sides of the first gate structure 101, the first channel region has a first width d1 in a direction parallel to the surface of the substrate 100, and the first width d1 is the width between the first source-drain doped regions 103.
[0044] Please continue to refer to Figure 1 A second gate structure 102 and second source-drain doped regions 104 in the second region II on both sides of the second gate structure 102 are formed on the second region II. A second channel region (not marked) is provided in the substrate 100 at the bottom of the second gate structure 102. The second channel region is located between the second source-drain doped regions 104 on both sides of the second gate structure 102. The second channel region has a second width d2 in a direction parallel to the surface of the substrate 100. The second width d2 is the width between the second source-drain doped regions 104. The first width d1 is greater than the second width d2.
[0045] In this embodiment, the first source-drain doping region 103 and the second source-drain doping region 104 have the same conductivity type.
[0046] In this embodiment, the conductivity type of the first source-drain doping region 103 and the second source-drain doping region 104 includes N type.
[0047] In another embodiment, the conductivity type of the first source-drain doping region and the second source-drain doping region includes P type.
[0048] In this embodiment, the first width d1 is in the range of greater than or equal to 1 micrometer.
[0049] In this embodiment, the second width d2 is in the range of less than 1 micrometer.
[0050] In this embodiment, the first gate structure 101 and the second gate structure 102 are formed simultaneously, and the first source-drain doped region 103 and the second source-drain doped region 104 are formed simultaneously.
[0051] The first gate structure 101 includes a first gate dielectric layer (not labeled) and a first gate layer (not labeled) located on the first gate dielectric layer; the second gate structure 102 includes a second gate dielectric layer (not labeled) and a second gate layer (not labeled) located on the second gate dielectric layer.
[0052] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include silicon oxide or low-K (K is less than 3.9) material; and the materials of the first gate layer and the second gate layer include polysilicon.
[0053] In another embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the first gate layer and the second gate layer includes a metal, and the metal includes tungsten.
[0054] Please refer to Figure 2 An initial stress layer 105 is formed on the surface of the substrate 100 , the top surface and sidewall surfaces of the first gate structure 101 , and the top surface and sidewall surfaces of the second gate structure 102 .
[0055] In this embodiment, the conductivity type of the first source-drain doping region 103 and the second source-drain doping region 104 includes N-type, and the initial stress layer 105 includes a tensile stress layer. The initial stress layer 105 is used to provide tensile stress for the NMOS device later.
[0056] In this embodiment, the material of the initial stress layer 105 includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
[0057] In this embodiment, the thickness of the initial stress layer 105 is less than 1000 angstroms.
[0058] The process of forming the initial stress layer 105 includes a deposition process, and the deposition process includes physical vapor deposition, chemical vapor deposition or atomic layer deposition.
[0059] In another embodiment, the conductivity type of the first source-drain doping region and the second source-drain doping region includes a P type, and the initial stress layer includes a compressive stress layer. The initial stress layer is used to provide compressive stress for the PMOS device later.
[0060] In another embodiment, the material of the initial stress layer includes silicon germanium.
[0061] Please refer to Figure 3, remove the initial stress layer 105 on the top surface and sidewall surfaces of the second gate structure 102 and the surface of the second region II, and form a stress layer 106 on the surface of the first region I and the top surface and sidewall surfaces of the first gate structure 101.
[0062] The method for removing the initial stress layer 105 on the top surface and sidewall surfaces of the second gate structure 102, and the surface of the second region II comprises: providing an initial layout, the initial layout comprising a first region and a second region corresponding to the substrate; obtaining an area of the second region on the initial layout; obtaining an exposure layout based on the area of the second region on the initial layout; forming a photoresist layer (not shown) on the initial stress layer 105; exposing and developing the photoresist layer based on a mask generated by the exposure layout, removing the photoresist layer on the second region, exposing the top surface and sidewall surfaces of the second gate structure 102, and the surface of the initial stress layer 105 on the surface of the second region II; removing the initial stress layer 105 exposed on the second region II, and forming a stress layer 106 on the surface of the first region I, and the top surface and sidewall surfaces of the first gate structure 101.
[0063] The process of removing the top surface and the sidewall surface of the second gate structure 102 and the initial stress layer 105 on the surface of the second region II includes: a wet etching process or a dry etching process.
[0064] Please continue to refer to Figure 3 , the stress layer 106 is annealed.
[0065] The stress layer 106 is annealed to generate tensile stress in the first channel region at the bottom of the first gate structure 101 to improve the mobility of electrons in the device on the first region I, thereby increasing the current under the same leakage condition.
[0066] The stress layer 106 only exists on the surface of the first region I with a larger channel width, and the top surface and sidewall surface of the first gate structure 101. Therefore, it can selectively provide tensile stress to the devices on the first region 1 that need to be provided with tensile stress, thereby avoiding the negative impact of the stress layer 106 on the devices on the second region II with a smaller channel width due to excessively large leakage current, thereby optimizing the performance of the semiconductor structure.
[0067] Please refer to Figure 4 After annealing the stress layer 106 , the stress layer 106 is removed.
[0068] After the stress layer 106 is removed, the tensile stress still exists in the first channel region at the bottom of the first gate structure 101 to improve the mobility of electrons in the device on the first region I, thereby increasing the current under the same leakage condition.
[0069] In this embodiment, the process of removing the stress layer 106 includes a wet etching process, and the wet etching process causes less damage to the surface of the substrate and the surface of the first gate structure 101 .
[0070] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 3 ,include:
[0071] A substrate 100, wherein the substrate 100 includes a first region I and a second region II;
[0072] A first gate structure 101 located on the first region I, wherein a first channel region is provided in the substrate 100 at the bottom of the first gate structure 101, and the first channel region has a first width d1 in a direction parallel to the surface of the substrate 100;
[0073] A second gate structure 102 located on the second region II, wherein a second channel region is provided in the substrate 100 at the bottom of the second gate structure 102, wherein the second channel region has a second width d2 in a direction parallel to the surface of the substrate 100, and the first width d1 is greater than the second width d2;
[0074] The stress layer 106 is located on the surface of the first region I, and the top surface and sidewall surface of the first gate structure 101 .
[0075] In this embodiment, it also includes: a first source-drain doped region 103 located in the first region I on both sides of the first gate structure 101, the first channel region is located between the first source-drain doped regions 103 on both sides of the first gate structure 101, and the first width d1 is the width between the first source-drain doped regions 103; a second source-drain doped region 104 located in the second region II on both sides of the second gate structure 102, the second channel region is located between the second source-drain doped regions 104 on both sides of the second gate structure 102, and the second width d2 is the width between the second source-drain doped regions 104.
[0076] In this embodiment, the first source-drain doping region 103 and the second source-drain doping region 104 have the same conductivity type.
[0077] In this embodiment, the conductivity type of the first source-drain doping region 103 and the second source-drain doping region 104 includes N type.
[0078] In this embodiment, the stress layer 106 includes a tensile stress layer; the material of the tensile stress layer includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
[0079] In another embodiment, the conductivity type of the first source-drain doped region and the second source-drain doped region includes P type; the stress layer includes a compressive stress layer; and the material of the compressive stress layer includes silicon germanium.
[0080] In this embodiment, the thickness of the stress layer 106 is less than 1000 angstroms.
[0081] In this embodiment, the first width d1 is in the range of greater than or equal to 1 micrometer.
[0082] In this embodiment, the second width d2 is in the range of less than 1 micrometer.
[0083] In another embodiment, the substrate also includes a third region; the semiconductor structure also includes: a third gate structure located on the third region and a third source-drain doped region located in the third region on both sides of the third gate structure, and the third source-drain doped region has a conductivity type opposite to that of the first source-drain doped region and the second source-drain doped region.
[0084] In another embodiment, the conductivity type of the third source-drain doping region includes P type or N type.
[0085] In another embodiment, the third gate structure is formed simultaneously with the first gate structure and the second gate structure; the initial stress layer is also located on the top surface and side wall surface of the third gate structure; while removing the initial stress layer on the top surface and side wall surface of the second gate structure and the surface of the second region, the top surface and side wall surface of the third gate structure and the initial stress layer on the surface of the third region are also removed.
[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; Forming a first gate structure on the first region, wherein a first channel region is provided in the substrate at the bottom of the first gate structure, and the first channel region has a first width in a direction parallel to the surface of the substrate; forming a second gate structure on the second region, wherein a second channel region is provided in the substrate at the bottom of the second gate structure, wherein the second channel region has a second width in a direction parallel to the surface of the substrate, and the first width is greater than the second width; forming an initial stress layer on the substrate surface, the top surface and sidewall surfaces of the first gate structure, and the top surface and sidewall surfaces of the second gate structure; The initial stress layer on the top surface and sidewall surfaces of the second gate structure and the surface of the second region is removed, and a stress layer is formed on the surface of the first region and the top surface and sidewall surfaces of the first gate structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the initial stress layer, it also includes: forming a first source-drain doped region in the first area on both sides of the first gate structure, the first channel area is located between the first source-drain doped regions on both sides of the first gate structure, and the first width is the width between the first source-drain doped regions; forming a second source-drain doped region in the second area on both sides of the second gate structure, the second channel area is located between the second source-drain doped regions on both sides of the second gate structure, and the second width is the width between the second source-drain doped regions.
3. The method for forming a semiconductor structure according to claim 2, wherein: The first source-drain doping region and the second source-drain doping region have the same conductivity type.
4. The method for forming a semiconductor structure according to claim 3, wherein: The conductivity types of the first source-drain doping region and the second source-drain doping region include N type.
5. The method for forming a semiconductor structure according to claim 4, wherein: The stress layer includes a tensile stress layer; the material of the tensile stress layer includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
6. The method for forming a semiconductor structure according to claim 3, wherein: The conductivity types of the first source-drain doping region and the second source-drain doping region include P type.
7. The method for forming a semiconductor structure according to claim 6, wherein: The stress layer includes a compressive stress layer; the material of the compressive stress layer includes silicon germanium.
8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the stress layer is less than 1000 angstroms.
9. The method for forming a semiconductor structure according to claim 1, wherein: The range of the first width is: greater than or equal to 1 micron.
10. The method for forming a semiconductor structure according to claim 1, wherein: The second width is in the range of less than 1 micron.
11. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the initial stress layer on the top surface and sidewall surface of the second gate structure and the surface of the second region comprises: providing an initial layout, the initial layout comprising a first region and a second region corresponding to the substrate; obtaining an area of the second region on the initial layout; obtaining an exposure layout based on the area of the second region on the initial layout; forming a photoresist layer on the initial stress layer; exposing and developing the photoresist layer based on a mask generated by the exposure layout, removing the photoresist layer on the second region, exposing the top surface and sidewall surface of the second gate structure and the surface of the initial stress layer on the surface of the second region; removing the initial stress layer exposed on the second region, and forming a stress layer on the surface of the first region, and the top surface and sidewall surface of the first gate structure.
12. The method for forming a semiconductor structure according to claim 3, wherein: The substrate also includes a third region; further including: forming a third gate structure located on the third region and forming third source-drain doped regions located in the third region on both sides of the third gate structure, wherein the third source-drain doped regions have a conductivity type opposite to that of the first source-drain doped regions and the second source-drain doped regions, and the initial stress layer is also located on the top surface and side wall surface of the third gate structure; while removing the initial stress layer on the top surface and side wall surface of the second gate structure and the surface of the second region, the top surface and side wall surface of the third gate structure and the initial stress layer on the surface of the third region are also removed.
13. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the top surface and the sidewall surface of the second gate structure and the initial stress layer on the surface of the second region includes: a wet etching process or a dry etching process.
14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: performing annealing treatment on the stress layer; After the stress layer is annealed, the stress layer is removed.
15. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A first gate structure located on the first region, wherein a first channel region is provided in the substrate at the bottom of the first gate structure, and the first channel region has a first width in a direction parallel to the surface of the substrate; A second gate structure located on the second region, wherein a second channel region is provided in the substrate at the bottom of the second gate structure, wherein the second channel region has a second width in a direction parallel to the surface of the substrate, and the first width is greater than the second width; A stress layer is located on the surface of the first region, and the top surface and sidewall surface of the first gate structure.
16. The semiconductor structure according to claim 15, wherein: It also includes: a first source-drain doped region in the first area on both sides of the first gate structure, the first channel region is located between the first source-drain doped regions on both sides of the first gate structure, and the first width is the width between the first source-drain doped regions; a second source-drain doped region in the second area on both sides of the second gate structure, the second channel region is located between the second source-drain doped regions on both sides of the second gate structure, and the second width is the width between the second source-drain doped regions.
17. The semiconductor structure according to claim 16, wherein: The first source-drain doping region and the second source-drain doping region have the same conductivity type.
18. The semiconductor structure according to claim 17, wherein: The conductivity types of the first source-drain doping region and the second source-drain doping region include N type.
19. The semiconductor structure according to claim 18, wherein: The stress layer includes a tensile stress layer; the material of the stress layer includes nitrogen-containing silicide, and the nitrogen-containing silicide includes silicon nitride or silicon nitride oxide.
20. The semiconductor structure according to claim 17, wherein: The conductivity types of the first source-drain doping region and the second source-drain doping region include P type.
21. The semiconductor structure according to claim 20, wherein: The stress layer includes a compressive stress layer; The material of the compressive stress layer includes silicon germanium.
22. The semiconductor structure according to claim 15, wherein: The thickness of the stress layer is less than 1000 angstroms.
23. The semiconductor structure according to claim 15, wherein: The range of the first width is: greater than or equal to 1 micron.
24. The semiconductor structure according to claim 15, wherein: The second width is in the range of less than 1 micron.
25. The semiconductor structure according to claim 15, wherein: The substrate also includes a third region; and further includes: a third gate structure located on the third region and third source-drain doped regions located in the third region on both sides of the third gate structure, wherein the third source-drain doped regions have a conductivity type opposite to that of the first source-drain doped regions and the second source-drain doped regions.