Trench gate silicon carbide VDMOS with high switching speed and preparation method thereof

Abstract

The invention provides a trench gate silicon carbide VDMOS with high switching speed and a preparation method thereof. The method comprises the following steps: forming a barrier layer on a drain metal layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; removing the barrier layer, and depositing to form a silicon carbide substrate above the drain metal layer and the insulating layer; performing epitaxial growth on the silicon carbide substrate to form a drift layer; performing ion implantation, forming an N-type region in the drift layer, forming a barrier layer on the drift layer, performing etching, performing ion implantation, forming a P-type well region in the N-type region, re-forming the barrier layer, performing etching, performing ion implantation, forming an N-type source region in the N-type region and the P-type well region, re-forming the barrier layer, performing etching to form a second groove, and performing oxidation to form a gate dielectric layer, a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. The switching speed of the device is improved and the switching loss of the device is reduced.

Description

Technical Field

[0001] The invention relates to a high-switching-speed trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different emphases, but the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, etc.), and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method for preparing a trench gate silicon carbide VDMOS with a high switching speed, thereby improving the switching speed of the device and reducing the switching loss of the device. At the same time, the body diode conduction loss of the device can be reduced and the reverse recovery speed of the device can be improved.

[0004] In a first aspect, the present invention is implemented as follows: a method for preparing a high switching speed trench gate silicon carbide VDMOS comprises the following steps:

[0005] Step 1, forming a barrier layer on the drain metal layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer;

[0006] Step 2, removing the barrier layer, and depositing a silicon carbide substrate on the drain metal layer and the insulating layer;

[0007] Step 3, epitaxially growing a drift layer on a silicon carbide substrate;

[0008] Step 4: ion implantation to form an N-type region in the drift layer, with an ion implantation energy of 100-270kev;

[0009] Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region in the N-type region;

[0010] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form an N-type source region in the N-type region and the P-type well region;

[0011] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the N-type region and the drift layer to form a second groove, oxidize to form a gate dielectric layer, and the gate dielectric layer is provided with a groove;

[0012] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0013] Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer until the upper side of the N-type source region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention is implemented as follows: a trench gate silicon carbide VDMOS with high switching speed, wherein the silicon carbide VDMOS is prepared by the preparation method of the first aspect.

[0015] The advantages of the present invention are:

[0016] 1. The present invention increases the thickness of the bottom of the gate dielectric layer from the traditional 50nm to 100nm on the basis of the trench gate structure, so that the P-type shielding layer is no longer used to protect the device structure, eliminating the influence of the P-type shielding layer on the on-resistance of the device;

[0017] Second, the device gate-controlled conductive channel is not included at the bottom of the gate dielectric, so the structural change does not affect the gate control capability of the device;

[0018] 3. An N-type silicon carbide material with a high middle and low sides is constructed above the device drain metal. This structure effectively reduces the distance from the device gate to the drain, which can effectively suppress the device gate-drain capacitance, namely the Maitreya capacitance, and can reduce the platform period of device opening and closing, effectively improving the switching speed of the device;

[0019] Fourth, a Schottky body diode is constructed from the source metal to the N-type region inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and increase the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 The schematic diagram of a high switching speed trench gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0023] Figure 3 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0024] Figure 4A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0025] Figure 5 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0026] Figure 6 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0027] Figure 7 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0028] Figure 8 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0029] Fig. 9 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0030] Fig.10 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0031] Fig.11 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0032] Fig.12 A cross-sectional view of the process of a high switching speed trench gate silicon carbide VDMOS of the present invention Figure 10 one.

[0033] Fig.13 The figure is a schematic diagram of an insulating layer of a high switching speed trench gate silicon carbide VDMOS according to the present invention. DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS with a high switching speed, comprising the following steps:

[0040] Step 1, forming a barrier layer a on the drain metal layer 9, etching the barrier layer a to form a through hole, and depositing to form an insulating layer 121;

[0041] Step 2, removing the barrier layer a, and depositing a silicon carbide substrate 1 on the drain metal layer 9 and the insulating layer 121;

[0042] Step 3, epitaxially growing a drift layer 2 on the silicon carbide substrate 1; since the insulating layer 121 is nanometer-level, and the drift layer 2 is micrometer-level, the thickness of the drift layer 2 is more than ten times the thickness of the insulating layer 121, so during the epitaxial growth process, the upper surface of the drift layer 2 tends to be flat as the epitaxial growth progresses, and no additional treatment is required;

[0043] Step 4: ion implantation to form an N-type region 5 in the drift layer 2, with an ion implantation energy of 100-270kev;

[0044] Step 4: forming a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation to form a P-type well region 3 in the N-type region 5, wherein the ion implantation energy is 170-270kev;

[0045] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation to form an N-type source region 4 in the N-type region 5 and the P-type well region 3, with the ion implantation energy being 100-200 keV;

[0046] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the N-type region 5 and the drift layer 2 to form a second groove 21, and oxidizing to form a gate dielectric layer 6, wherein the gate dielectric layer 6 is provided with a groove 61;

[0047] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 7;

[0048] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 2 until the upper side of the N-type source region 4, deposit metal to form a source metal layer 8, remove the barrier layer a, and complete the preparation.

[0049] In this embodiment, preferably, Fig.13 As shown, the step 1 is specifically as follows:

[0050] Step 11, forming a barrier layer a on the drain metal layer 9, etching the barrier layer a to form a through hole, and depositing a first layer of insulating material;

[0051] Step 12, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and deposit a second layer of insulating material; perform step 12 at least once to finally form an insulating layer 121, which can be trapezoidal or stepped.

[0052] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0053] A silicon carbide substrate 1, wherein a protrusion 11 is provided on the silicon carbide substrate 1, a first groove 12 is provided on the silicon carbide substrate 1, and an insulating layer 121 is provided in the first groove 12; the protrusion 11 is trapezoidal or step-shaped; the insulating layer 121 is trapezoidal or step-shaped;

[0054] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a second groove 21 is provided on the drift layer 2;

[0055] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2;

[0056] An N-type source region 4 connected to the P-type well region 3;

[0057] N-type region 5, wherein the N-type region 5 is respectively connected to the upper side of the drift layer 2, the outer side of the N-type source region 4 and the P-type well region 3;

[0058] A gate dielectric layer 6, wherein the lower portion of the gate dielectric layer 6 is disposed in the second groove 21, and the outer side surface of the gate dielectric layer 6 is respectively connected to the inner side surface of the N-type source region 4 and the inner side surface of the P-type well region 3; a groove 61 is disposed in the gate dielectric layer 6;

[0059] A gate metal layer 7, wherein the gate metal layer 7 is disposed in the groove 61;

[0060] A source metal layer 8, wherein the source metal layer 8 is respectively connected to the N-type source region 4 and the N-type region 5;

[0061] And, a drain metal layer 9 , wherein the drain metal layer 9 is respectively connected to the silicon carbide substrate 1 and the insulating layer 121 .

[0062] The thickness of the bottom of the gate dielectric layer 6 is 100 nm, the doping concentration of the N-type region 5 is less than the doping concentration of the P-type well region 3, and the doping concentration of the P-type well region 3 is less than the doping concentration of the N-type source region 4; the depth of the second groove 21 is equal to the thickness from the upper side of the groove 61 of the gate dielectric layer 61 to the bottom of the gate dielectric layer 6, the width of the upper side of the insulating layer 121 is greater than the width of the gate dielectric layer 6, and the P-type well region 3 is L-shaped.

[0063] In another embodiment of the present invention, the insulating layer 121 is silicon dioxide, and the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 , the silicon carbide substrate 1 is N-type; the doping concentration of the drift layer 2 is 1e16cm -3 , the drift layer 2 is N-type; the doping concentration of the N-type region 5 is 1e17cm -3 , the doping concentration of P-type well region 3 is 5e17 cm -3 The gate dielectric layer 6 can be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide. The doping concentration of the N-type source region 4 is 2e18cm -3 ;

[0064] The insulating layer 121 is silicon dioxide, which is to improve process compatibility and ensure the reliability of depositing N-type silicon carbide material on the insulating material. The insulating layer 121 is set to form a set shape of the silicon carbide substrate 1 and prevent the high voltage of the drain from easily impacting the gate structure of the device; the concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 9, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the N-type region 5 is to reduce the on-resistance of the device, and at the same time form a Schottky metal instead of an ohmic contact with the source metal layer 8 to form a Schottky body diode inside the device; the P-type well region 3 is to control the turn-off characteristics of the device without affecting the gate control capability and the Schottky diode freewheeling capability of the device.

[0065] The thickness of the N-type silicon carbide substrate 1 of the present invention is 1 μm, which is to ensure the support of the subsequent structure preparation of the device. The thickness of the N-type drift layer 2 is 15-25 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type region 5 above the P-type well region 3 is 200 nm, and the thickness on the edge side of the P-type well region 5 is 500 nm. The width of the N-type source region 4 is 500 nm. The lateral width of the device N-type region 5 to the P-type well region 3 is related to the doping concentration of the P-type well region 3 and the N-type region 5 to ensure that the region can be turned off when the device is reversely withstand voltage; the bottom thickness of the gate dielectric layer 6 is 100 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the gate corner. The side thickness of the gate dielectric layer 6 is 50 nm, the thickness of the N-type source region 4 is 300 nm, the thickness of the P-type well region 3 in the contact area with the N-type source region 4 is 200 nm, and the thickness of the contact part with the N-type region 5 is 300 nm;

[0066] The N-type region 5 of the device is connected to the source metal layer 8, forming a Schottky diode between the source metal and the N-type region 5, which can effectively reduce the body diode conduction voltage drop of the device. The cathode distribution position of the Schottky diode of the device is the same as that of the pn junction cathode, but the reverse recovery of the Schottky diode is faster and the conduction voltage drop is lower, so in general, the device has a fast recovery characteristic;

[0067] The device adopts a trench gate structure and the thickness of the insulating dielectric at the bottom of the device is increased from the traditional 50nm to 100nm, so that it is not necessary to set a P-type shielding layer at the bottom of the gate dielectric layer 6 to protect the device structure, eliminating the influence of the P-type shielding layer on the on-resistance of the device. The bottom of the gate dielectric layer 6 does not contain a device gate-controlled conductive channel, so the structural change does not affect the gate control capability of the device;

[0068] An N-type silicon carbide substrate 1 with a high middle and low sides is constructed above the device drain metal layer 9. This structure effectively reduces the distance from the device gate to the drain, can effectively suppress the device gate-drain capacitance, namely the Maitreya capacitance, can reduce the platform period of device turn-on and turn-off, and effectively improve the switching speed of the device. A Schottky body diode is constructed from the source metal to the N-type region inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and improve the switching speed of the device.

[0069] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high switching speed trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1, forming a barrier layer on the drain metal layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; Step 2, removing the barrier layer, and depositing a silicon carbide substrate on the drain metal layer and the insulating layer; Step 3, epitaxially growing a drift layer on a silicon carbide substrate; Step 4: Ion implantation to form an N-type region in the drift layer; Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region in the N-type region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form an N-type source region in the N-type region and the P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the N-type region and the drift layer to form a second groove, oxidize to form a gate dielectric layer, and the gate dielectric layer is provided with a groove; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer until the upper side of the N-type source region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The step 1 is specifically as follows: Step 11, forming a barrier layer on the drain metal layer, etching the barrier layer to form a through hole, and depositing a first layer of insulating material; Step 12, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing a second layer of insulating material; performing step 12 at least once to finally form an insulating layer.

3. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The depth of the second groove is equal to the thickness from the upper side of the gate dielectric layer trench to the bottom of the gate dielectric layer.

4. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating layer is 300-600nm.

5. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the upper side surface of the insulating layer is greater than the width of the gate dielectric layer.

6. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The P-type well region is L-type.

7. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the bottom of the gate dielectric layer is 100 nm.

8. The method for preparing a high switching speed trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the N-type region is lower than the doping concentration of the P-type well region, and the doping concentration of the P-type well region is lower than the doping concentration of the N-type source region.

9. A high switching speed trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 8.

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