Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a first shallow trench isolation structure in the substrate; a drift region is formed in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is larger than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to the surface of a part of the first shallow trench isolation structure in the first drift region; the broadening of a depletion region is increased, an electric field is distributed as uniformly as possible, and the difficulty of avalanche breakdown is improved, so that the breakdown voltage is greatly improved, the quality of the semiconductor structure is improved, and the application range is relatively wide.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Laterally diffused metal oxide semiconductor (LDMOS) is a high-voltage semiconductor device widely used in radio frequency base stations, plasma display panels (PDP) display drivers, power management, and automotive electronics. Compared with traditional insulated gate bipolar transistors (IGBTs), it has higher response speed and lower leakage current, and as a planar device, it has greater advantages in process integration. Adding a shallow trench isolation (STI) region to the drift region of a traditional LDMOS device can effectively increase the breakdown voltage of the high-voltage device and improve the on-resistance of the device. STI-type LDMOS devices have been widely used. Because in most applications, the drain end often needs to be connected to a high voltage, the influence of the hot carrier effect is very prominent. In the field of device reliability, the density and position information of interface traps play an important role in the reliability of the device.

[0003] Drain to Source Breakdown Voltage (BVDS) is an important parameter of LDMOS and an important aspect of LDMOS device reliability. Although LDMOS has a lower doped drift region, which makes it have a higher breakdown voltage than other MOS devices, with the development of society's demand for high voltage and high power, it is necessary to increase the breakdown voltage of LDMOS devices.

[0004] Adding STI to the drift region of a traditional LDMOS device can effectively increase the breakdown voltage of the LDMOS device, so STI-type LDMOS devices are widely used. However, power LDMOS devices are constrained by the "silicon limit". While improving the LDMOS device, the on-resistance will also increase. When using STI-type LDMOS devices to increase the breakdown voltage, the on-resistance of the LDMOS device will increase significantly.

[0005] The performance of current LDMOS devices needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the performance of the semiconductor structure.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, and one side and a part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to a part of the surface of the first shallow trench isolation structure in the first drift region.

[0008] Optionally, the ion type in the first drift region is the same as the ion type in the second drift region, the width of the first drift region in a first direction is greater than the width of the second drift region in the first direction, and the first direction is parallel to the channel direction.

[0009] Optionally, a width of the first shallow trench isolation structure in the second drift region is smaller than a width of the first shallow trench isolation structure in the first drift region, and a direction of the width is parallel to a channel direction.

[0010] Optionally, a ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, and a direction of the width is parallel to a channel direction.

[0011] Optionally, the method for forming the drift region includes: forming a first mask layer on the surface of the substrate, the first mask layer having a first mask layer opening, the bottom of the first mask layer opening exposing a portion of the top surface of the first shallow trench isolation structure and a portion of the surface of the substrate on one side of the first shallow trench isolation structure; performing a first ion implantation on the exposed surface of the substrate and the exposed bottom of the first shallow trench isolation structure to form the first drift region; removing the first mask layer; forming a second mask layer on the surface of the substrate, the second mask layer having a second mask layer opening, the bottom of the second mask layer opening exposing the top surface of the first shallow trench isolation structure outside the first drift region and a portion of the surface of the substrate located on one side of the first shallow trench isolation structure and adjacent to the first drift region; performing a second ion implantation on the exposed surface of the substrate and the substrate at the bottom of the first shallow trench isolation structure to form the second drift region, the first drift region and the second drift region constituting the drift region, the first drift region and the second drift region being adjacent to each other, and the first shallow trench isolation structure being located in the drift region.

[0012] Optionally, the process parameters of the first ion implantation include that the element implanted is phosphorus, and the doping dose of the ion implantation is about 4E12atom / cm 2 -5E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

[0013] Optionally, the process parameters of the second ion implantation include that the element implanted is phosphorus, and the doping dose of the ion implantation is about 2E12atom / cm 2 -3E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

[0014] Optionally, after forming the gate structure, the method further includes: forming a body doping region in the substrate on one side of the gate structure, wherein the body doping region and the first drift region are located on both sides of the second drift region.

[0015] Optionally, the ion type in the drift region is opposite to the ion type in the body doping region.

[0016] Optionally, the method further includes: forming a first source-drain doping region in the drift region and the body doping region on both sides of the gate structure; and forming a second source-drain doping region in the body doping region between adjacent first source-drain doping regions.

[0017] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a first shallow trench isolation structure located in the substrate; a drift region located in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; a gate structure located on the surface of the substrate, the gate structure covers the surface of the second drift region and extends to a portion of the surface of the first shallow trench isolation structure in the first drift region.

[0018] Optionally, a width of the first drift region in a first direction is greater than a width of the second drift region in the first direction, and the first direction is parallel to the channel direction.

[0019] Optionally, the width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region, and the ratio of the width of the first shallow trench isolation structure in the second drift region to the width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, and the direction of the width is parallel to the channel direction.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the method for forming a semiconductor structure of the present invention, a substrate is provided, a first shallow trench isolation structure is formed in the substrate, a drift region is formed in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, a side wall and a part of the bottom of the shallow first trench isolation structure are located in the second drift region, a gate structure is formed on the surface of the substrate in the partial drift region, the gate structure covers the second drift region and extends to the surface of the part of the first shallow isolation trench structure in the first drift region; a means of reducing the concentration of injected ions in the second drift region is adopted to reduce the withstand voltage of the contact area between the first shallow trench isolation structure at the bottom of the gate structure and the second drift region, thereby increasing the width of the depletion region, allowing the electric field to be distributed as evenly as possible, and increasing the difficulty of avalanche breakdown, thereby greatly increasing the breakdown voltage, improving the quality of the semiconductor structure, and having a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a cross-sectional view of a semiconductor structure in one embodiment;

[0023] Figure 2 is an electric field distribution of a semiconductor structure in one embodiment;

[0024] Figures 3 to 9 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0025] Fig.10 FIG. 4 is an electric field distribution diagram of a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] As the background technology, the performance of existing semiconductor structures is poor. Figure 1 and Figure 2 Provide detailed explanation.

[0027] Please refer to Figure 1 The semiconductor structure includes a substrate 100; a shallow trench isolation structure 101 located in the substrate 100; a drift region 102 located in the substrate 100, wherein at least one shallow trench isolation structure 101 is located in the drift region 102 and the drift region 102 also extends to a portion of the bottom of an adjacent shallow trench isolation structure; a body doping region 104 is formed in the substrate 100; a gate structure 103 is formed on the substrate 100, wherein the gate structure 103 is located on the top surface of the shallow trench isolation structure in the partial drift region and the gate structure 103 is also located on the surface of the substrate 100 between the body doping region 104 and the drift region 102; the substrate 100 on both sides of the gate structure 103 is doped to form a source-drain doping region 105.

[0028] The inventors found that in this semiconductor structure, the contact area between the shallow trench isolation structure at the bottom of the gate structure and the drift region is an area of ​​concentrated electric field (dashed circle in the figure), which is prone to collision ionization, thereby causing avalanche breakdown, reducing the quality of the semiconductor structure. Figure 2 The breakdown voltage BV is 55V and Rsp is 37.

[0029] The inventors have found through research that a substrate is provided, a first shallow trench isolation structure is formed in the substrate, a drift region is formed in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, a side wall and a part of the bottom of the shallow first trench isolation structure are located in the second drift region, a gate structure is formed on the surface of the substrate in the part of the drift region, the gate structure covers the second drift region and extends to the surface of the part of the first shallow isolation trench structure in the first drift region; the concentration of injected ions in the second drift region is reduced, the withstand voltage of the contact area between the first shallow trench isolation structure at the bottom of the gate structure and the second drift region is reduced, the width of the depletion region is increased, the electric field is distributed as evenly as possible, and the difficulty of avalanche breakdown is increased, thereby greatly improving the breakdown voltage, improving the quality of the semiconductor structure, and having a wider range of applications.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Figures 3 to 9 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0032] Please refer to Figure 3 , providing a substrate 200.

[0033] In this embodiment, the material of the substrate 200 is silicon.

[0034] In other embodiments, the material of the substrate 200 also includes semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, and gallium arsenide.

[0035] In this embodiment, the substrate 200 is a P-type substrate 200 .

[0036] Please continue to refer to Figure 3 , etching the substrate 200 to form a first shallow trench 201 in the substrate 200 .

[0037] In this embodiment, during the etching process of the substrate 200, in addition to forming the first shallow trench 201, a plurality of shallow trenches are formed. Figure 3 For example, a second shallow trench 202 is further formed in the substrate 200 .

[0038] In this embodiment, the formation of two shallow trenches is shown.

[0039] Please refer to Figure 4 , an isolation layer is filled in the first shallow trench 201 to form a first shallow trench isolation structure 203.

[0040] In this embodiment, the second shallow trench 202 is filled while the first shallow trench 201 is filled, and a second shallow trench isolation structure 204 is formed in the second shallow trench 202 .

[0041] In this embodiment, the method for forming the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204 includes forming an isolation structure film (not shown) on the substrate 200; and etching back the isolation structure film to form the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204.

[0042] The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by the fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.

[0043] In this embodiment, the material of the isolation layer includes silicon oxide.

[0044] In this embodiment, after the shallow trench is fully filled with the isolation layer, the isolation layer is planarized until its surface is flush with the surface of the substrate 200 .

[0045] For the process of forming the drift region in the substrate 200, please refer to Figures 5 and 6 .

[0046] Please refer to Figure 5 A first mask layer (not shown in the figure) is formed on the surface of the substrate 200, and a first mask layer opening (not shown in the figure) is provided in the first mask layer. The bottom of the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure 203 and a portion of the surface of the substrate 200 on one side of the first shallow trench isolation structure 203.

[0047] Specifically, the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure 203, a portion of the top surface of the second shallow trench isolation structure 204, and the surface of the substrate 200 between the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204, and the size of the first shallow trench isolation structure 203 exposed by the first mask layer opening is larger than the size of the second shallow trench isolation structure 204 exposed by the first mask layer opening.

[0048] In this embodiment, a first ion implantation is performed on the exposed surface of the substrate 200 and the exposed bottom of the first shallow trench isolation structure 203 of the substrate 200 to form the first drift region 205 .

[0049] In this embodiment, after the first drift region 205 is formed, the first mask layer is removed.

[0050] In this embodiment, the material of the first mask layer is photoresist.

[0051] In other embodiments, the material of the first mask layer may also be a hard mask layer such as silicon oxide, silicon nitride, etc.

[0052] In this embodiment, the ion type of the first ion implantation is N-type ions.

[0053] In other embodiments, the ion type of the first ion implantation may also be P-type ions.

[0054] In this embodiment, the process parameters of the first ion implantation include that the implanted element is phosphorus, the doping dose of the ion implantation is about 4E12atom / cm2-5E12atom / cm2, and the energy of the ion implantation is about 100Kev-200Kev.

[0055] In this embodiment, the process of removing the first mask layer is an ashing process.

[0056] In other embodiments, the process of removing the first mask layer may be a wet etching process.

[0057] Please refer to Figure 6 A second mask layer (not shown in the figure) is formed on the surface of the substrate 200, and a second mask layer opening (not shown in the figure) is provided in the second mask layer. The bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure 203 outside the first drift region 205 and a portion of the surface of the substrate 200 located on one side of the first shallow trench isolation structure 203 and adjacent to the first drift region 205.

[0058] In this embodiment, the material of the second mask layer is photoresist.

[0059] In this embodiment, a second ion implantation is performed on the exposed surface of the substrate 200 and the substrate 200 at the bottom of the first shallow trench isolation structure 203 to form the second drift region 206, the first drift region 205 and the second drift region 206 constitute the drift region, the first drift region 205 and the second drift region 206 are adjacent to each other, and the first shallow trench isolation structure 203 is located in the drift region.

[0060] In this embodiment, the ion type of the second ion implantation is N-type.

[0061] In other embodiments, the ion type of the second ion implantation may also be P type.

[0062] In this embodiment, the ion type of the first ion implantation is the same as the ion type of the second ion implantation.

[0063] In this embodiment, the width (a2) of the first shallow trench isolation structure 203 in the second drift region 206 in the first direction is smaller than the width (a1) of the first shallow trench isolation structure 203 in the first drift region 205 in the first direction. The purpose of this design is to alleviate the density of the potential lines at the junction of the right side of the first shallow trench isolation structure 203 and the gate and at the lower right corner of the first shallow trench isolation structure 203, thereby alleviating the peak electric field strength at these positions and improving the breakdown voltage of the device.

[0064] In this embodiment, the ratio of the width (a2) of the first shallow trench isolation structure 203 in the second drift region 206 in the first direction to the width (a1) of the first shallow trench isolation structure 203 in the first drift region 205 in the first direction is in the range of 0.2:1-0.4:1, and the first direction is parallel to the channel direction.

[0065] In this embodiment, the process parameters of the second ion implantation include that the element implanted is phosphorus, and the doping dose of the ion implantation is about 2E12atom / cm 2 -3E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

[0066] In this embodiment, the ion concentration of the first drift region 205 is greater than the ion concentration of the second drift region 206 .

[0067] Please refer to Figure 7 , a gate structure 207 is formed on the substrate 200 , wherein the gate structure 207 covers a surface of the second drift region 206 and extends to a surface of a portion of the first shallow trench isolation structure 203 in the first drift region 205 .

[0068] In this embodiment, the ion concentration in the second drift region 206 is smaller than the ion concentration in the first drift region 205, so as to reduce the withstand voltage of the contact area between the shallow trench isolation structure at the bottom of the gate structure 207 and the second drift region 206, increase the width of the depletion region, make the electric field as evenly distributed as possible, and increase the difficulty of avalanche breakdown, thereby greatly improving the breakdown voltage and enhancing the quality of the semiconductor structure, which has a wider range of applications.

[0069] In this embodiment, the gate structure 207 includes a gate oxide layer 207 b formed on the surface of the substrate 200 and a gate layer 207 a formed on the surface of the gate oxide layer 207 b , and the material of the gate layer 207 a is polysilicon.

[0070] In an embodiment, a spacer 207 c is further formed on the sidewall of the gate structure 207 .

[0071] Please refer to Figure 8 A body doping region 208 is formed in the substrate 200 on one side of the gate structure 207 , and the body doping region 208 and the first drift region 205 are located on both sides of the second drift region 206 .

[0072] In this embodiment, the type of ions doped in the body doping region 208 is opposite to the type of ions doped in the drift region.

[0073] In this embodiment, the ion type in the drift region is N-type, and the ion type in the body doping region 208 is P-type.

[0074] In this embodiment, the drift region and the body doping region 208 have the same doping depth.

[0075] Please refer to Fig. 9 , further comprising: forming a first source-drain doping region 209 in the drift region and the body doping region 208 on both sides of the gate structure 207; and forming a second source-drain doping region 210 in the body doping region 208 between adjacent first source-drain doping regions 209.

[0076] In this embodiment, the type of ions in the first source-drain doping region 209 is the same as the type of ions in the first drift region 205 .

[0077] In this embodiment, the ion type in the second source / drain doping region 210 is opposite to the ion type in the first source / drain doping region 209 .

[0078] In this embodiment, please refer to Fig.10 After applying an electric field to the semiconductor structure formed by the above method, its breakdown voltage BV is 69V and Rsp is 39, which greatly improves the difficulty of avalanche breakdown of the semiconductor structure. When Rsp changes very little, the BVDS of LDMOS is greatly improved; the depletion region of LDMOS is greatly widened by the optimized IMP injection, and the electric field distribution is more even; the optimized electric field is more conducive to the device reliability of LDMOS, and no new process steps are introduced, but the original drift region formation mask is split into two masks for separate injection, so the cost does not change much and has a wider range of applications.

[0079] Rsp means specific on-resistance, which relates resistance to area. It is a normalized quantity used to eliminate the impact of different area differences of resistors on performance. It represents the relationship between resistance and area in the on state. Its unit is mohm*mm 2 .

[0080] Please refer to Fig. 9The present invention also provides a semiconductor structure, comprising: a substrate 200; a first shallow trench isolation structure 203 located in the substrate 200; a drift region located in the substrate 200, wherein the first shallow trench isolation structure 203 is located in the drift region, wherein the drift region comprises a first drift region 205 and a second drift region 206 adjacent to the first drift region 205, wherein the ion concentration in the first drift region 205 is greater than the ion concentration in the second drift region 206, and one side and a part of the bottom of the first shallow trench isolation structure 203 are located in the second drift region 206; and a gate structure 207 located on the surface of the substrate 200, wherein the gate structure 207 covers the surface of the second drift region 206 and extends to a part of the surface of the first shallow trench isolation structure 203 in the first drift region 205.

[0081] In this embodiment, the width of the first drift region 205 in a first direction is greater than the width of the second drift region 206 in the first direction, and the first direction is parallel to the channel direction.

[0082] In this embodiment, the width of the first shallow trench isolation structure 203 in the second drift region 206 in the first direction is smaller than the width of the first shallow trench isolation structure 203 in the first drift region 205 in the first direction.

[0083] In this embodiment, the ratio of the width of the first shallow trench isolation structure 203 in the second drift region 206 in the first direction to the width of the first shallow trench isolation structure 203 in the first drift region 205 in the first direction is in the range of 0.2:1-0.4:1, and the first direction is parallel to the channel direction.

[0084] In this embodiment, it further includes: a sidewall spacer located on the sidewall of the gate structure 207 .

[0085] In this embodiment, it further includes: a body doping region 208 located in the substrate 200 on one side of the gate structure 207 , and the body doping region 208 and the first drift region 205 are located on both sides of the second drift region 206 .

[0086] In this embodiment, the type of ions doped in the body doping region 208 is opposite to the type of ions doped in the drift region.

[0087] In this embodiment, the ion type in the drift region is N-type, and the ion type in the body doping region 208 is P-type.

[0088] In this embodiment, the drift region and the body doping region 208 have the same doping depth.

[0089] In this embodiment, it also includes: a first source-drain doping region 209 located in the drift region and the body doping region 208 on both sides of the gate structure 207 ; and a second source-drain doping region 210 located between adjacent first source-drain doping regions 209 and in the body doping region 208 .

[0090] In this embodiment, the type of ion doping in the first source / drain doping region 209 is opposite to the type of ion doping in the second source / drain doping region 210 .

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first shallow trench isolation structure in the substrate; A drift region is formed in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, and one side and a part of the bottom of the first shallow trench isolation structure are located in the second drift region; A gate structure is formed on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to a surface of a portion of the first shallow trench isolation structure in the first drift region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The ion type in the first drift region is the same as the ion type in the second drift region, the width of the first drift region in a first direction is greater than the width of the second drift region in the first direction, and the first direction is parallel to the channel direction.

3. The method for forming a semiconductor structure according to claim 1, wherein: The width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region, and a direction of the width is parallel to a channel direction.

4. The method for forming a semiconductor structure according to claim 1, wherein: A ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, and a direction of the width is parallel to a channel direction.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the drift region comprises: forming a first mask layer on the surface of the substrate, wherein the first mask layer has a first mask layer opening, and the bottom of the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure and a portion of the surface of the substrate on one side of the first shallow trench isolation structure; Performing a first ion implantation on the exposed surface of the substrate and the exposed bottom of the first shallow trench isolation structure to form the first drift region; removing the first mask layer; A second mask layer is formed on the surface of the substrate, wherein the second mask layer has a second mask layer opening, and the bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure outside the first drift region and a portion of the surface of the substrate located on one side of the first shallow trench isolation structure and adjacent to the first drift region; A second ion implantation is performed on the exposed surface of the substrate and the substrate at the bottom of the first shallow trench isolation structure to form the second drift region, wherein the first drift region and the second drift region constitute the drift region, the first drift region and the second drift region are adjacent to each other, and the first shallow trench isolation structure is located in the drift region.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the first ion implantation include that the element implanted is phosphorus and the doping dose of the ion implantation is about 4E12atom / cm 2 -5E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

7. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the second ion implantation include that the element implanted is phosphorus and the doping dose of the ion implantation is about 2E12atom / cm 2 -3E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the gate structure, the method further includes: A body doping region is formed in the substrate at one side of the gate structure, and the body doping region and the first drift region are located at two sides of the second drift region.

9. The method for forming a semiconductor structure according to claim 8, wherein: The ion type in the drift region is opposite to the ion type in the body doping region.

10. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: forming a first source-drain doped region in the drift region and the body doped region on both sides of the gate structure; A second source-drain doping region is formed in the body doping region between adjacent first source-drain doping regions.

11. A semiconductor structure, characterized in that: include: substrate; a first shallow trench isolation structure located in the substrate; a drift region located in the substrate, wherein the first shallow trench isolation structure is located in the drift region, wherein the drift region includes a first drift region and a second drift region adjacent to the first drift region, wherein the ion concentration in the first drift region is greater than the ion concentration in the second drift region, and one side and a part of the bottom of the first shallow trench isolation structure are located in the second drift region; A gate structure is located on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to a surface of a portion of the first shallow trench isolation structure in the first drift region.

12. The semiconductor structure according to claim 11, wherein: A width of the first drift region in a first direction is greater than a width of the second drift region in the first direction, and the first direction is parallel to a channel direction.

13. The semiconductor structure according to claim 11, wherein: The width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region, and the ratio of the width of the first shallow trench isolation structure in the second drift region to the width of the first shallow trench isolation structure in the first drift region is in the range of 0.2:1-0.4:1, and the direction of the width is parallel to the channel direction.

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