Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, forming a source injection region in the epitaxial layer, and forming gate electrode layers on two sides of the source injection region; forming an interlayer dielectric layer covering the epitaxial layer and the gate electrode layer; etching the interlayer dielectric layer to form a source electrode contact hole exposing the source electrode injection region and a gate electrode contact hole exposing the gate electrode layer; performing ion implantation on the epitaxial layer exposed out of the source electrode contact hole so as to modify the upper surface of the epitaxial layer; forming a metal layer covering the bottoms and the side walls of the source electrode contact hole and the grid electrode contact hole; and annealing the metal layer to form a source ohmic contact layer at the bottom of the source contact hole and form a gate ohmic contact layer at the bottom of the gate contact hole. The scheme can shorten the production period and reduce the production cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Silicon Carbide (SiC) is a semiconductor material with excellent properties such as high melting point, high hardness, and high current carrying capacity. It is widely used in new energy, power electronics, radio frequency electronics and other fields. The on-resistance and switching loss of SiC MOSFET are greatly reduced, which is suitable for higher operating frequencies. In addition, due to its high-temperature working characteristics, its high-temperature stability is greatly improved.

[0003] Ohmic contact refers to a good current channel between an electrode material and a semiconductor prepared by a specific process, which can achieve low-resistance, stable and reliable electron transmission. The quality of ohmic contact has an important impact on device performance. Since the source ohmic contact and the gate ohmic contact are usually made of different metal materials, the source ohmic contact and the gate ohmic contact need to be completed in two processes, which increases the production cycle and manufacturing cost of semiconductor devices. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate, a source injection region is formed in the epitaxial layer, and gate electrode layers are formed on the epitaxial layer at both sides of the source injection region; forming an interlayer dielectric layer covering the epitaxial layer and the gate electrode layer; Etching the interlayer dielectric layer to form a source contact hole exposing the source injection region and a gate contact hole exposing the gate electrode layer; Performing ion implantation on the epitaxial layer exposed by the source contact hole to modify the upper surface of the epitaxial layer; forming a metal layer covering the bottom and sidewalls of the source contact hole and the gate contact hole; The metal layer is annealed to form a source ohmic contact layer at the bottom of the source contact hole and a gate ohmic contact layer at the bottom of the gate contact hole.

[0006] Exemplarily, the metal layer includes an ohmic contact metal layer and a barrier layer formed in sequence.

[0007] Exemplarily, the ohmic contact metal layer includes a Ti layer, and the barrier layer includes a TiN layer.

[0008] Exemplarily, the epitaxial layer is a silicon carbide epitaxial layer, and the ions implanted by the ion implantation include silicon ions.

[0009] Exemplarily, the ion implantation temperature is 25°C to 700°C.

[0010] Exemplarily, the energy of the ion implantation is 30KeV ~ 400KeV.

[0011] Exemplarily, the dose of the ion implantation is not less than the E13 level.

[0012] Exemplarily, the annealing temperature is 700° C. to 900° C., and the annealing time is 15 s to 360 s.

[0013] A second aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method described above.

[0014] A third aspect of an embodiment of the present invention provides an electronic device, which includes the semiconductor device described above.

[0015] According to the manufacturing method of the semiconductor device provided by the present invention, the epitaxial layer in the source injection region is modified by performing ion implantation on the epitaxial layer, so that the source ohmic contact layer and the gate ohmic contact layer can be formed by using the same metal material and the same process, thereby shortening the production cycle and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0017] In the attached figure: Figures 1A to 1F A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing various steps according to a method for manufacturing a semiconductor device in the related art is shown; Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention; FIG. 3A to FIG. 3D The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0019] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0020] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0021] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0022] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0023] like Figures 1A to 1F As shown in FIG, currently the source contact hole and the gate contact hole are completed in two photolithography processes. Figure 1A As shown, a source injection region 101 is formed in the epitaxial layer 100, a gate structure 102 is formed on the epitaxial layer 100, and an interlayer dielectric layer 103 covering the gate structure 102 is formed; first, a source contact hole 104 is formed in the interlayer dielectric layer 103 by photolithography and dry etching; then, as shown in FIG. Figure 1B As shown, a first metal layer 105 is deposited on the bottom and sidewall of the source contact hole 104. The material of the first metal layer 105 is metal Ni. Then, as shown in FIG. Figure 1C As shown, the first metal layer reacts with the epitaxial layer 100 exposed at the bottom of the source contact hole 104 through high temperature annealing to form a Ni-Si complex layer; finally, the unreacted metal Ni on the surface of the interlayer dielectric layer 103 is removed by a wet method to finally form a source ohmic contact layer 106.

[0024] Then, if Figure 1D As shown, a photolithography and dry etching are performed again to form a gate contact hole 107; then as shown Figure 1E As shown, a second metal layer 108 is deposited on the bottom and sidewall of the gate contact hole 107, and the material of the second metal layer 108 is metal Ti; finally, as shown in FIG. Figure 1F As shown, the metal Ti reacts with the gate structure 102 exposed at the bottom of the gate contact hole 107 through high temperature annealing to form a gate ohmic contact layer 109 .

[0025] The main difficulty in forming the source ohmic contact layer 106 and the gate ohmic contact layer 109 at the same time is the selection of the contact metal: First, although Ni and SiC can form a good ohmic contact at the source contact hole, Ni reacts violently with polysilicon at the gate contact hole, and polysilicon is easily consumed, resulting in device failure. Therefore, Ni cannot be used as a contact metal. Secondly, although Ti does not react violently with polysilicon at the gate contact hole, the specific contact resistance between Ti and the N-type region is high at the source contact hole, which affects the on-resistance of the device.

[0026] That is to say, Ni can be used as a source contact metal but not as a gate contact metal, and Ti can be used as a gate contact metal but not as a source contact metal. Therefore, the source contact metal layer and the gate contact metal layer must be completed in two processes, which affects the production cycle time of semiconductor devices.

[0027] In view of the existence of the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: Providing a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate, a source injection region is formed in the epitaxial layer, and gate electrode layers are formed on the epitaxial layer at both sides of the source injection region; forming an interlayer dielectric layer covering the epitaxial layer and the gate electrode layer; Etching the interlayer dielectric layer to form a source contact hole exposing the source injection region and a gate contact hole exposing the gate electrode layer; Performing ion implantation on the epitaxial layer exposed by the source contact hole to modify the upper surface of the epitaxial layer; forming a metal layer covering the bottom and sidewalls of the source contact hole and the gate contact hole; The metal layer is annealed to form a source ohmic contact layer at the bottom of the source contact hole and a gate ohmic contact layer at the bottom of the gate contact hole.

[0028] The manufacturing method of the semiconductor device in the embodiment of the present invention modifies the epitaxial layer in the source injection region by performing ion implantation on the epitaxial layer, so that the source ohmic contact layer and the gate ohmic contact layer can be formed by the same metal material and the same process, thereby shortening the production cycle and reducing production costs.

[0029] Below, reference Figure 2 and FIG. 3A to FIG. 3D A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. FIG. 3A to FIG. 3D The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0030] First, execute step S201, such as Figure 3AAs shown, a semiconductor substrate is provided, an epitaxial layer 300 is formed on the semiconductor substrate, a source injection region 301 is formed in the epitaxial layer 300 , and a gate electrode layer 302 is formed on the epitaxial layer 300 on both sides of the source injection region 301 .

[0031] The material of the semiconductor substrate may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the semiconductor substrate may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form a semiconductor substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.

[0032] In one example, the semiconductor device to be formed is a silicon carbide (SiC) MOSFET device, and the semiconductor substrate is a silicon carbide substrate. Exemplarily, the epitaxial layer 300 is a silicon carbide epitaxial layer formed on a silicon carbide substrate. Optionally, the silicon carbide substrate and the epitaxial layer 300 may have the same conductivity type. Exemplarily, the silicon carbide substrate and the epitaxial layer 300 may have different doping concentrations, for example, the doping concentration of the epitaxial layer 300 may be lower than the doping concentration of the silicon carbide substrate. Optionally, the epitaxial layer 300 may be used as a drift region of the semiconductor device. The presence of the drift region can provide a breakdown voltage of the device and act as a buffer, while reducing the parasitic capacitance between the source and the drain.

[0033] The semiconductor substrate includes a cell region and a terminal region, a source injection region 301 is formed in the cell region, and a gate electrode layer 302 is formed in the terminal region. Exemplarily, the source injection region can be formed by an ion implantation process, and the doped ions in the source injection region are activated by an annealing process, while repairing the lattice structure of the semiconductor substrate surface damaged in the ion implantation process, and finally forming the source injection region 301.

[0034] Exemplarily, a gate structure is formed in both the cell region and the terminal region, and the gate structure includes a gate dielectric layer (not shown) and a gate electrode layer. Optionally, the gate dielectric layer may include a conventional dielectric material such as silicon oxide. Alternatively, the gate dielectric layer may include a higher dielectric constant dielectric material, such as hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate, and lead zirconate titanate. In one embodiment, the gate electrode layer is composed of a polysilicon material, or a metal, a metal nitride, a metal silicide, or a similar compound may be used to form the gate electrode layer.

[0035] In a specific example, taking an N-type SiC MOSFET as an example, a P-type SiC substrate can be provided, and then a lightly doped N-type drift region is formed on the SiC substrate through an epitaxial process, and then ion implantation is performed to form a P-type well region. Next, a field oxide layer is formed in the drift region and the P-type well region to define the active region, and then a gate oxide layer and a gate electrode layer are grown on the active region, and the gate electrode layer and the gate oxide layer are etched in sequence to form a gate structure. Then, a P-type heavily doped region and N-type heavily doped regions located on both sides of the P-type heavily doped region are formed in the P-type well region through a doping process as a source injection region 301, and a drain structure is formed on the side of the drift region away from the P-type well region.

[0036] Next, step S202 is performed to form an interlayer dielectric layer 303 covering the epitaxial layer 300 and the gate electrode layer 302. By way of example, the interlayer dielectric layer 303 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). By way of example, the material of the interlayer dielectric layer 303 may be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride, which is not limited in the embodiment of the present invention. The interlayer dielectric layer 303 covers the gate electrode layer 302 and the surface of the epitaxial layer 300 located above the source injection region 301.

[0037] Next, step S203 is performed to etch the interlayer dielectric layer 303 to form a source contact hole 304 exposing the source injection region 301 and a gate contact hole 305 exposing the gate electrode layer 302. Exemplarily, a mask layer is formed on the interlayer dielectric layer, the mask layer includes etching windows corresponding to the source injection region 301 and the gate electrode layer 302; and the interlayer dielectric layer 303 is etched based on the mask layer to form a source contact hole 304 exposing the source injection region 301 and a gate contact hole 305 exposing the gate electrode layer 302, as shown in FIG. Figure 3B That is, through one photolithography and etching process, the source contact hole 304 and the gate contact hole 305 are formed simultaneously.

[0038] Specifically, a photoresist layer can be formed on the interlayer dielectric layer 303, and the photoresist layer is exposed and developed to form an etching window defining the position of the source contact hole 304 and the gate contact hole 305, and then the interlayer dielectric layer 303 is dry-etched using the photoresist layer as a mask, so as to form a source contact hole 304 above the source injection region 301 in the cell region, and to form a gate contact hole 305 above the gate electrode layer 302 in the terminal region. The dry etching process includes but is not limited to etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching. The embodiment of the present invention simultaneously forms the source contact hole 304 and the gate contact hole 305 through a single photolithography etching process, saving two photolithography processes to one photolithography process, which can save wafer fabrication costs and time.

[0039] After forming the source contact hole 304 and the gate contact hole 305 , step S204 is performed to perform ion implantation on the epitaxial layer 300 exposed by the source contact hole 304 to modify the upper surface of the epitaxial layer 300 so that the properties of the epitaxial layer 300 are close to those of the gate electrode layer 302 .

[0040] For example, when the epitaxial layer 300 is a silicon carbide epitaxial layer and the material of the gate electrode layer 302 is polysilicon, the ions injected into the epitaxial layer 300 include silicon ions. After the silicon ions are injected, the physical properties of the silicon carbide epitaxial layer exposed by the source contact hole 304 will be closer to the properties of the polysilicon constituting the gate electrode layer 302.

[0041] For example, the temperature of ion implantation is 25°C to 700°C, the energy of ion implantation is 30KeV to 400KeV, and the dose of ion implantation is not less than the order of magnitude of E13. When ion implantation is performed using the above process conditions, the properties of the epitaxial layer 300 exposed by the source contact hole 304 can meet the process requirements.

[0042] Next, step S205 is performed to form a metal layer covering the bottom and sidewalls of the source contact hole 304 and the gate contact hole 305. Since the epitaxial layer 300 has been modified before, the source and the gate can share the same metal layer to form an ohmic contact layer.

[0043] In one embodiment, Figure 3C As shown, the metal layer includes an ohmic contact metal layer 306 and a barrier layer 307 formed in sequence. The ohmic contact metal layer 306 is used to form an ohmic contact layer with the epitaxial layer 300 and the gate electrode layer 302, and the barrier layer 307 is used to prevent metal ions from diffusing.

[0044] Exemplarily, the ohmic contact metal layer 306 includes a Ti layer, and the barrier layer 307 includes a TiN layer. Ti, as an ohmic contact metal for forming a complex, can reduce the barrier height between the metal and SiC; TiN, as a barrier layer, can prevent Ti from diffusing during subsequent thermal annealing and avoid changes in the composition of the Ti-SiC complex. In addition, using Ti instead of Ni as the ohmic contact metal layer 306 can also avoid violent reactions between Ni and polysilicon. Compared with Ni, the interface of the ohmic contact between Ti and SiC is smoother, and no additional carbon clusters are precipitated.

[0045] Next, execute step S206, such as Figure 3D As shown, the metal layer is annealed to form a source ohmic contact layer 308 at the bottom of the source contact hole 304, and a gate ohmic contact layer 309 is formed at the bottom of the gate contact hole 305. Since metal can react with silicon, but will not react with silicon oxides such as silicon dioxide, the metal will only react with the exposed surface of the epitaxial layer 300 or the surface of the gate electrode layer 302 to form a metal silicide, i.e., an ohmic contact layer. Exemplarily, the annealing temperature is 700°C to 900°C, and the annealing time is 15s to 360s. The embodiment of the present invention reduces the annealing temperature from the original 950°C to 1050°C to 700°C to 900°C, which reduces the thermal budget and further saves the wafer production cost.

[0046] Afterwards, a metal interconnection layer may be formed to fill the source contact hole 304 and the gate contact hole 305. Optionally, the material of the metal interconnection layer may include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al.

[0047] After forming the metal interconnection layer, a passivation layer covering the metal interconnection layer may be formed, and the passivation layer is used to isolate the external influence. In one example, the material of the passivation layer may include various suitable materials such as oxide, nitride, polymer, etc.

[0048] At this point, the process steps implemented in the method for manufacturing a semiconductor device according to the first aspect of the present invention have been completed. It can be understood that the method for manufacturing a semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0049] According to the method for manufacturing a semiconductor device provided by an embodiment of the present invention, the semiconductor substrate in the source injection region is modified by performing ion implantation on the semiconductor substrate, so that the source ohmic contact layer and the gate ohmic contact layer can be formed by using the same metal material and the same process, thereby shortening the production cycle and reducing production costs.

[0050] The second aspect of the present invention further provides a semiconductor device, which can be prepared by the method in the first embodiment.

[0051] Below, reference Figure 3D The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment 1. For specific explanations and descriptions, reference can be made to the description in embodiment 1.

[0052] Specifically, Figure 3D As shown, the semiconductor device of the embodiment of the present invention includes a semiconductor substrate, an epitaxial layer 300 is formed on the semiconductor substrate, a source injection region 301 is formed in the epitaxial layer 300, and a gate electrode layer 302 is formed on the epitaxial layer 300 on both sides of the source injection region 301; an interlayer dielectric layer 303 is formed above the epitaxial layer 300 and the gate electrode layer 302; a source contact hole 304 exposing the source injection region 301 and a gate contact hole 305 exposing the gate electrode layer 302 are formed in the interlayer dielectric layer 303; a source ohmic contact layer 308 is formed at the bottom of the source contact hole 304, and a gate ohmic contact layer 309 is formed at the bottom of the gate contact hole 305, and the source ohmic contact layer 308 and the gate ohmic contact layer 309 are made of the same material. Exemplarily, the source ohmic contact layer 308 and the gate ohmic contact layer 309 both include a Ti-SiC complex.

[0053] The semiconductor device of the embodiment of the present invention has similar advantages because it is manufactured by the method of the first embodiment.

[0054] The third aspect of the present invention further provides an electronic device in an embodiment, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0055] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0056] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that The method comprises: Providing a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate, a source injection region is formed in the epitaxial layer, and gate electrode layers are formed on the epitaxial layer at both sides of the source injection region; forming an interlayer dielectric layer covering the epitaxial layer and the gate electrode layer; Etching the interlayer dielectric layer to form a source contact hole exposing the source injection region and a gate contact hole exposing the gate electrode layer; Performing ion implantation on the epitaxial layer exposed by the source contact hole to modify the upper surface of the epitaxial layer; forming a metal layer covering the bottom and sidewalls of the source contact hole and the gate contact hole; The metal layer is annealed to form a source ohmic contact layer at the bottom of the source contact hole and a gate ohmic contact layer at the bottom of the gate contact hole.

2. The manufacturing method according to claim 1, It is characterized in that The metal layer includes an ohmic contact metal layer and a barrier layer which are formed in sequence.

3. The manufacturing method according to claim 2, It is characterized in that The ohmic contact metal layer includes a Ti layer, and the barrier layer includes a TiN layer.

4. The manufacturing method according to claim 1, It is characterized in that The epitaxial layer is a silicon carbide epitaxial layer, and the ions implanted by the ion implantation include silicon ions.

5. The manufacturing method according to claim 1 or 4, It is characterized in that The temperature of the ion implantation is 25°C to 700°C.

6. The manufacturing method according to claim 1 or 4, It is characterized in that The energy of the ion implantation is 30KeV ~400KeV.

7. The manufacturing method according to claim 1 or 4, It is characterized in that The dosage of the ion implantation is not less than the E13 level.

8. The manufacturing method according to claim 1, It is characterized in that The annealing temperature is 700° C. to 900° C., and the annealing time is 15 s to 360 s.

9. A semiconductor device, It is characterized in that The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, It is characterized in that The electronic apparatus includes the semiconductor device according to claim 9.

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