Manufacturing method of silicon carbide MOS device and silicon carbide MOS device

Abstract

The invention provides a manufacturing method of a silicon carbide MOS device and the silicon carbide MOS device, and belongs to the field of semiconductors. The manufacturing method of the silicon carbide MOS device comprises the steps that a substrate is provided, a drift region and a drain electrode are arranged on the front face and the back face of the substrate respectively, the drift region is provided with a JFET region and a P well, a gate structure is formed in the JFET region, a source electrode is formed in the P well, and the gate structure and the silicon carbide substrate are covered with dielectric layers. And respectively and simultaneously manufacturing a source contact hole and a gate contact hole at the positions of the source structure and the gate structure. And shielding the gate contact hole. Forming first ohmic contact at the source contact hole and forming second ohmic contact at the gate contact hole by adopting a rapid thermal annealing process; and removing the residual metal. The source contact hole and the grid contact hole are manufactured at the same time, the photoetching process is saved from two times to one time, tape-out cost and time are saved, and violent reaction between metal nickel and polycrystalline silicon is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a silicon carbide MOS device and a silicon carbide MOS device. Background Art

[0002] Silicon carbide (SiC) material is a typical representative of the third generation of semiconductor materials. It is also one of the wide bandgap semiconductor materials with the most mature and widely used crystal growth technology and device manufacturing level. Compared with silicon materials, it has a larger bandgap width, higher thermal conductivity, higher electron saturation drift velocity and a critical breakdown electric field 10 times that of silicon materials, making it an ideal semiconductor material in high temperature, high frequency, high power and radiation-resistant applications. Therefore, wide bandgap semiconductor materials represented by silicon carbide are rapidly developing new semiconductor materials. Silicon carbide power device technology is a strategic high-tech with extremely important value. Therefore, it has received extensive attention and in-depth research from many semiconductor companies and research institutions at home and abroad, and has become one of the hot spots in the international research of new materials, microelectronics and power electronics. One of the key processes for the application of silicon carbide materials in the field of high temperature, high power and high frequency semiconductor devices is the need to prepare ohmic contacts.

[0003] In the prior art, the metal contact holes at the ohmic contact of the source and the ohmic contact position of the gate are completed in two photolithography processes. The specific steps are: first, the source contact hole position is formed by photolithography and dry etching. Next, metal nickel (Ni) is deposited. Then, by using a high-temperature rapid annealing process at a temperature of 700°C to 1050°C, it reacts with the Ni deposited in the source contact hole to form a Ni2Si complex. Subsequently, the unreacted metal Ni on the dielectric layer is removed by wet etching, and finally the source ohmic contact is formed. Finally, the gate contact hole position is formed by another photolithography and dry etching, and the gate ohmic contact is formed by depositing metal TiAL.

[0004] When the source ohmic contact and the gate ohmic contact are made in the above-mentioned manner, two photolithography steps are required to complete the production of the contact holes, which prolongs the production time of the product. After the source contact hole and the gate contact hole are made simultaneously by one photolithography, when metal Ni is deposited in the source contact hole, metal Ni will also be deposited on the inner wall and bottom of the gate contact hole. Since metal Ni reacts with the polysilicon layer of the gate structure by thermal diffusion, the polysilicon layer of the gate is easily consumed, causing damage to the gate structure. In addition, since metal Ni reacts with the substrate silicon carbide (SiC), additional carbon (C) clusters will be precipitated, further damaging the device and reducing the performance of the device.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a method for manufacturing a silicon carbide MOS device and a silicon carbide MOS device, so as to solve the problem that the prior art is time-consuming or causes damage to the gate and substrate of the device when manufacturing ohmic contacts.

[0007] In order to solve the above technical problems, the present invention provides a method for manufacturing a silicon carbide MOS device, comprising: A substrate is provided, wherein a drift region and a drain are respectively arranged on the front and back sides of the substrate, the drift region is provided with a JFET region and a P well, the JFET region is formed with a gate structure, the P well is formed with a source, and the gate structure and the silicon carbide substrate are covered with a dielectric layer; Simultaneously making a source contact hole and a gate contact hole at the positions of the source and gate structures respectively; Blocking the gate contact hole and removing the blocking material after depositing metal in the source contact hole; A first ohmic contact is formed at the source contact hole and a second ohmic contact is formed at the gate contact hole by using a rapid thermal annealing process; Remove any remaining metal.

[0008] Preferably, the step of simultaneously forming a source contact hole and a gate contact hole at the positions of the source and gate structures respectively comprises: Producing source contact hole patterns and gate contact hole patterns on a photolithography plate; Transferring the source contact hole pattern and the gate contact hole pattern to the surface of the dielectric layer by developing; The dielectric layer is removed by dry etching, a source contact hole is formed at the source, and a gate contact hole is formed at the gate structure.

[0009] Preferably, blocking the gate contact hole and removing the blocking material after depositing metal in the source contact hole comprises: Covering the gate contact hole with a metal mask; After metal is deposited on the inner wall and bottom of the source contact hole, the metal mask is removed.

[0010] Preferably, blocking the gate contact hole and removing the blocking material after depositing metal in the source contact hole comprises: Depositing photoresist on the surface of the dielectric layer; Etching the photoresist at a position corresponding to the source contact hole, and making an arc structure at a position of the photoresist close to the source contact hole; Depositing metal on the inner wall and bottom of the source contact hole; Next, the photoresist is removed by wet etching.

[0011] Preferably, the metal is deposited on the inner wall and the bottom of the source contact hole by evaporating the metal.

[0012] Preferably, the metal deposited in the source contact hole is nickel.

[0013] Preferably, the temperature of the rapid thermal annealing process is 700° C. to 1050° C., and the duration is 150 seconds to 360 seconds.

[0014] Preferably, after removing the remaining metal, the method for manufacturing the silicon carbide MOS device further comprises: Forming a source metal layer and a gate metal layer on the source electrode and the gate structure respectively, wherein the source metal layer and the gate metal layer are both arranged on the surface of the dielectric layer, the source metal layer penetrates the source electrode and is connected to the first ohmic contact, and the gate metal layer penetrates the gate structure and is connected to the second ohmic contact; forming a passivation layer on the surface of the source metal layer and the gate metal layer, wherein the passivation layer covers the metal layer of the gate structure, the gap between the gate metal layer and the source metal layer, and the source metal layer near the gap; A PI layer is formed on the surface of the passivation layer.

[0015] Preferably, the gate structure includes an oxide layer formed in the JFET region and a polysilicon layer formed on the surface of the oxide layer.

[0016] Based on the same inventive concept, the present invention also provides a silicon carbide MOS device, including a device manufactured by the above-mentioned method for manufacturing the silicon carbide MOS device.

[0017] Compared with the prior art, the method for manufacturing a silicon carbide MOS device of the present invention has the following advantages: The present invention provides a substrate, wherein a drift region and a drain are respectively arranged on the front and back sides of the substrate, the drift region is provided with a JFET region and a P well, the JFET region is formed with a gate structure, the P well is formed with a source, and the gate structure and the silicon carbide substrate are covered with a dielectric layer. A source contact hole and a gate contact hole are simultaneously made at the positions of the source and gate structures, respectively. The gate contact hole is shielded, and after metal is deposited in the source contact hole, the shielding is removed. A first ohmic contact is formed at the source contact hole and a second ohmic contact is formed at the gate contact hole by a rapid thermal annealing process; and the remaining metal is removed. Therefore, the method for manufacturing a silicon carbide MOS device provided by the present invention saves two photolithography processes to one photolithography process because the source contact hole and the gate contact hole are simultaneously made, and the first ohmic contact and the second ohmic contact are synchronously formed in the source contact hole and the gate contact hole by a rapid thermal annealing process, thereby saving the cost and time of wafer taping and avoiding the violent reaction between metal nickel and polysilicon. Therefore, the ohmic contact manufacturing time of the silicon carbide MOS device can be shortened and damage to the silicon carbide MOS device can be avoided, thereby improving the performance of the device.

[0018] The silicon carbide MOS device provided by the present invention and the method for manufacturing the silicon carbide MOS device provided by the present invention belong to the same inventive concept. Therefore, the silicon carbide MOS device provided by the present invention has at least all the advantages of the method for manufacturing the silicon carbide MOS device provided by the present invention, and improves the performance of the silicon carbide MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flow chart of a method for manufacturing a silicon carbide MOS device in one embodiment of the present invention.

[0020] Figure 2 It is a schematic structural diagram of forming a source contact hole and a gate contact hole in a source and gate structure in one embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the structure after the gate contact hole is blocked in one embodiment of the present invention.

[0022] Figure 4 It is a schematic structural diagram of forming a first ohmic contact in a source contact hole and forming a second ohmic contact in a gate contact hole in one embodiment of the present invention.

[0023] Figure 5 It is a schematic structural diagram after the gate contact hole is shielded in another embodiment of the present invention.

[0024] Figure 6 In one embodiment of the present invention, Figure 5 Schematic diagram of the structure after occlusion in .

[0025] In the figure, 100-drain; 200-N+ substrate; 300-N-drift region; 400-silicon oxide layer; 500-polysilicon layer; 600-dielectric layer; 610-source contact hole; 620-gate contact hole; 611-first ohmic contact; 612-second ohmic contact; 700-photoresist; 710-arc structure; 800-metal nickel; 900-metal mask. DETAILED DESCRIPTION

[0026] In order to make the purpose, advantages and features of the present invention clearer, the manufacturing method of the silicon carbide MOS device and the silicon carbide MOS device proposed in the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0028] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0029] In the prior art, when manufacturing ohmic contacts of silicon carbide MOS devices, there are technical problems such as long manufacturing time, complicated processes, or damage to the devices.

[0030] The core idea of ​​the present invention is to provide a method for manufacturing a silicon carbide MOS device, which can shorten the manufacturing time and avoid damage to the device when manufacturing the silicon carbide MOS device.

[0031] In order to realize the above idea, the present invention provides a method for manufacturing a silicon carbide MOS device. Figures 1 to 6 A specific implementation of a method for manufacturing a silicon carbide MOS device is disclosed. The method for manufacturing a silicon carbide MOS device includes the following steps S1 to S5.

[0032] Step S1: Provide a silicon carbide substrate, wherein a drift region and a drain 100 are respectively arranged on the front and back sides of the silicon carbide substrate, the drift region is provided with a JFET region and a P well, the JFET region is formed with a gate structure, the P well is formed with a source, and the gate structure and the silicon carbide substrate are covered with a dielectric layer 600.

[0033] Specifically, refer to Figure 1 and Figure 2 As shown, a substrate is provided. The substrate is an N+ substrate 200. A drain 100 is arranged on the back side of the N+ substrate 200. An N-drift region 300 is arranged on the front side of the N+ substrate 200. The N-drift region 300 is provided with a JFET region and a P well. A source is formed in the P well, including a highly doped P+ region and a highly doped N+ region. The N+ substrate 200, the N-drift region 300, the JFET region, the P+ region, and the N+ region are all made of SiC materials. A gate structure is formed in the JFET region, including a silicon oxide layer 400 deposited in the JFET region, a polysilicon layer 500 deposited on the surface of the silicon oxide layer 400, and a dielectric layer 600 deposited on the polysilicon layer 500 and the surface of the source.

[0034] Step S2: simultaneously making a source contact hole 610 and a gate contact hole 620 at the source and gate structure positions respectively.

[0035] Specifically, continue to Figure 1 and Figure 2 As shown, simultaneously forming a source contact hole 610 and a gate contact hole 620 at the source and gate structure positions respectively includes: First, a source contact hole pattern and a gate contact hole pattern are formed on a photoresist.

[0036] Next, the source contact hole pattern and the gate contact hole pattern are transferred to the surface of the dielectric layer 600 by developing, that is, the source contact hole pattern and the gate contact hole pattern are formed at the positions corresponding to the source and gate structures on the surface of the dielectric layer 600.

[0037] Then, the dielectric layer 600 is removed by dry etching, a source contact hole 610 is formed at the source, and a gate contact hole 620 is formed at the gate structure. Dry etching is performed by, for example, introducing an etching gas such as methane, ethane, or carbon tetrafluoride into an etching machine to etch the dielectric layer 600, so as to form the following at the positions corresponding to the source and the gate structure: Figure 2 The source contact hole 610 and the gate contact hole 620 are shown. In this step, by simultaneously making the source contact hole pattern and the gate contact hole pattern on the same photomask, and completing the source contact hole 610 and the gate contact hole 620 at the same time, the contact hole production time can be shortened, thereby shortening the device production time. Two photolithography processes are reduced to one photolithography process, saving the cost and time of tape-out.

[0038] Step S3: Block the gate contact hole 620 and remove the blocking material after metal is deposited in the source contact hole 610 .

[0039] Specifically, refer to Figure 1 and Figure 3 As shown, the metal may be nickel, aluminum, etc. In this embodiment, the deposited metal is preferably nickel. As one embodiment, first, the gate contact hole 620 is blocked, and metal nickel 800 is deposited in the source contact hole 610, including: covering the gate contact hole 620 with a metal mask 900.

[0040] Then, after depositing metal nickel 800 on the inner wall and bottom of the source contact hole 610, the metal mask 900 is removed. Since metal nickel 800 is deposited on the inner wall, bottom and surrounding of the source contact hole 610, the metal mask 900 is removed.

[0041] Ginseng Figure 1 , Figure 5 and Figure 6 As shown, the metal is still preferably nickel metal 800, the gate contact hole 620 is blocked, and the nickel metal 800 is deposited in the source contact hole 610, including: First, a photoresist 700 is deposited on the surface of the dielectric layer 600 to cover the gate contact hole 620 .

[0042] Secondly, the photoresist 700 is etched at the position corresponding to the source contact hole 610, and the arc structure 710 is made at the position of the photoresist 700 close to the source contact hole 610. When making the arc structure 710, it is only necessary to block the position of the arc structure 710 to complete the making. It should be noted that how to make the arc structure 710 and etch the photoresist 700 are both prior arts, and those skilled in the art are already familiar with the specific process steps, which will not be described in detail here.

[0043] Then, metal nickel 800 is deposited on the inner wall and bottom of the source contact hole 610. In this embodiment, the metal nickel 800 is deposited on the inner wall and bottom of the source contact hole 610 by evaporating the metal nickel 800. Since the metal nickel 800 is deposited by evaporating the metal nickel 800, the metal nickel 800 is deposited on the inner wall and bottom of the source contact hole 610, around the source contact hole 610, and on the surface of the photoresist 700.

[0044] Next, the photoresist 700 is removed by wet etching. For example, the photoresist 700 can be etched by adding a cleaning agent such as sulfuric acid to the etching tank. When etching the photoresist 700, since the photoresist 700 forms an arc structure 710, the cleaning agent will enter one side of the arc structure 710 and remove the metal nickel 800 on the surface of the photoresist 700, forming a Figure 6 The structure shown.

[0045] Step S4 : forming a first ohmic contact 611 at the source contact hole 610 and forming a second ohmic contact 612 at the gate contact hole 620 by using a rapid thermal annealing process.

[0046] Specifically, refer to Figure 1 and Figure 4As shown, a rapid thermal annealing process is used to form a first ohmic contact 611 at the source contact hole 610, and a second ohmic contact 612 at the gate contact hole 620. The temperature of the rapid thermal annealing process is 700°C to 1050°C. That is, the temperature of the rapid thermal annealing process can be 700°C, 800°C, 900°C, 1000°C, 1050°C, or any temperature within the range of 700°C to 1050°C. The duration of the rapid thermal annealing is 150 seconds to 360 seconds. That is, the duration of the rapid thermal annealing can be 150 seconds, 200 seconds, 250 seconds, 300 seconds, 360 seconds, or any time within the range of 150 seconds to 360 seconds. Through rapid thermal annealing, the metal nickel 800 reacts with the SiC material to generate a Ni2Si complex, reduce the barrier height between the metal and SiC, and form the first ohmic contact 611 at the source contact hole 610. The second ohmic contact 612 is formed at the gate contact hole 620 by a rapid thermal annealing process. The first ohmic contact 611 and the second ohmic contact 612 are formed by this step, which can avoid the metal nickel 800 from reacting with the polysilicon layer 500 through thermal diffusion, thereby avoiding damage to the gate structure. At the same time, it can also avoid the metal Ni from reacting with the substrate silicon carbide (SiC) to cause additional C group precipitation, thereby avoiding damage to the device substrate. The performance of the device is improved.

[0047] Step S5: removing the remaining metal.

[0048] Specifically, refer to Figure 1 , Figure 3 and 5 As shown, in step S3, there is still metal nickel 800 around the source contact hole 610, so the remaining metal nickel 800 can be removed by wet etching. The cleaning solution for wet etching can be a mixture of sulfuric acid and hydrogen peroxide.

[0049] After removing the remaining metal nickel 800, the method for manufacturing the silicon carbide MOS device further includes: A source metal layer and a gate metal layer are formed on the source and gate structures respectively, and both the source metal layer and the gate metal layer are arranged on the surface of the dielectric layer 600, the source metal layer penetrates the source and is connected to the first ohmic contact 611, and the gate metal layer penetrates the gate structure and is in contact with the second ohmic contact 612. The material of the metal layer is titanium aluminum (TiAl) alloy.

[0050] Next, a passivation layer is formed on the surface of the source metal layer and the gate metal layer, and the passivation layer covers the metal layer of the gate structure, the gap between the gate metal layer and the source metal layer, and the source metal layer near the gap. The material of the passivation layer is silicon nitride (SiN).

[0051] Then, a PI layer is formed on the surface of the passivation layer. The material of the PI layer is polyimide.

[0052] To realize the above idea, this embodiment also discloses a silicon carbide MOS device, including: The silicon carbide MOS device is manufactured using the manufacturing method described above.

[0053] The silicon carbide MOS device provided in this embodiment and the method for manufacturing the silicon carbide MOS device provided in this embodiment belong to the same inventive concept. Therefore, the silicon carbide MOS device provided in this embodiment has at least all the advantages of the method for manufacturing the silicon carbide MOS device provided in this embodiment, and improves the performance of the silicon carbide MOS device.

[0054] In summary, the above embodiments provide detailed descriptions of the manufacturing method of silicon carbide MOS devices and different configurations of silicon carbide MOS devices. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a silicon carbide MOS device, characterized in that: include: A substrate is provided, wherein a drift region and a drain are respectively arranged on the front and back sides of the substrate, the drift region is provided with a JFET region and a P well, the JFET region is formed with a gate structure, the P well is formed with a source, and the gate structure and the silicon carbide substrate are covered with a dielectric layer; Simultaneously making a source contact hole and a gate contact hole at the positions of the source and gate structures respectively; Blocking the gate contact hole and removing the blocking material after depositing metal in the source contact hole; A first ohmic contact is formed at the source contact hole and a second ohmic contact is formed at the gate contact hole by using a rapid thermal annealing process; Remove any remaining metal.

2. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: The step of simultaneously forming a source contact hole and a gate contact hole at the source and gate structure positions respectively comprises: Producing source contact hole patterns and gate contact hole patterns on a photolithography plate; Transferring the source contact hole pattern and the gate contact hole pattern to the surface of the dielectric layer by developing; The dielectric layer is removed by dry etching, a source contact hole is formed at the source, and a gate contact hole is formed at the gate structure.

3. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: After blocking the gate contact hole and depositing metal in the source contact hole, removing the blocking material comprises: Covering the gate contact hole with a metal mask; After metal is deposited on the inner wall and bottom of the source contact hole, the metal mask is removed.

4. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: After blocking the gate contact hole and depositing metal in the source contact hole, removing the blocking material comprises: Depositing photoresist on the surface of the dielectric layer; Etching the photoresist at a position corresponding to the source contact hole, and making an arc structure at a position of the photoresist close to the source contact hole; Depositing metal on the inner wall and bottom of the source contact hole; Next, the photoresist is removed by wet etching.

5. The method for manufacturing a silicon carbide MOS device according to claim 4, characterized in that: Metal is deposited on the inner wall and bottom of the source contact hole by evaporating the metal.

6. The method for manufacturing a silicon carbide MOS device according to any one of claims 1 to 5, characterized in that: The metal deposited in the source contact hole is nickel.

7. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: The temperature of the rapid thermal annealing process is 700° C. to 1050° C., and the duration is 150 seconds to 360 seconds.

8. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: After removing the remaining metal, the method for manufacturing the silicon carbide MOS device further includes: Forming a source metal layer and a gate metal layer on the source electrode and the gate structure respectively, wherein the source metal layer and the gate metal layer are both arranged on the surface of the dielectric layer, the source metal layer penetrates the source electrode and is connected to the first ohmic contact, and the gate metal layer penetrates the gate structure and is connected to the second ohmic contact; forming a passivation layer on the surface of the source metal layer and the gate metal layer, wherein the passivation layer covers the metal layer of the gate structure, the gap between the gate metal layer and the source metal layer, and the source metal layer near the gap; A PI layer is formed on the surface of the passivation layer.

9. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that: The gate structure includes an oxide layer formed in the JFET region and a polysilicon layer formed on the surface of the oxide layer.

10. A silicon carbide MOS device, characterized in that: include: The silicon carbide MOS device is manufactured using the manufacturing method of any one of claims 1 to 9.

Images