Wafer cutting method

Abstract

A wafer dicing method is provided that includes implanting a substrate with a dopant to form an implant layer within the substrate, the implant layer being located at an intermediate height between an upper surface and a lower surface of the substrate. A laser beam is irradiated onto the implant layer and onto the side wall of the substrate. After the laser beam is irradiated, the substrate is heated, so that the substrate is cut at the implant layer and is cut into a top part and a bottom part;

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor technology, and more particularly to a method for cutting a wafer having a notch on a side wall of the wafer. Background Art

[0002] Semiconductor wafers can be thinned in some manufacturing processes. The thinning process can be performed by a chemical mechanical polishing (CMP) process or a mechanical grinding process. Summary of the invention

[0003] In some embodiments, a wafer cutting method is provided, comprising: implanting a substrate with a dopant to form an implantation layer in the substrate, wherein the implantation layer is located at an intermediate height between the upper surface and the lower surface of the substrate; irradiating the implantation layer with a laser beam, wherein the laser beam is irradiated on a side wall of the substrate; and after irradiating the laser beam, heating the substrate to separate the substrate at the implantation layer, wherein the substrate is separated into a top portion and a bottom portion.

[0004] In some embodiments, a wafer cutting method is provided, comprising: implanting a substrate with a dopant to form an implantation layer in the substrate, wherein the implantation layer is located at an intermediate height between the upper surface and the lower surface of the substrate; cutting the substrate to form a notch, wherein the notch extends into the implantation layer; and after forming the notch, heating the substrate to separate the substrate at the notch.

[0005] In some embodiments, a wafer dicing method is provided, comprising: bonding a top wafer to a bottom wafer, wherein the top wafer includes a substrate, and wherein the substrate includes an implanted layer having a dopant; forming a high stress region in the substrate, wherein the high stress region extends laterally in the implanted layer; and forming a crack starting from the high stress region, wherein the crack propagates laterally from the crack to separate the top wafer into a top portion and a bottom portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1-3 , 4A, 4B, 4C and 5-8 are cross-sectional schematic diagrams showing intermediate stages of a wafer cutting process according to some embodiments.

[0007] Fig. 9 The distribution of implanted dopants and the locations of notches are shown according to some embodiments.

[0008] Fig.10 The process flow of a wafer dicing process according to some embodiments of the present disclosure is shown.

[0009] Description of reference numerals:

[0010] 20: Package components; bottom wafer; wafer

[0011] 24: Semiconductor substrate

[0012] 26: Integrated circuit devices

[0013] 28: Interlayer dielectric (ILD) layer

[0014] 30: Contact plug

[0015] 32: Internal connection structure

[0016] 34: Metal wire

[0017] 36: Via hole

[0018] 38,126: Dielectric layer

[0019] 40,70: Photonic devices

[0020] 42: Bonding film layer

[0021] 46: Implantation Process

[0022] 50: Composite wafer

[0023] 52: Rotating suction cup platform

[0024] 54: Laser beam generator

[0025] 56: Laser Beam

[0026] 58: Stress concentration area

[0027] 60: Notch

[0028] 62: Blade

[0029] 64: Heating unit

[0030] 65: Radiation

[0031] 72: Microlens

[0032] 74: Transparent dielectric layer

[0033] 120: Top wafer

[0034] 120B: bottom part; bottom wafer part

[0035] 120T: Top part; top wafer part

[0036] 122: Bonding film layer; Dielectric layer

[0037] 124: Base

[0038] 130: implantation layer; implantation area

[0039] 200: Process

[0040] 202,204,206,208,210,212,214: process steps

[0041] LD1: Lateral Depth DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present disclosure. The following disclosure describes specific examples of various components and their arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present disclosure. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in various different examples. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0043] Spatially related terms such as "under", "below", "lower", "over", "upper", etc. are used herein to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0044] A wafer cutting process is provided. According to some embodiments of the present disclosure, a top wafer is bonded to a bottom wafer. Dopants are implanted into a portion of the top wafer to form an implantation layer, which is located at the middle height of the wafer. A stress concentration area is generated around the edge area of ​​the wafer. A laser can be used to generate the stress concentration area. According to some embodiments, the stress concentration area may include a notch. A blade can also be used to generate the stress concentration area. The wafer is then cut by heating the wafer, wherein defects are generated in the implantation area so that the wafer is cut at the implantation area. During the heating process, cracks are formed in the stress concentration area, and the cracks extend to the entire implantation area. Therefore, the wafer cutting process is easier and more precise.

[0045] The embodiments described herein will provide examples of inventive subject matter that can be implemented or used, and those skilled in the art will readily appreciate the modifications that can be made while being encompassed within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to indicate the same components. Although the description of the method embodiments may be performed in a particular order, in other method embodiments, any logical order may be performed.

[0046] Figure 1-3 4A, 4B, 4C and 5-8 are cross-sectional schematic diagrams showing the intermediate stages of the wafer cutting process according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.10 The process flow shown.

[0047] Figure 1 A schematic cross-sectional view of the package component 20 is shown. According to some embodiments of the present disclosure, the package component 20 is a wafer or includes a wafer, and the wafer includes active devices and may also include passive devices, which are represented as integrated circuit devices 26. For example, according to some embodiments of the present disclosure, the package component 20 may be or may include an electronic wafer having an electronic grain inside, and the electronic grain may be used to form or bond to a photonic grain having a photonic device. According to other embodiments, the package component 20 is a photonic wafer or includes a photonic wafer having a photonic grain inside, and according to some embodiments of the present disclosure, the photonic grain may also be used to form a photonic engine. The photonic grain or wafer may include a photonic device, such as a waveguide, a grating coupler, a photodiode, a modulator, or the like.

[0048] According to other embodiments, the package component 20 is an interposer wafer that has no active devices and may or may not include passive devices. According to another embodiment, the package component 20 is a package or includes a package, such as an integrated fan-out (InFO) package. For example, the package component 20 may be a reconstructed wafer that includes device dies and / or wafers bonded together and encapsulated in a molding compound (e.g., a molding compound). The package component 20 may also be a silicon carrier that has no metal components and active devices therein.

[0049] In the subsequent description, a device wafer (which may include electronic devices and / or photonic devices) is used as an example of the package component 20, and the package component 20 may also be referred to as a bottom wafer 20. The embodiments may also be applicable to an interposer wafer, a reconstructed wafer, a separated package, a separated device die, a separated interposer die, etc.

[0050] The package component 20 may have multiple crystal grains, and some characteristic components of one of the crystal grains are shown. According to some embodiments of the present disclosure, the wafer 20 includes a semiconductor substrate 24 and characteristic components formed at the upper surface of the semiconductor substrate 24. The semiconductor substrate 24 may be or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, or the like. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0051] According to some embodiments of the present disclosure, the wafer 20 includes an integrated circuit device 26 formed at the upper surface of the semiconductor substrate 24. According to some embodiments of the present disclosure, the integrated circuit device 26 may include a complementary metal oxide semiconductor (CMOS) transistor, a resistor, a capacitor, a diode and / or the like. Details of the integrated circuit device 26 are not shown here.

[0052] An interlayer dielectric (ILD) layer 28 is formed on the semiconductor substrate 24 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments of the present disclosure, the interlayer dielectric (ILD) layer 28 is formed of phospho silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride or the like or includes these materials. The interlayer dielectric (ILD) layer 28 can be formed by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0053] The contact plug 30 is formed in the interlayer dielectric (ILD) layer 28 and is used to electrically connect the integrated circuit device 26 to the metal lines and vias above. According to some embodiments of the present disclosure, the contact plug 30 is formed of or includes a conductive material. The conductive material is selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0054] The interconnect structure 32 is formed above the interlayer dielectric (ILD) layer 28 and the contact plug 30. The interconnect structure 32 may include metal lines 34 and vias 36, which are formed in a dielectric layer 38 (also referred to as an inter-metal dielectric (IMD) layer). The metal lines at the same level are collectively referred to as metal layers below. According to some embodiments of the present disclosure, the interconnect structure 32 includes a plurality of metal layers connected via vias 36. The metal lines 34 and vias 36 may be formed of copper, a copper alloy and / or another metal. According to some embodiments of the present disclosure, the dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be less than about 3.5. The dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silicate (Hydrogen Silses Quioxane HSQ), methyl silicate (Methyl Silses Quioxane, MSQ), etc.

[0055] The interconnect structure 32 may also include a passivation layer on the low-k dielectric layer, which may be formed of a non-low-k dielectric material. The passivation layer may be formed of or include undoped silicate glass (USG), silicon nitride, silicon oxide, or the like, or multiple layers thereof. It may also have a metal pad (e.g., an aluminum-copper pad), a post-passivation interconnect (PPI), a metal pad, or the like, which is referred to as a conductive feature.

[0056] Figure 1 A photonic device 40 is also shown, which represents a plurality of photonic devices 40 that may be formed within the bottom wafer 20, according to some embodiments of the present disclosure. In addition, the photonic device 40 may also be formed within a plurality of dielectric layers of the bottom wafer 20. According to some embodiments, the photonic device 40 may include a waveguide (e.g., a silicon waveguide and / or a silicon nitride waveguide), a grating coupler, a modulator, or the like. According to other embodiments, the bottom wafer 20 may be free of photonic devices.

[0057] Please refer to further Figure 1, the bonding film layer 42 is deposited above the interconnect structure 32. The upper surface of the bonding film layer 42 is coplanar. The bonding film layer 42 may be a blanket dielectric layer, in which there are no conductive features (e.g., wires and conductive pads). Alternatively, the bonding film layer 42 may have bonding pads. According to some embodiments of the present disclosure, the entire bonding film layer 42 is a homogeneous layer with a uniform composition. In the full description, when two feature components (e.g., two film layers) are referred to as having the same composition, it means that the two feature components have the same type of elements, and the percentages of corresponding elements in the two feature components are the same as each other. Conversely, when two feature components are referred to as having different compositions, it means that one of the two feature components has at least one element that is not present in the other feature component, or the two feature components have the same element, but the percentages of the elements in the two feature components are different from each other.

[0058] According to some embodiments of the present disclosure, the bonding film layer 42 may be formed of a silicon-based dielectric material, which may include one or more of oxygen, carbon, and nitrogen. According to other embodiments, depending on the material of the top wafer to be bonded to the bottom wafer 20, the material of the bonding film layer 42 may be another material other than the silicon-containing dielectric material.

[0059] When the bonding film layer 42 is formed of a silicon-based dielectric material, it can be represented as SiO x N y C z , wherein x is approximately in the range of 0 to 2, y is approximately in the range of 0 to 1.33, and z is approximately in the range of 0 to 1, and x, y, and z will not all be 0. For example, the bonding film layer 42 may be formed of SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like or include these materials. According to some embodiments of the present disclosure, the bonding film layer 42 may be light-transmissive.

[0060] Figure 2 A top wafer 120 is shown according to some embodiments of the present disclosure. The top wafer 120 may be a device wafer, which may include an integrated circuit therein, and may include transistors, resistors, diodes, capacitors, or the like. According to some embodiments, the top wafer 120 may include a semiconductor substrate, wherein the back surface of the semiconductor substrate faces upward. The integrated circuit may be formed at the lower surface of the semiconductor substrate. There may or may not be a through-via (also referred to as a through-silicon via electrode or a semiconductor through-via electrode, not shown) extending from the bottom of the semiconductor substrate to an intermediate height between the upper surface and the bottom of the semiconductor substrate. According to some embodiments, the semiconductor substrate may include silicon.

[0061] According to other embodiments, the top wafer 120 may be a blank wafer without active devices and passive devices therein. The top wafer 120 includes a substrate 124 and may or may not include a bonding film layer 122 (which is a dielectric layer 122) located on top of the top wafer 120. In the exemplary embodiments described below, the substrate 124 includes a material that can be used to form a photonic device, such as a waveguide, a grating coupler, a modulator, and / or the like. For example, the substrate 124 may be formed of or include silicon, lithium niobate (LiNbO3), or the like. According to some embodiments, the substrate 124 may have a single crystal structure.

[0062] According to some embodiments, the dielectric layer 122 is formed on the upper surface of the substrate 124. According to some embodiments, the dielectric layer 122 is formed by bonding the film layer 42 ( Figure 1 ) is formed by a material that forms a strong bond. The dielectric layer 122 is referred to as the bonding film layer 122 below. According to some embodiments, the bonding film layer 122 is formed of or includes a silicon-based dielectric material, which can also be represented as SiO x N y C z , wherein x is approximately in the range of 0 to 2, y is approximately in the range of 0 to 1.33, and z is approximately in the range of 0 to 1, and x, y, and z are not all 0. For example, the bonding film layer 42 may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like. .

[0063] According to some embodiments of the present disclosure, the bonding film layer 122 may be light-transmissive. The bonding film layer 122 may be formed by a deposition process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or a similar deposition process. According to other embodiments, the bonding film layer 122 is not formed, and the substrate 124 may be directly bonded to the bonding film layer 42 in a subsequent bonding process.

[0064] According to some embodiments, the top wafer 120 includes a homogeneous base 124 and does not include other film layers, and a dielectric layer 126 may also be formed, and the dielectric layer 126 may be formed in the same formation process as the bonding film layer 122. For example, the bonding film layer 122 and the dielectric layer 126 may be formed by oxidation, nitridation, and / or the like.

[0065] Please refer to further Figure 2 , an implantation process is performed to implant dopants into the substrate 124. The corresponding process is shown as follows Fig.10 Process step 202 in process flow 200 is shown. Dopants may include hydrogen ions, helium ions, or the like. Dopants are implanted to a height intermediate between the upper surface and the lower surface of substrate 124 and implanted to the location of wafer 120 to be cut. The implanted dopants are concentrated at a height intermediate the substrate 124 to form implantation layer 130. Dopants may be selected depending on the material of substrate 124. For example, when substrate 124 includes silicon, hydrogen may be selected, and when substrate 124 includes lithium niobate, helium may be selected.

[0066] Next, please refer to Figure 3 , the top wafer 120 is turned upside down, and the top wafer 120 is bonded to the bottom wafer 20 by wafer-to-wafer bonding, thereby forming a composite wafer 50. The corresponding process is shown as follows Fig.10 The process step 204 in the process flow 200 shown. The above bonding may include a pre-bonding process, in which the center point of the top wafer 120 contacts the center point of the bottom wafer 20, and the contact is propagated to the entire top wafer 120 and the bottom wafer 20. Then, an annealing process may be performed to bond the top wafer 120 to the bottom wafer 20. When the bonding film layer 122 is formed, the bonding film layer 122 is bonded to the bonding film layer 42. Alternatively, when the bonding film layer 122 is not formed, the substrate 124 may be directly bonded to the bonding film layer 42.

[0067] According to some embodiments, Figure 2 and 3 As shown, the top wafer 120 is patterned to form the implant layer 130 first, and then the patterned top wafer 120 is bonded to the bottom wafer 20. According to other embodiments, the top wafer 120 is bonded to the bottom wafer 20, and then the implantation process 46 is performed to form the implant layer 130 in the top wafer 120.

[0068] Please refer to Figure 4A , the composite wafer 50 is placed on the rotating chuck platform 52. The center of rotation is also aligned with the center of the top wafer 120 and the bottom wafer 20. The rotating chuck platform 52 is used to rotate the composite wafer 50, and the composite wafer 50 does not vibrate vertically during its rotation. In other words, when the composite wafer 50 rotates, the entire upper surface of the top wafer 120 remains at the same height without moving up and down.

[0069] The composite wafer 50 rotates around the center. According to some embodiments, the laser beam generator 54 is used to generate the laser beam 56, and the laser beam 56 is irradiated onto the side wall of the top wafer 120. Similarly, the laser beam 56 is irradiated onto the implant layer 130. At the same time, the laser beam 56 is irradiated onto the implant layer 130. When the composite wafer 50 is irradiated onto the implant layer 130, the composite wafer 50 is rotated. According to some embodiments, the laser beam generator 54 is fixed in place and does not move when the laser beam 56 is irradiated onto the top wafer 120.

[0070] The laser beam 56 heats the irradiated area and can generate stress concentration areas 58 in the implanted layer 130. As the composite wafer 50 rotates, the stress concentration areas 58 form a ring around the periphery of the top wafer 120. The stress concentration areas 58 on the left and right sides of the top wafer 120 are shown in a cross section that cuts off the center of the top wafer 120. Since the composite wafer 50 does not vibrate vertically during rotation, the ring is located in a plane parallel to the bonding interface between the bottom wafer 20 and the top wafer 120.

[0071] According to some embodiments, Figure 4A As shown, the laser beam 56 is irradiated in a direction parallel to the plane of the bonding interface between the bottom wafer 20 and the top wafer 120. Figure 4B In the embodiment, the laser beam 56 is irradiated in a direction that forms an acute angle with the interface between the bottom wafer 20 and the top wafer 120. According to yet another embodiment, the laser beam generator 54 may be rotated as shown. When the laser beam generator 54 rotates, the laser beam 54 may irradiate the same point, or, when the laser beam 54 rotates downward, the irradiation point on the top wafer 120 moves slightly downward. This may help to generate a notch having a triangular cross-sectional shape.

[0072] Please refer to Figure 5 , the notch 60 is formed by heating via the laser beam 56. The corresponding process is shown as follows Fig.10 The process step 206 in the process flow 200 is shown. The notch 60 forms a ring extending inward from the sidewall of the top wafer 120. According to some embodiments, the notch 60 has a triangular cross-sectional shape with its tip pointing to the other side of the notch 60. The tip also forms a ring. The tip is where stress is concentrated and is most likely to cause cracks. Therefore, in the case where the tip is generated at the same height as the tip ring, the location of the subsequent crack can be accurately determined.

[0073] According to some embodiments, the notch 60 is formed as a ring due to the rotation of the composite wafer 50. According to some embodiments, the rotation speed of the composite wafer 50 is low. Therefore, the notch 60 is generated when the composite wafer 50 rotates. When the top wafer 120 rotates a full circle, a notch ring is formed, which is also represented by the reference numeral 60. The composite wafer 50 can continue to be rotated and burned by the laser beam 54, and the notch 60 can be expanded in subsequent rotations. According to some embodiments, when the notch 60 is completed, the lateral depth LD1 can be greater than 1 μm, and can be approximately in the range of 10 μm to 500 μm.

[0074] According to other embodiments, the composite wafer 50 is rotated at a high speed. Therefore, in one rotation, the protruding portion of the top wafer 120 is heated, but no notch is formed in the first rotation. As the top wafer 120 continues to rotate, the temperature of the protruding area increases, and the notch 60 is eventually formed. The notch 60 also expands in subsequent rotations of the top wafer 120.

[0075] According to other embodiments, the notch 60 is not formed using the laser beam 54, but is formed by a mechanical cutting process. Figure 4C As shown, the blade 62 can be used to cut into the top wafer 120 from the side to form the notch 60. When the blade 62 cuts into the side of the top wafer 120, the top wafer 120 also rotates, so the notch 60 also forms a ring. According to some embodiments, the portion of the blade 62 that cuts into the top wafer 120 has a triangular shape, so that the resulting notch 60 also has a triangular cross-section.

[0076]

[0040] According to yet another embodiment, rather than forming a notch ring, a laser beam 54 is used to create a stress concentration area 58, such as Figure 4A According to these embodiments, when the composite wafer 50 is heated to cut the top wafer 120, as explained in the subsequent paragraphs, no notches are formed in the implanted layer 130. The stress concentration area 58 is therefore a burn area (burn ring) and is an uncut portion of the top wafer 120. The sidewalls of the top wafer 120 can therefore remain straight or curved, the same as before receiving the laser beam 56.

[0077] Please refer to Figure 6 , heating the composite wafer 50 to perform a dicing process so that the top wafer 120 is separated into a top portion and a bottom portion. The corresponding process is shown as follows Fig.10Process step 208 in process flow 200 is shown. According to some embodiments, composite wafer 50 moves to heating unit 64, which heats composite wafer 50 from the bottom. According to other embodiments, composite wafer 50 is heated from the top, for example, by radiation 65 generated by a heat source (e.g., a lamp), or is heated from the top and the bottom simultaneously. According to some embodiments, during the heating process, top wafer 120 is heated to a temperature in the range of about 200° C. to 300° C. The heating duration may be in the range of about 0.5 hours to 10 hours, depending on the material of substrate 124, the concentration of implanted dopants, etc.

[0078] As the heating process proceeds, cracks are generated where stress is concentrated. The implanted layer 130 is where the substrate 124 is weakened and where stress is more concentrated. In addition, due to the formation of the stress concentration area, cracks are more likely to be generated and propagated (in a shorter time and / or at a lower temperature). According to some embodiments, as the notch ring 60 is formed, cracks extending from the notch ring 60 are generated and propagate inward along the implanted layer 130 until they meet the cracks that propagated from the notch ring 60, and the top and bottom of the top wafer 120 are separated, as shown in FIG. Figure 7 According to some embodiments, where the notch 60 has a tip, for example, when the notch 60 has a triangular cross-sectional shape, the crack will propagate from the tip of the notch 120. Thus, the position where the wafer dicing occurs is precisely controlled.

[0079] According to other embodiments, as shown in FIG. Figure 4A As illustrated, the stress concentration region 58 is formed as a ring using the laser beam 56, while no notch is formed in the region where the laser beam 56 irradiates the top wafer 120. Figure 6 During the subsequent heating process shown, cracks may also originate from stress concentration areas 58, which are also located within the weakened implant layer 130. The cracks propagate along the implant layer 130 to separate the top from the bottom.

[0080] Figure 7 The structure after the wafer dicing process is shown, in which the top portion 120T of the top wafer 120 is separated from the bottom portion 120B. According to some embodiments in which the notch 60 is formed, the notch 60 is divided into the top wafer portion 120T and the bottom wafer portion 120B. Therefore, the edge portions of the top wafer portion 120T and the bottom wafer portion 120B have grooves. For example, at the edge portion of the top wafer portion 120T, there may be a small inclined lower surface, and at the edge portion of the bottom wafer portion 120B, there may be a small inclined upper surface.

[0081] Fig. 9The dopant concentration profile of the implanted dopant is schematically shown as a function of depth, where the depth is measured downward from the upper surface of the top wafer 120. It can be understood that the dopant concentration in the implanted region 130 has a certain distribution, with the highest dopant concentration at a position close to the implanted layer 130 or at a mid-height, and the dopant concentration gradually decreases at a position away from the highest dopant concentration. According to some embodiments, Figure 5 The notch 60 (or Figure 4A and 4B The stress concentration region 58 in the notch 60 is aligned with the location where the dopant concentration is the highest. For example, when the notch 60 has a tip, the tip is aligned with the location where the dopant concentration is the highest, which is also the location where the substrate 124 has the weakest structure. In this way, cracks starting from the notch 60 or the stress concentration region 58 are less likely to deviate upward and downward, and the bottom portion 120B ( Figure 7 ) has a flatter upper surface.

[0082] Figure 8 Schematically shows the Figure 7 More features 68 are formed by the structure shown. For example, it is possible to flatten Figure 7 The bottom portion 120B in the embodiment of the present invention is formed to have a flat surface. The corresponding process is shown as follows Fig.10 The process step 210 in the process flow 200 shown in FIG. 2 may include a chemical mechanical polishing (CMP) process or a mechanical grinding process. The planarized bottom portion 120B may then be patterned to form a plurality of photonic devices 70, which may include grating couplers, waveguides, modulators, and / or the like. The corresponding process is shown as follows: Fig.10 The process step 212 in the process flow 200 is shown. The photonic device can be a silicon-based device, a lithium niobate-based device, or the like. More features can be formed on the photonic device 134. Fig.10 As shown, the corresponding process is shown as Fig.10 Process step 214 of process flow 200 is shown. According to some embodiments, a plurality of transparent dielectric layers 74, nitride waveguides (not shown), microlenses 72, etc. are formed.

[0083] It should be understood that although the example of cutting a wafer to form a photonic device is used, the embodiments can be applied to the cutting of wafers of any other structure as long as it is applicable. For example, when bonding two device wafers, one of which includes a through substrate via electrode (TSV), the embodiments of the present disclosure can be used to cut the semiconductor substrate having the through substrate via electrode (TSV) therein, followed by a thinning process to expose the through substrate via electrode (TSV).

[0084] The embodiments of the present disclosure have some advantageous features. By forming a stress concentration area (e.g., a notch) in the implanted layer of the wafer, cracks can be generated from the notch, making the wafer cutting process more accurate. Furthermore, cracks can be generated under reduced heating time and / or heating temperature.

[0085] According to some embodiments of the present disclosure, a wafer cutting method includes: implanting a substrate with a dopant to form an implantation layer in the substrate, wherein the implantation layer is located at an intermediate height between the upper surface and the lower surface of the substrate; irradiating the implantation layer with a laser beam, wherein the laser beam is irradiated on a side wall of the substrate; and after irradiating the laser beam, heating the substrate to separate the substrate at the implantation layer, wherein the substrate is separated into a top portion and a bottom portion.

[0086] In one embodiment, the laser beam causes a notch ring to be formed in the substrate, and the notch ring extends laterally from the side wall of the substrate into the substrate. In one embodiment, in a cross-sectional view of the substrate, the notch ring has a tip pointing to the center of the substrate. In one embodiment, the implanted layer includes: a middle portion having a dopant with a highest doping concentration; a top portion located above the middle portion; and a bottom portion located below the middle portion, wherein the dopant concentration of the top portion and the bottom portion is lower than that of the middle portion, and wherein the laser beam is irradiated on the middle portion. In one embodiment, when the substrate is initially heated, the portion of the substrate that receives the laser beam is retained, and the stress concentration area has been formed as part of the substrate. In one embodiment, the substrate is cut at the stress concentration area.

[0087] In one embodiment, the substrate has a single crystal structure. In one embodiment, the substrate is contained in a top wafer, and the method further comprises bonding the top wafer to a bottom wafer. In one embodiment, after cutting the substrate, the bottom portion of the substrate remains bonded to the bottom wafer. In one embodiment, the method further comprises planarizing the bottom portion of the substrate. In one embodiment, the method further comprises patterning the bottom portion of the substrate after planarizing the bottom portion of the substrate to form a plurality of photonic devices. In one embodiment, the substrate comprises a silicon substrate. In one embodiment, the substrate comprises a lithium niobate substrate.

[0088] According to some embodiments of the present disclosure, a wafer cutting method includes: implanting a substrate with a dopant to form an implantation layer in the substrate, wherein the implantation layer is located at an intermediate height between the upper surface and the lower surface of the substrate; cutting the substrate to form a notch, wherein the notch extends into the implantation layer; and after forming the notch, heating the substrate to separate the substrate at the notch.

[0089] In one embodiment, the substrate is cut using a laser beam. In one embodiment, the substrate is cut using a blade. In one embodiment, the method further includes bonding the substrate to a bottom wafer to form a composite wafer; and rotating the composite wafer, wherein the notch is formed while the composite wafer is rotated.

[0090] According to some embodiments of the present disclosure, a wafer dicing method includes: bonding a top wafer to a bottom wafer, wherein the top wafer includes a substrate, and wherein the substrate includes an implanted layer having a dopant; forming a high stress region in the substrate, wherein the high stress region extends laterally in the implanted layer; and forming a crack starting from the high stress region, wherein the crack propagates laterally from the crack to separate the top wafer into a top portion and a bottom portion. In one embodiment, forming the high stress region includes forming a notch ring using a laser beam. In one embodiment, forming the high stress region includes forming a burn region using a laser beam.

[0091] The above briefly describes the characteristic components of several embodiments of the present disclosure, so that those skilled in the art can more easily understand the form of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the concept and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the concept and scope of the present disclosure.

Claims

1. A wafer cutting method, comprising: implanting a substrate with a dopant to form an implant layer in the substrate, wherein the implant layer is located at an intermediate height between an upper surface and a lower surface of the substrate; irradiating the implantation layer with a laser beam, wherein the laser beam irradiates a side wall of the substrate; as well as After irradiating the laser beam, the substrate is heated to separate the substrate at the implantation layer, wherein the substrate is separated into a top portion and a bottom portion. 2 . The wafer dicing method of claim 1 , wherein the laser beam causes a notch ring to be formed in the substrate, and wherein the notch ring extends laterally from the sidewall of the substrate into the substrate.

3. The wafer dicing method according to claim 1, wherein the implanted layer comprises: a middle portion having a dopant with the highest doping concentration; a top portion located above the middle portion; as well as A bottom portion is located below the middle portion, wherein the top portion and the bottom portion of the implanted layer have a lower dopant concentration than the middle portion, and wherein the laser beam is irradiated on the middle portion.

4. The wafer dicing method as claimed in claim 1, wherein when the substrate starts to be heated, a portion of the substrate receiving the laser beam is retained, and a stress concentration area has been formed as a portion of the substrate. The wafer dicing method as claimed in claim 1 , wherein the substrate comprises a silicon substrate.

6. A wafer cutting method, comprising: implanting a substrate with a dopant to form an implant layer in the substrate, wherein the implant layer is located at an intermediate height between an upper surface and a lower surface of the substrate; cutting the substrate to form a notch, wherein the notch extends into the implant layer; as well as After forming the notch, the substrate is heated to separate the substrate at the notch.

7. The wafer dicing method as claimed in claim 6, wherein a laser beam is used to diced the substrate.

8. The wafer cutting method according to claim 6, further comprising: bonding the substrate to a base wafer to form a composite wafer; as well as The composite wafer is rotated, wherein the recess is formed while the composite wafer is rotated.

9. A wafer cutting method, comprising: bonding a top wafer to a bottom wafer, wherein the top wafer comprises a substrate, and wherein the substrate comprises an implanted layer having a dopant; forming a high stress region in the substrate, wherein the high stress region extends laterally into the implant layer; as well as A plurality of cracks are formed starting from the high stress region, wherein the plurality of cracks propagate laterally from the plurality of cracks to separate the top wafer into a top portion and a bottom portion. 10 . The wafer dicing method as claimed in claim 9 , wherein forming the high stress area comprises forming a notch ring using a laser beam.

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