Dielectric materials and molding compounds having different dielectric constants coupled to die including integrated circuit system

Abstract

Implementations herein relate to systems, devices, techniques, or processes for reducing the capacitance of a package including a die by at least partially enclosing the die in molding compounds and dielectric materials having different dielectric constants. Other embodiments may be described and / or claimed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to the field of package assemblies, and more particularly to package assemblies including a die at least partially encapsulated within a mold compound. Background Art

[0002] During the manufacture of a computing system, the package containing the die that includes the integrated circuit system is physically and electrically coupled to other system components (e.g., an interposer, substrate, or motherboard). During shipping and / or handling of the package, charge may accumulate within the package due to the high capacitance of the package relative to the ground plane. The capacitance of a package is the primary determinant of the charged device model (CDM) of the package. The CDM is a model used to characterize the susceptibility of a packaged integrated circuit (IC) to damage caused by electrostatic discharge.

[0003] When the package is physically and electrically coupled to other components on the assembly line, a short-term, high-amperage electrostatic discharge or spark may be generated between the package and the conductive components of the assembly line. For example, the duration of a CDM electrostatic discharge can be several nanoseconds (ns) with a rise time in the range of 100-300 picoseconds (ps). The rise of the portion of the CDM current pulse can be as fast as 20-30ps, and during this time, the resulting current can be several amperes at 250 volts, depending on the capacitance of the package.

[0004] Although this electrostatic discharge lasts for a short period of time, the large voltage drop generated by the discharge may cause damage to devices within the packaged IC. Such damage may include, for example, damage to transistor structures (e.g., gate oxide, interlayer dielectric, etc.) within the packaged die. Such damage may result in increased yield loss and, as a result, increased overall manufacturing costs.

[0005] As a result, the die or chip within the package often includes an ESD protection device, which may be referred to as an electrostatic discharge (ESD) protection structure, located within the die or chip close to the integrated circuit system (which may also be referred to as the electrical circuit system) to mitigate damage caused by high voltage electrostatic discharge during assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An older package is shown having a die including an integrated circuit with an ESD protection device, a redistribution layer, and a ball grid array (BGA) on the redistribution layer.

[0007] Figures 2A-2D Included are exemplary diagrams and circuitry for characterizing the CDM of a package, and graphs of exemplary CDM waveforms during testing.

[0008] Figures 3A-3IVarious cross-sectional side and cross-sectional top-down views of dielectric materials and molding compounds having different dielectric constants coupled to a die are shown according to various embodiments.

[0009] Figures 4A-4F Cross-sectional side views of stages in a manufacturing process for creating a package including dielectric materials with different dielectric constants and a mold compound coupled to a die are shown according to various embodiments.

[0010] Figure 5 An example of a process for creating a package including dielectric materials with different dielectric constants and a mold compound coupled to a die is shown in accordance with various embodiments.

[0011] Figure 6 A computing device according to an embodiment is schematically illustrated. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure may generally relate to systems, devices, and / or processes for reducing the capacitance of a package and, as a result, reducing the peak CDM current of the package. In an embodiment, a package may include a die including one or more ICs located within the die, wherein the die is at least partially surrounded by a combination of a molding compound and a dielectric material. In an embodiment, the molding compound may be referred to as a molding. In an embodiment, the molding compound and the dielectric material have different dielectric constants. For example, the molding compound may have a higher dielectric constant than the dielectric material. In an embodiment, the molding compound may partially surround the die, and the dielectric material may be located on the molding compound. In other embodiments, portions of the molding compound and / or the dielectric material may both be close to the die, and / or may be in direct physical contact with the die.

[0013] In an embodiment, the presence of dielectric material close to the die can reduce capacitance in the package, and as a result, a reduced size of the electrostatic discharge protection device within the die can be obtained. When the package is electrically and / or physically coupled to another component during system manufacturing, the electrostatic discharge protection device can be used to prevent high current discharges associated with ESD and associated subsequent device damage.

[0014] By implementing a reduced size electrostatic discharge protection device within the die, this can reduce the high capacitance load of the signal routed within the die, thereby improving the die and package performance. Moreover, electrical leakage can be reduced, thereby reducing the total power requirement of the integrated circuit, and the size of the die can also be made smaller. The capacitive load can be reduced by reducing the size of the ESD protection device, thereby significantly improving the performance of the high-speed interface, because the peak CDM current will be reduced. In addition, the noise coupling with the surrounding can be reduced because we have now reduced the package capacitance. In an embodiment, the material of the molding compound can include a dielectric material.

[0015] In the detailed description below, reference will be made to the accompanying drawings that constitute part of the detailed description, wherein similar parts are represented by similar reference numerals throughout, and wherein embodiments of the subject matter of the present disclosure are shown by way of example. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limited sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0016] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0017] The description may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are merely used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0018] The description may use the phrase "in an embodiment", which may refer to one or more embodiments of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in connection with the embodiments of the present disclosure are synonymous.

[0019] The term "coupled with" may be used herein, along with its derivatives. "Coupled" may mean one or more of the following meanings. "Coupled" may refer to two or more elements being in direct physical or electrical contact. However, "coupled" may also refer to two or more elements being in indirect contact with each other, but still cooperating or interacting with each other, and may refer to one or more other elements being coupled or connected between elements referred to as being mutually coupled. The term "directly coupled" may refer to two or more elements being in direct contact.

[0020] Various operations may be described as multiple discrete operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be inferred to imply that these operations are necessarily order dependent.

[0021] As used herein, the term "module" may refer to, include, or be part of: an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other appropriate components that provide the described functionality.

[0022] Various figures herein may depict one or more layers of one or more packaged components. The layers depicted herein are depicted as examples of relative positions of layers of different packaged components. The layers are depicted for purposes of explanation and are not drawn to scale. Therefore, relative sizes of layers should not be assumed from the figures, and for some embodiments, sizes, thicknesses, or dimensions may be assumed only where specifically indicated or discussed.

[0023] Various embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon, which, when executed, cause the actions of any of the embodiments described above. In addition, some embodiments may include a device or system having any appropriate module units for implementing the various operations of the embodiments described above.

[0024] Figure 1 An old package is shown with a die including an integrated circuit with an ESD protection device, a redistribution layer, and a ball grid array (BGA) on the redistribution layer. Package 100 shows a cross-sectional side view of an old package including a die 102. Die 102 includes an integrated circuit system 104, which may include, but is not limited to, transistors, capacitors, and / or other active or passive circuit systems. Integrated circuit system 104 may be distributed in various portions of die 102. Integrated circuit system 104 may include metal and / or other structures that may contribute to the capacitance of package 100.

[0025] The die 102 may also include an ESD protection device 106. In an embodiment, the ESD protection device 106 may include, but is not limited to, a single diode, a dual diode, a self-protected output driver for digital I / O, and / or a rail clip. Electrical connectors 108, which may include solder bumps and / or conductive pads, are located on one side of the die 102 and are electrically coupled to the integrated circuit system 104. Although Figure 1Three different areas of the integrated circuit system 104 and two areas for the ESD protection device 106 are shown, but in an implementation, the integrated circuit system 104 and the ESD protection device 106 may appear anywhere within the die 102 .

[0026] The die 102 may be embedded or partially embedded within the mold compound 110. A redistribution layer (RDL) 120 may be located on the die 102 and electrically coupled to the die 102 using electrical connectors 108. The RDL 120 may include various electrical routings 114 that electrically couple the electrical connectors 108 located on a first side of the RDL 120 to a ball grid array (BGA) 116 located on a second side of the RDL 120 opposite the first side. In an embodiment, an underfill 112 may be disposed between the die 102 and the RDL 120, and between the electrical connectors 108.

[0027] In an embodiment, ESD protection device 106 may be used to protect integrated circuit system 104 of die 102 from ESD events that may occur during the manufacture of a computer system when assembling package 100 with another component, such as a motherboard (not shown). Figure 6 The structure of package 100 including die 102, integrated circuit system 104, and mold compound 110 establishes the capacitance of package 100. Specifically, each package 100 may have a capacitance characteristic or model, which may be referred to as a CDM, as discussed further below.

[0028] As package 100 is transported, e.g., along rollers on its way to an insertion machine, electrostatic charge may build up in package 100, depending on the CDM of package 100. When one of BGAs 116 contacts a conductive component (e.g., a metal pin of a motherboard (not shown) or any other conductive component) during insertion onto the motherboard, any electrostatic charge built up within package 100 will be immediately discharged into the conductive component.

[0029] The ESD event can be a very fast event that causes a large voltage drop across the package 100 at a very high current rate. The total time of the event is about 1-2ns or less, and can be as short as 20 to 300ps. The current generated can be very high, in some packages, in the range of 5-6 amps at 250V charging. For packages used in automotive computing systems, the amperage can be as high as 10 to 15 amps at 500V charging.

[0030] In the case of a high current discharge, a large voltage drop may be generated, which may cause damage to the integrated circuit system 104. For example, it may include damage to the gate oxide, source and / or drain, parasitic bipolar junctions, and / or interlayer dielectrics of the metal oxide semiconductor (MOS) device. Note that when the package 100 is coupled to a motherboard (not shown), there may be board-level protection against electrostatic discharge, and when the motherboard (not shown) is inserted into a system (not shown), the system may have system-level ESD protection, including shielding and a system chassis for discharge.

[0031] In legacy implementations, the ESD protection device 106 within the die 102 is made large enough so that the CDM (based on the capacitance of the package 100) meets a target standard to be able to handle a threshold current during an ESD event during manufacturing. The threshold current can be expressed as a breakdown voltage of the package 100. If the CDM target requirement is not met, the yield loss of the package 100 can exceed 3% to 4%, and in some implementations can exceed 20%.

[0032] A substantial amount of the capacitance of the package 100 is contributed by the mold compound 110 surrounding the die 102. The mold compound 110 may be included to provide structural stability and / or thermal conductivity properties to the die 102. In embodiments, the typical dielectric constant of the mold compound 110 may be greater than or equal to 4. In these embodiments, as the size of the package 100 increases, the size and complexity of the ESD protection device 106 may also need to increase. However, the increase in the size of the ESD protection device 106 may result in some trade-offs.

[0033] For example, the increased size or number of ESD protection devices 106 may add additional capacitance or may burden high-speed interfaces and affect the frequency of input / output (I / O) that may be achieved through electrical connectors 108 on die 102. For example, high-speed I / O that may be transmitted at 50 or 100 gigabits per second may be subject to increased noise within integrated circuit system 104 or electrical connectors 108. In addition, large ESD protection devices 106 may also increase the amount of electrical leakage within die 102 and may increase the overall size of die 102.

[0034] Thus, in an embodiment, by reducing the amount of the mold compound 110 having a higher dielectric constant proximate to the die 102 , the size of the ESD protection device 106 may be reduced without necessarily reducing the CDM requirements of the package 100 .

[0035] Figures 2A-2D Included are exemplary diagrams and circuitry for characterizing the CDM of a package and graphs of exemplary CDM waveforms during testing. Figure 2AA diagram of a system for measuring the CDM of a package 200 is shown. The package 200 may be used with Figure 1 2. The package 200 may be similar to the package 100 of FIG. 2. The package 200 may be located on a dielectric layer 252, which may be located on a field plate 250. In an embodiment, the field plate 250 may be electrically coupled to a charging resistor 254, which may be switched to connect to a high voltage power supply 258 using a switch 256. In an embodiment, either may be coupled to a ground plane 260. The ground plane 260 is electrically connected to a pogo pin 262 through a one ohm resistor 264, and the resistance and inductance of the spark and the pogo pin 262 may be coupled to a 50 ohm input of an oscilloscope (not shown) using a 50 ohm coaxial cable 266.

[0036] During operation, package 200 will be charged to a high voltage, for example, 250 volts. Once package 200 is fully charged, spring pins 262 will be connected to BGA 216 (which can be connected to Figure 1 The solder balls of BGA 116 (similar to BGA 116) are measured, and package 200 is discharged through the solder balls of BGA 216. Afterwards, the resulting discharge is measured. This process can be repeated for each of the solder balls on package 200, and the values ​​of each test will be combined to determine the CDM of package 200.

[0037] Figure 2B Shows Figure 2A Equivalent circuit diagram of the CDM test environment shown in . Figure 2B The field plate 250, the dielectric layer 252 on the field plate 250, and the package 200 on the dielectric layer 252 are shown. Sub-figure 262a is a graph showing the spark resistance, inductance, and electrical coupling with the solder ball 217. Figure 2A The equivalent diagram of the resistance of the spring pin 262, the solder ball 217 can be Figure 2A Subgraph 262a is shown electrically coupled to ground plane 260 and one ohm resistor 264.

[0038] The capacitance shown at CDUT 270 is the capacitance of package 200, which may also be referred to as a device under test (DUT). The capacitance shown at CDG 272 is shown as the capacitance between package 200 and ground plane 260. The capacitance shown at CFG 274 is the capacitance between field plate 250 and ground plane 260. Figure 2B As shown in , any charge held in the capacitance shown at CDUT 270 is discharged to ground plane 260 via the spark shown in subgraph 262a and one ohm resistor 264. During testing, this process can be done for both positive and negative polarities.

[0039] Figure 2CAn arbitrary discharge waveform 280, which may be referred to as a CDM stress waveform, is shown, with the y-axis 276 of the graph showing the current in amperes plotted against the x-axis 278 showing time in nanoseconds. As shown, Figure 2B The package 200 has been charged to 250 volts. The resulting waveform 280 is an oscillating waveform with an exponentially decreasing amplitude. For example, the waveform 280 shows a first peak 282 of approximately 6 amps and a second peak 284 at -2.2 amps in the time range of 1-2 ns. It should be noted that Figure 2B Each of the solder balls 217 of the package 200 may have a different waveform, although the charge placed on the package 200 will be the same for each iteration.

[0040] Figure 2C indicates that the maximum current discharge is very high and the capacitance of package 200 or CDUT 270 is Figure 2B The dielectric layer 252 and the integrated circuit system in the package 200 (which can be Figure 1 The medium (eg, Figure 1 This is partly due to the relative dielectric constant / dielectric constant of the mold compound 110 having a value of 4 or greater.

[0041] The capacitance of a parallel plate capacitor is given by the following formula

[0042] C=ε0ε r A / d

[0043] where A is the area of ​​the plates, d is the separation distance between the plates, ε0 is the dielectric constant of free space, and ε r is the relative permittivity or dielectric constant, k, of the dielectric material between the plates.

[0044] Figure 2D Another illustration of package 200 on dielectric layer 252 on field plate 250 is shown. Package 200 includes mold compound 210, die 202, electrical connector 208, underfill 212, RDL 220, electrical routing 214, and BGA 216, which can be connected to Figure 1 The mold compound 110 , die 102 , electrical connectors 108 , underfill 112 , RDL 120 , electrical routing 114 , and BGA 116 of EMBODIMENT 1 are similar. Figure 2D Can be used with Figure 2A Region 271 includes individual sub-regions 270a, 270b, 270c, 270d, 270e, 270f, each of which has a respective capacitance that can be combined to identify the package 200. Figure 2BThe capacitance CDUT 270.

[0045] As a result, the CDM peak current depends on the package 200 capacitance CDUT 270, which also determines the amount of charge that can be stored in the package 200 including the IC (not shown). The capacitance CDUT 270 is proportional to the dielectric constant of the mold compound 210 (or any other substance) that may be located between the dielectric layer 252 and the RDL 220. In the old implementation, the mold compound 210 has a relative dielectric coefficient or dielectric constant greater than 4. For this reason, the generated capacitance can be very high, in the range of a few picofarads to tens of picofarads. Accordingly, as Figure 2C As shown in , the CDM peak current can be very high, in the range of several amperes.

[0046] Thus, in the old implementation, the charge stored in the package 200 can be large and the peak CDM current during ESD can be very high due to the high capacitance CDUT 270 of the package 200. To provide protection against the high voltage drop from ESD during package insertion, the ESD protection device (e.g., Figure 1 This results in a higher capacitive load on the signal within the package 200, a larger size of the package 200, and increased power leakage and higher power requirements of the package 200. These results can be attributed in part to the ESD protection device 106. These old implementations with high capacitive loads can be very disadvantageous for high-speed interfaces or low-power integrated circuits within the package 200.

[0047] Figures 3A-3I Various cross-sectional side views and cross-sectional top-down views of dielectric materials and molding compounds having different dielectric constants coupled to a die are shown according to various embodiments. Figures 3A-3I Low to ultra-low ε r Various embodiments of a (or k) layer, which may be in the form of a dielectric layer and may be patterned onto or coated onto a high-k molding compound layer to reduce the capacitance of the package, e.g. Figure 2D The capacitance CDUT 270.

[0048] Figure 3A Shows that it can be Figure 1 100. The package 300A includes a die 302, an integrated circuit system 304, an ESD protection device 306, an electrical connector 308, an underfill 312, an RDL 320, an electrical trace 314, a BGA 316, and a molding compound 310, which can be similar to the package 100 of FIG. Figure 1The die 102 , integrated circuit system 104 , ESD protection device 106 , electrical connector 108 , underfill 112 , RDL 120 , electrical routing 114 , BGA 116 , and mold compound 110 of FIG. 1 are similar.

[0049] Embodiments include a dielectric material 318 disposed on the mold compound 310. In embodiments, the dielectric material 318 may have a dielectric constant value that is less than the dielectric constant value of the mold compound 310. In embodiments, the mold compound 310 may have a dielectric constant value of approximately 4 or greater, and the dielectric material 318 may have a dielectric constant value of approximately 2 or less. In embodiments, the dielectric material 318 may be considered a low-k or ultra-low-k dielectric layer. In embodiments, the dielectric material 318 may be disposed on the mold compound 310. Figure 1 The height of the mold compound 310 may be reduced compared to the height of the mold compound 110 of the package 300A, so that the height of the mold compound 310 in addition to the height of the dielectric material 318 will cause the package 300A to have a height similar to that of the mold compound 110 of the package 300A. Figure 1 The package is similar to 100 in height.

[0050] In an embodiment, dielectric material 318 may be a layer having an arbitrary or varying thickness. In an embodiment, dielectric material 318 may have a non-uniform thickness. In an embodiment, dielectric material 318 may be composed of a plurality of dielectric materials, one or more of which may have a lower dielectric constant. In an embodiment, dielectric material 318 may be a layer substantially perpendicular to the surface of die 302. In other embodiments, dielectric material 318 may extend to or beyond at least one side of die 302, wherein the at least one side of the die is perpendicular or substantially perpendicular to the surface of die 302.

[0051] In an embodiment, the ESD protection device 306 within the die 302 may be smaller than Figure 1 The ESD protection device 106 in the die 102 is smaller than the CDM of the package 300A. Figure 1 This is attributed to the presence of the lower-k dielectric material 318 which reduces the overall capacitance of the package 300A. As a result, in an embodiment, the charge storage of the package 300A may be less than 100% due to the presence of the lower-k dielectric material 318. Figure 1 The size of the package volume is 100.

[0052] Figure 3B Shows that it can be Figure 3AFIG. 3 is a cross-sectional side view of a package 300B similar to package 300A, wherein dielectric material 318 is inserted into portions of mold compound 310. In an embodiment, portions 310a of mold compound may extend along the sides of dielectric material 318. In an embodiment, dielectric material 318 may be close to die 302, thereby reducing the total capacitance and, thus, the peak CDM discharge current of package 300B. In an embodiment, some portions 310a of mold compound may be left in place, thereby providing additional structural integrity and / or thermal properties to package 300B. In an embodiment, mold compound 310 may have a higher structural integrity than dielectric material 318.

[0053] Additionally, dielectric material 318 may have lower thermal conductivity properties than mold compound 310 and, therefore, may be less able to conduct heat away from die 302 during operation. As a result, a minimum thickness of mold compound 310 may be required between die 302 and dielectric material 318 to adequately dissipate heat from die 302. In some embodiments (not shown), a heat sink may be placed within mold compound 310 and / or within dielectric material 318 to conduct heat away from die 302.

[0054] Figure 3C Shows that it can be Figure 3B 300B, wherein dielectric material 318 is formed within a cavity in mold compound 310. However, unlike Figure 3B Differently, dielectric material 318 may not have any straight edges or planar sides within mold compound 310. In an embodiment, this structure may allow dielectric material 318 to be closer to a portion of die 302 that may include higher metallization and thus reduce the capacitance relative to that portion of die 302. As a result, the volume and shape of dielectric material 318 may be selected in a manner to customize a capacitance value for package 300C that may be unique to die 302.

[0055] Figure 3D Shows that it can be Figure 3B 300B, wherein the dielectric material 318 is broken into individual segments and inserted into the mold compound 310. In an embodiment, each of the individual segments may be separated by a portion 310a of the mold compound, which may be used to provide rigidity to the package 300D. In an embodiment, each of the individual segments of the dielectric material 318 may be placed on the die 302, which may include a metal structure (not shown) (which may be connected to the die 302). Figure 1In an embodiment, portions of dielectric material 318 may also extend beyond the edge of die 302. In an embodiment, dielectric material 318 may be filled into the interior of a cavity created within mold compound 310 during manufacture of package 300D.

[0056] Figure 3E Shows that it can be Figure 3D 300E, wherein a dielectric material 318 may be inserted into the mold compound 310. In an embodiment, a first section 310a of the mold compound may be located between sections of the dielectric material 318, and a second section 310b of the mold compound may be located above the dielectric material 318. In an embodiment, the second section 310b of the mold compound may provide additional stiffness to the package 300E. In an embodiment, the additional stiffness may allow additional forces to be applied to the top side of the package 300E during insertion, and / or reduce warping of the package 300E during insertion or operation. In an embodiment, the second section 310b of the mold compound may also provide thermal conductivity to provide an enhanced thermal path between the die 302 and the first section 310a of the mold compound to the second section of the mold compound 310b, to the top of the package 300E.

[0057] Figure 3F Shows that it can be Figure 3D Package 300D is a cross-sectional side view similar to package 300F, wherein dielectric material 318 may include air. Figure 3G Shows that it can be Figure 3D Package 300D is a cross-sectional side view similar to package 300G, wherein thermal paste 319 may be inserted between dielectric material 318 and mold compound 310. In an embodiment, thermal paste 319 may be any other type of thermally conductive material and may be placed on package 300F after the package is assembled onto a printed circuit board assembly.

[0058] Figure 3H Shows that it can be Figure 3D 300D is a cross-sectional top-down view of package 300H similar to that of package 300H. Individual sections of dielectric material 318 may be formed within mold compound 310 and may be separated by portions 310a of mold compound. Die 302 may be located below the individual sections of dielectric material 318 and may extend beyond the footprint of die 302.

[0059] Fig. 3I Shows that it can be Figure 3DPackage 300D is similar to a cross-sectional top-down view of package 300I, where individual sections of dielectric material 318 may be formed over only portions of die 302. In an embodiment, these individual sections of dielectric material 318 may be placed over locations within die 302 that have a higher contribution to the capacitance of package 300I, and mold compound 310 provides package rigidity and / or thermal properties.

[0060] It should be recognized that Figures 3A-3I is an example of an embodiment, but is not limiting of the application of dielectric material 318 within or on mold compound 310. Other embodiments may include mixing and matching the properties of dielectric material 318, mold compound 310, and / or other materials or cavities that may be inserted into the package to facilitate reduction of capacitance of the package.

[0061] Figures 4A-4F Cross-sectional side views of stages in a manufacturing process for creating a package including dielectric materials with different dielectric constants and a mold compound coupled to a die are shown according to various embodiments. Figure 4A 4 shows a stage in the manufacturing process where a die 402 is provided and electrical connectors 408 may be electrically and / or physically coupled to the die 402. The die 402 and electrical connectors 408 may be coupled to Figure 1 The die 102 and electrical connectors 108 are similar. In an embodiment, the electrical connectors 108 may be implemented as solder bumps, such as microbumps, or the electrical connectors 108 may be copper or other metal connections.

[0062] Figure 4B The manufacturing process is shown at a further stage, where the die 402 and electrical connectors 408 may be applied to the redistribution layer 420 (which may be connected to the Figure 1 In an embodiment, the redistribution layer 420 may include electrical routing 414 that may be electrically coupled to one or more of the electrical connectors 408. In an embodiment, an underfill 412 may be placed between the die 402 and the redistribution layer 420 to provide a strong mechanical coupling between the die 402 and the redistribution layer 420.

[0063] Figure 4C 4 shows a stage in the manufacturing process where a mold compound 410 is formed over at least a portion of the die 402 and the redistribution layer 420. In an embodiment, the mold compound 410 may be formed with Figure 1 In an embodiment, the mold compound 410 may be flowed over and / or extruded onto the die 402 and the redistribution layer 420 .

[0064] Figure 4DShown is a stage in the manufacturing process where a cavity 417 may be formed within the mold compound 410. In embodiments, the cavity 417 may be made using an etching process or drilling or may be directly punched during mold compound extrusion.

[0065] Figure 4E shows the stages in the manufacturing process where the Figures 3A-3E The dielectric material 318 is similar to the dielectric material 418 inserted into Figure 4D In the cavity 417 of the dielectric material 418, in embodiments, the dielectric material 418 may be placed using spraying, spin coating, dispensing, 3D printing, doctor blade and stencil printing, and / or other deposition techniques. In some embodiments, a curing step may also be applied.

[0066] Figure 4F shows the stages in the manufacturing process where the Figure 1 The BGA 116 is similar to the BGA 416 coupled with a redistribution layer 420 .

[0067] Figure 5 An example of a process for creating a package including dielectric materials with different dielectric constants and a mold compound coupled to a die according to various embodiments is shown. Figures 3A-4F The described processes, techniques, devices and / or systems may be used to perform process 500.

[0068] At block 502, the process may include providing a die, wherein the die has a first side and a second side opposite the first side, wherein the die includes an integrated circuit system, and wherein the first side of the die includes one or more electrical connections. In an embodiment, the die may be connected to Figures 3A-3I The die 302 is similar to or may be Figures 4A-4F In an embodiment, the electrical connector may be similar to the die 402. Figures 3A-3I The electrical connector 308 is similar to or can be Figures 4A-4F The electrical connector 408 is similar.

[0069] At block 504, the process may further include forming a molding at least partially surrounding the die, wherein the molding is physically coupled to at least a portion of the second side of the die. Figure 1 Molding compound 110, Figures 3A-3I The mold compound 310 is similar to or may be similar to Figures 4C-4F The molding compound 410 is similar.

[0070] At block 506, the process may further include forming a dielectric material on the molding, wherein at least a portion of the molding is between the dielectric material and the die, wherein the molding has a first dielectric constant, the first dielectric constant has a first value, wherein the dielectric material has a second dielectric constant, the second dielectric constant has a second value, and wherein the first value is greater than the second value. In an embodiment, the dielectric material may be Figures 3A-3I The dielectric material 318 is similar to or may be Figures 4E-4F The dielectric material 418 is similar.

[0071] Figure 6 6 is a schematic diagram of a computer system 600 according to an embodiment of the present invention. The computer system 600 (also referred to as electronic system 600) as shown can embody dielectric materials and molding compounds with different dielectric constants coupled to a die according to any of the several disclosed embodiments set forth in the present disclosure and their equivalents. The computer system 600 can be a mobile device such as a netbook computer. The computer system 600 can be a mobile device such as a wireless smart phone. The computer system 600 can be a desktop computer. The computer system 600 can be a handheld reader. The computer system 600 can be a server system. The computer system 600 can be a supercomputer or a high performance computing system.

[0072] In an embodiment, the electronic system 600 is a computer system that includes a system bus 620 to electrically couple various components of the electronic system 600. According to various embodiments, the system bus 620 is a single bus or any combination of buses. The electronic system 600 includes a voltage source 630 that provides power to the integrated circuit 610. In some embodiments, the voltage source 630 supplies current to the integrated circuit 610 through the system bus 620.

[0073] According to an embodiment, the integrated circuit 610 is electrically coupled to the system bus 620 and includes any circuit or circuit combination. In an embodiment, the integrated circuit 610 includes a processor 612, which can be of any type. As used herein, the processor 612 can refer to any type of circuit, such as but not limited to a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or other processor. In an embodiment, as disclosed herein, the processor 612 includes a dielectric material and a molding compound with different dielectric constants coupled to the die or coupled thereto. In an embodiment, an SRAM embodiment is used in the memory cache of the processor. Other types of circuits that may be included in the integrated circuit 610 are custom circuits or application specific integrated circuits (ASICs), such as communication circuits 614 for wireless devices or communication circuits for servers, such as cellular phones, smart phones, pagers, portable computers, walkie-talkies, and similar electronic systems. In an embodiment, the integrated circuit 610 includes an on-die memory 616, such as a static random access memory (SRAM). In an embodiment, the integrated circuit 610 includes embedded on-die memory 616, such as embedded dynamic random access memory (eDRAM).

[0074] In an embodiment, integrated circuit 610 is supplemented with subsequent integrated circuit 611. Available embodiments include dual processors 613, dual communication circuits 615, and dual on-die memory 617, such as SRAM. In an embodiment, dual integrated circuit 610 includes embedded on-die memory 617 such as eDRAM.

[0075] In an embodiment, the electronic system 600 also includes an external memory 640, which in turn may include one or more memory elements suitable for a particular application, such as a main memory 642 in the form of RAM, one or more hard disk drives 644, and / or one or more drives that manipulate removable media 646, such as magnetic disks, compact disks (CDs), digital versatile disks (DVDs), flash drives, and other removable media known in the art. According to an embodiment, the external memory 640 may also be an embedded memory 648, such as the first die in the die stack.

[0076] In an embodiment, the electronic system 600 further includes a display device 650 and an audio output 660. In an embodiment, the electronic system 600 includes an input device, such as a controller 670, which can be a keyboard, a mouse, a trackball, a game controller, a microphone, a voice recognition device, or any other input device that inputs information into the electronic system 600. In an embodiment, the input device 670 is a camera. In an embodiment, the input device 670 is a digital audio recorder. In an embodiment, the input device 670 is a camera and a digital audio recorder.

[0077] As shown herein, an integrated circuit 610 including a packaging substrate having dielectric materials and mold compounds with different dielectric constants coupled to a die according to any of the several disclosed embodiments and their equivalents may be implemented in accordance with a wide variety of different embodiments, and an electronic system including a packaging substrate, a computer system, one or more methods of making an integrated circuit including a packaging substrate, and one or more methods of making an electronic assembly including a packaging substrate may also be implemented, wherein the packaging substrate has dielectric materials and mold compounds with different dielectric constants coupled to a die according to any of the several disclosed embodiments set forth herein in various embodiments and their art-recognized equivalents. According to any of the several disclosed embodiments of the packaging substrate having dielectric materials and mold compounds with different dielectric constants coupled to a die and their equivalents, the components, materials, geometries, dimensions, and order of operations may all be varied to accommodate specific I / O coupling requirements including array contact count, array contact configuration, for a microelectronic die embedded in a processor mounting substrate. Such may include, for example, Figure 6 The base substrate represented by the dotted line in FIG. Figure 6 Passive components depicted in .

[0078] Although specific embodiments have been illustrated and described herein for purposes of description, a wide range of alternative and / or equivalent embodiments or implementations calculated to achieve the same purpose may be substituted for the illustrated and described embodiments without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, it is expressly intended that the embodiments described herein be limited only by the claims.

[0079] When the disclosure refers to "a" or "first" element or its equivalent, such disclosure includes one or more such elements, and neither requires nor excludes two or more such elements. In addition, the use of ordinal indicators (e.g., first, second, or third) for identified elements to distinguish between elements does not indicate or imply a required or limited number of such elements, nor do they indicate a specific position or order of such elements unless specifically indicated otherwise.

[0080] Various embodiments may include any suitable combination of the embodiments described above, including alternative (or) embodiments of the embodiments described above in combination (and) (e.g., "and" may be "and / or"). In addition, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon, which, when executed, cause the actions of any of the embodiments described above. In addition, some embodiments may include a device or system having any suitable module units for implementing the various operations of the embodiments described above.

[0081] The above description of the illustrated embodiments, including the content described in the Abstract, is not intended to be exclusive or to limit the embodiments to the exact forms disclosed. Although specific embodiments are described herein for illustrative purposes, various equivalent modifications may exist within the scope of these embodiments, which will be recognized by those skilled in the relevant art.

[0082] These modifications may be made to the embodiments in light of the detailed description above. The terms used in the following claims should not be interpreted to limit the embodiments to the specific implementations disclosed in the specification and claims. Instead, the scope of the present invention will be determined entirely by the following claims, which should be interpreted in accordance with recognized principles of claim interpretation.

[0083] Example

[0084] The following paragraphs will describe examples of various embodiments.

[0085] Example 1 is a device comprising: a die; an integrated circuit system located within the die; a molding at least partially surrounding the die, wherein the molding has a first dielectric constant; and a dielectric material located on the molding, wherein the dielectric material has a second dielectric constant, wherein a first value of the second dielectric constant is less than a second value of the first dielectric constant.

[0086] Example 2 includes the device of Example 1, wherein at least a portion of the dielectric material is located over the integrated circuit system, and wherein the dielectric material reduces a capacitance of the device.

[0087] Example 3 includes the apparatus of Example 1 or 2, wherein the molded object includes one or more cavities, and wherein the one or more cavities are at least partially filled with a dielectric material.

[0088] Example 4 includes the device of Example 1, 2, or 3, wherein the portion of the dielectric material is directly physically coupled to the die.

[0089] Example 5 includes the device of Example 1, 2, 3, or 4, wherein the dielectric material is a layer parallel to a surface of the die.

[0090] Example 6 includes the apparatus of Example 5, wherein the dielectric material extends to at least one side of the die, wherein the at least one side of the die is perpendicular to the surface of the die.

[0091] Example 7 includes the device of Example 1, 2, 3, 4, 5 or 6, wherein the dielectric material includes one or more selected from the following options: modified polyimide (PI) resin, liquid crystal polymer (LCP) resin, covalent organic framework film (COF), polytetrafluoroethylene (PTFE) polymer or air.

[0092] Example 8 includes the apparatus of Example 1, 2, 3, 4, 5, 6, or 7, wherein the thickness of the dielectric material is in a range from 10 microns to 10 millimeters, and the thickness of the molding is in a range from 10 microns to 10 millimeters.

[0093] Example 9 includes the apparatus of Examples 1, 2, 3, 4, 5, 6, 7, or 8, wherein the surface of the die includes one or more electrical contacts electrically coupled to the integrated circuit system.

[0094] Example 9.1 includes the apparatus of Example 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein the thickness of the dielectric material is in a range from a few microns to hundreds of microns, and the thickness of the molding is in a range from a few microns to hundreds of microns.

[0095] Example 9.2 includes the apparatus of Example 9.1, wherein a width of the dielectric material is greater than a width of the molding.

[0096] Example 9.3 includes the apparatus of Example 1, 2, 3, 4, 5, 6, 7, 8, 9, 9.1, or 9.2, wherein the dielectric material is a low-k dielectric material.

[0097] Example 10 is a package comprising: a die including an integrated circuit system; a first set of electrical connectors located at a first side of the die, wherein the first set of electrical connectors are coupled to the integrated circuit system; a redistribution layer located on the first side of the die, wherein the first side of the redistribution layer is electrically coupled to at least one of the first set of electrical connectors located at the first side of the die; a second set of electrical connectors located on a second side of the redistribution layer opposite the first side of the redistribution layer, wherein the second set of electrical connectors are electrically coupled to the first set of electrical connectors; a molding compound surrounding at least a portion of the die, wherein the molding compound is in direct physical contact with at least a portion of the second side of the die opposite the first side of the die; and a dielectric material coupled to the molding compound, wherein at least a portion of the molding compound is located between the dielectric material and the die, wherein the molding compound has a first dielectric constant, the first dielectric constant having a first value, wherein the dielectric material has a second dielectric constant, the second dielectric constant having a second value, and wherein the first value is greater than the second value.

[0098] Example 11 includes the package of Example 10, wherein the first value is greater than or equal to 3, and wherein the second value is less than or equal to 3.

[0099] Example 12 includes the package of Example 10 or 11, wherein the molding compound includes one or more cavities, wherein the one or more cavities are at least partially filled with a dielectric material, and wherein at least one of the one or more cavities is proximate to the integrated circuit system.

[0100] Example 13 includes the package of Example 12, wherein the one or more cavities are surrounded by the molding compound.

[0101] Example 14 includes the package of Example 12 or 13, wherein the one or more cavities include a thermally conductive paste.

[0102] Example 15 includes the package of Examples 10, 11, 12, 13, or 14, wherein the dielectric material comprises one or more selected from the following options: a modified polyimide (PI) resin, a liquid crystal polymer (LCP) resin, a covalent organic framework film (COF), a polytetrafluoroethylene (PTFE) polymer, or air, and wherein the thickness of the dielectric material is in the range from 10 microns to 10 millimeters, and the thickness of the molding compound is in the range from 10 microns to 10 millimeters.

[0103] Example 16 includes the package of Examples 10, 11, 12, 13, 14, or 15, wherein the die includes an electrostatic discharge protection structure.

[0104] Example 17 includes the package of Examples 10, 11, 12, 13, 14, 15, or 16, wherein the first set of electrical connections or the second set of electrical connections include solder balls.

[0105] Example 18 is a method comprising: providing a die, wherein the die has a first side and a second side opposite the first side, wherein the die includes an integrated circuit system, and wherein the first side of the die includes one or more electrical connectors; forming a molding at least partially surrounding the die, wherein the molding is physically coupled to at least a portion of the second side of the die; and forming a dielectric material on the molding, wherein at least a portion of the molding is located between the dielectric material and the die, wherein the molding has a first dielectric constant, the first dielectric constant has a first value, wherein the dielectric material has a second dielectric constant, the second dielectric constant has a second value, and wherein the first value is greater than the second value.

[0106] Example 19 includes the method of Example 18, wherein forming the molded object further comprises forming the molded object including one or more cavities on the molded object, and wherein forming a dielectric material on the molded object further comprises forming the dielectric material in at least a portion of the one or more cavities.

[0107] Example 20 includes the method of Example 18 or 19, wherein the dielectric material includes one or more selected from the following options: modified polyimide (PI) resin, liquid crystal polymer (LCP) resin, covalent organic framework film (COF), polytetrafluoroethylene (PTFE) polymer or air.

Claims

1. A device comprising: tube core; an integrated circuit system within the die; a molding at least partially surrounding the die, wherein the molding has a first dielectric constant; and A dielectric material is disposed on the molded object, wherein the dielectric material has a second dielectric constant, wherein a first value of the second dielectric constant is less than a second value of the first dielectric constant.

2. The device according to claim 1, wherein At least a portion of the dielectric material is located over the integrated circuit system, and wherein the dielectric material reduces capacitance of the device.

3. The device according to claim 1 or 2, wherein: The molded object comprises one or more cavities, and wherein the one or more cavities are at least partially filled with the dielectric material.

4. The device according to claim 1 or 2, wherein: Portions of the dielectric material are directly physically coupled to the die.

5. The device according to claim 1 or 2, wherein: The dielectric material is a layer parallel to the surface of the die.

6. The device according to claim 5, wherein The dielectric material extends to at least one side of the die, wherein the at least one side of the die is perpendicular to the surface of the die.

7. The apparatus according to claim 1 or 2, wherein: The dielectric material includes one or more selected from the following options: modified polyimide (PI) resin, liquid crystal polymer (LCP) resin, covalent organic framework film (COF), polytetrafluoroethylene (PTFE) polymer or air.

8. The apparatus according to claim 1 or 2, wherein: The thickness of the dielectric material is in the range from 10 micrometers to 10 millimeters, and the thickness of the molding is in the range from 10 micrometers to 10 millimeters.

9. The apparatus according to claim 1 or 2, wherein: A surface of the die includes one or more electrical contacts electrically coupled to the integrated circuit system.

10. A package comprising: A die comprising an integrated circuit system; a first set of electrical connections at a first side of the die, wherein the first set of electrical connections is coupled to the integrated circuit system; a redistribution layer on the first side of the die, wherein the first side of the redistribution layer is electrically coupled to at least one electrical connector of the first set of electrical connectors at the first side of the die; a second set of electrical connectors on a second side of the redistribution layer opposite the first side of the redistribution layer, wherein the second set of electrical connectors are electrically coupled to the first set of electrical connectors; a mold compound surrounding at least a portion of the die, wherein the mold compound is in direct physical contact with at least a portion of a second side of the die opposite the first side of the die; and A dielectric material coupled to the mold compound, wherein at least a portion of the mold compound is located between the dielectric material and the die, wherein the mold compound has a first dielectric constant having a first value, wherein the dielectric material has a second dielectric constant having a second value, and wherein the first value is greater than the second value.

11. The package according to claim 10, wherein: The first value is greater than or equal to 3, and wherein the second value is less than or equal to 3.

12. The package according to claim 10 or 11, wherein The molding compound includes one or more cavities, wherein the one or more cavities are at least partially filled with the dielectric material, and wherein at least one of the one or more cavities is proximate to the integrated circuit system.

13. The package according to claim 12, wherein: The one or more cavities are surrounded by the molding compound.

14. The package according to claim 12, wherein: The one or more cavities include thermally conductive paste.

15. The package according to claim 10 or 11, wherein The dielectric material includes one or more selected from the following options: modified polyimide (PI) resin, liquid crystal polymer (LCP) resin, covalent organic framework film (COF), polytetrafluoroethylene (PTFE) polymer or air, and wherein the thickness of the dielectric material is in the range from 10 microns to 10 mm, and the thickness of the molding compound is in the range from 10 microns to 10 mm.

16. The package according to claim 10 or 11, wherein The die includes an electrostatic discharge protection structure.

17. The package according to claim 10 or 11, wherein The first set of electrical connections or the second set of electrical connections include solder balls.

18. A method comprising: providing a die, wherein the die has a first side and a second side opposite the first side, wherein the die includes an integrated circuit system, and wherein the first side of the die includes one or more electrical connections; forming a molding at least partially surrounding the die, wherein the molding is physically coupled to at least a portion of the second side of the die; and A dielectric material is formed on the molding, wherein at least a portion of the molding is located between the dielectric material and the die, wherein the molding has a first dielectric constant having a first value, wherein the dielectric material has a second dielectric constant having a second value, and wherein the first value is greater than the second value.

19. The method according to claim 18, wherein Forming the molded object further includes forming the molded object including one or more cavities within the molded object, and wherein forming the dielectric material on the molded object further includes forming the dielectric material in at least a portion of the one or more cavities.

20. The method according to claim 18 or 19, wherein The dielectric material includes one or more selected from the following options: modified polyimide (PI) resin, liquid crystal polymer (LCP) resin, covalent organic framework film (COF), polytetrafluoroethylene (PTFE) polymer or air.

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