Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a capacitor contact plug, a conductive pad and a capacitor structure partially located in the substrate. A first electrode layer of the capacitor structure comprises a first part located in the substrate and a second part located on the top surface of the substrate; the first part is electrically connected with the second part; the first electrode layer is adjacent to the substrate; the conductive pad is at least partially located in the substrate and electrically connected with the second part of the first electrode layer; the capacitor contact plug is located above the conductive pad and is electrically connected with the conductive pad. According to the semiconductor structure, the etching window of the capacitor contact plug is enlarged through the conductive pad, extra etching margin is provided, short-circuit electric leakage caused by direct connection of the capacitor contact plug and the substrate is avoided, and the yield, the performance and the reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Deep trench capacitors (DTC) can effectively improve the impedance and logic voltage drop of the power delivery network (PDN), and can also effectively improve leakage current. However, with the development of devices, the thickness between the upper and lower plates of the capacitor is shrinking.

[0003] However, the electrode manufacturing technology of double-sided capacitors and multi-sided capacitors also makes the distance between the upper and lower electrode layers closer and closer. When preparing capacitor contact plugs, since the upper and lower electrode layers and the high dielectric constant insulating layer are very thin, it is difficult to stop etching on a certain layer, resulting in short circuit or open circuit in the capacitor contact plug. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which can at least avoid the problem of capacitor contact plug short circuit or open circuit caused by etching.

[0005] One aspect of the present disclosure provides a semiconductor structure, including a substrate, a capacitor contact plug, a conductive pad, and a capacitor structure partially located in the substrate; the first electrode layer of the capacitor structure includes a first portion located in the substrate and a second portion located on the top surface of the substrate; the first portion is electrically connected to the second portion; the first electrode layer is adjacent to the substrate; the conductive pad is at least partially located in the substrate and electrically connected to the second portion of the first electrode layer; the capacitor contact plug is located above the conductive pad and electrically connected to the conductive pad.

[0006] The semiconductor structure in the above-mentioned embodiment is provided with a conductive pad in the substrate, and the conductive pad is electrically connected to the second part of the first electrode layer. When etching the groove required for the capacitor contact plug, since the capacitor contact plug is located above the conductive pad, even if over-etching occurs, it will only be etched onto or into the conductive pad, resulting in the capacitor contact plug being electrically connected to the conductive pad. Therefore, the semiconductor structure of this embodiment increases the etching window of the capacitor contact plug through the conductive pad, provides additional etching margin, avoids short circuit leakage caused by direct connection between the capacitor contact plug and the substrate, improves the conductive performance of the capacitor contact plug, and improves the yield, performance and reliability of the semiconductor structure.

[0007] In some embodiments, the second portion of the first electrode layer is located between the conductive pad and the capacitor contact plug. The semiconductor structure of this embodiment does not have over-etching, and the capacitor contact plug is just electrically connected to the first electrode layer.

[0008] In some embodiments, the capacitor contact plug penetrates the second portion of the first electrode layer and is electrically connected to the conductive pad. In this embodiment, overetching occurs, and the overetching causes the second portion of the first electrode layer under the capacitor contact plug to be etched through, exposing the top surface of the conductive pad. The capacitor contact plug is directly connected to the conductive pad, avoiding the capacitor contact plug being directly connected to the substrate and causing short circuit leakage of the capacitor contact plug. Therefore, the conductive pad increases the etching window of the capacitor contact plug, provides additional etching margin, improves the conductive performance of the capacitor contact plug, and improves the reliability of the capacitor structure.

[0009] In some embodiments, part of the capacitor contact plug is located in the conductive pad. In this embodiment, over-etching occurs, and the over-etching causes the second part of the first electrode layer under the capacitor contact plug to be etched through and part of the conductive pad to be etched away. The capacitor contact plug is located in the conductive pad, and the capacitor contact plug is directly connected to the conductive pad, so as to avoid the capacitor contact plug being directly connected to the substrate and causing short circuit leakage of the capacitor contact plug. Therefore, the conductive pad increases the etching window of the capacitor contact plug, provides additional etching margin, and increases the contact area of ​​the capacitor contact plug, reduces the contact resistance, improves the conductive performance of the capacitor contact plug, and improves the reliability of the capacitor structure.

[0010] In some embodiments, the positive projection of the capacitor contact plug on the top surface of the conductive pad at least partially overlaps with the top surface of the conductive pad, so that even if over-etching occurs when etching the capacitor contact plug, the capacitor contact plug can still contact the conductive pad below and be electrically connected to the conductive pad, thereby avoiding direct connection between the capacitor contact plug and the substrate to cause short circuit leakage of the capacitor contact plug.

[0011] In some embodiments, the semiconductor structure also includes an isolation layer, which is located between the conductive pad and the substrate, and between the first electrode layer and the substrate, so that the bottom surface of the capacitor structure is isolated from the adjacent substrate, avoiding short circuit between the capacitor structure and the substrate, and improving the conductivity of the semiconductor structure.

[0012] In some embodiments, the capacitor structure also includes an intermediate dielectric layer, a second electrode layer and a dielectric layer, the intermediate dielectric layer conformally covers the first electrode layer; the second electrode layer conformally covers the intermediate dielectric layer; the dielectric layer is partially located in the substrate, and the dielectric layer covers the bottom and top surfaces of the second electrode layer. The first electrode layer of the capacitor structure can be used as a lower electrode, and the second electrode layer can be used as an upper electrode. The intermediate dielectric layer isolates the first electrode layer and the second electrode layer to avoid short circuits between adjacent electrode layers, thereby improving the conductivity of the semiconductor structure.

[0013] In some embodiments, the dielectric layer includes at least one of insulating gaps, insulating particles, and insulating voids, which improves the isolation effect of the dielectric layer while reducing the complexity and cost of the manufacturing process.

[0014] In some embodiments, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, wherein the first sub-dielectric layer is partially located in the substrate, and the first sub-dielectric layer covers the bottom surface and at least a portion of the top surface of the second electrode layer; the second sub-dielectric layer covers a portion of the top surface of the second electrode layer, and the second sub-dielectric layer is partially located in the first sub-dielectric layer; wherein the capacitor contact plug is located in the second sub-dielectric layer, and the dielectric layer covers the top of the capacitor structure to prevent the capacitor structure from being damaged in subsequent process steps.

[0015] In some embodiments, another aspect of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate; forming a conductive pad on the substrate, the conductive pad being at least partially located within the substrate; forming a capacitor structure on the substrate, the capacitor structure being partially located within the substrate; the first electrode layer of the capacitor structure includes a first portion located within the substrate and a second portion located on the top surface of the substrate; the first portion is electrically connected to the second portion; the first electrode layer is adjacent to the substrate; the conductive pad is electrically connected to the second portion of the first electrode layer; and forming a capacitor contact plug above the conductive pad, the capacitor contact plug being electrically connected to the conductive pad.

[0016] The semiconductor structure manufactured by the semiconductor structure manufacturing method in the above embodiment, by setting a conductive pad in the substrate and setting the conductive pad to be electrically connected to the second part of the first electrode layer, when etching the groove required for the capacitor contact plug, since the capacitor contact plug is located above the conductive pad, even if over-etching occurs, it will only be etched onto or into the conductive pad, causing the capacitor contact plug to be electrically connected to the conductive pad. Therefore, the semiconductor structure manufactured by the semiconductor structure manufacturing method of this embodiment increases the etching window of the capacitor contact plug through the conductive pad, provides additional etching margin, avoids short circuit leakage caused by direct connection between the capacitor contact plug and the substrate, improves the conductive performance of the capacitor contact plug, and improves the yield, performance and reliability of the semiconductor structure.

[0017] In some embodiments, a conductive pad is formed on a substrate, including: forming a capacitor groove and a groove in the substrate, the depth of the groove is less than the depth of the capacitor groove; forming an isolation layer, the isolation layer covers the bottom surface and sidewalls of the groove, the bottom surface and sidewalls of the capacitor groove, and the top surface of the substrate; forming a conductive pad in the groove; forming a capacitor structure on the substrate, including: forming a first electrode layer, the first electrode layer covers the surface of the isolation layer and the top surface of the conductive pad; forming an intermediate dielectric layer, the intermediate dielectric layer conformally covers the first electrode layer; forming a second electrode layer, the second electrode layer conformally covers the intermediate dielectric layer; forming a dielectric layer filling the capacitor groove, the top surface of the dielectric layer is higher than the top surface of the second electrode layer. The conductive pad increases the etching window of the capacitor contact plug, provides additional etching margin, avoids the capacitor contact plug from being directly connected to the substrate, causing the capacitor contact plug to short-circuit and generate leakage, and increases the contact area of ​​the capacitor contact plug, reduces the contact resistance, improves the conductive performance of the capacitor contact plug, and increases the yield, performance and reliability of the semiconductor structure.

[0018] In some embodiments, forming a capacitor contact plug above a conductive pad includes: forming a through hole in a dielectric layer, wherein an orthographic projection of the through hole on a top surface of the conductive pad at least partially overlaps with the top surface of the conductive pad; and forming a capacitor contact plug in the through hole.

[0019] In some embodiments, forming a capacitor contact plug above the conductive pad includes: forming a first through hole in the dielectric layer, the first through hole exposing the first electrode layer and located above the conductive pad; forming the capacitor contact plug in the first through hole. The semiconductor structure of this embodiment does not produce over-etching, and the capacitor contact plug is just electrically connected to the first electrode layer.

[0020] In some embodiments, a capacitor contact plug is formed above the conductive pad, including: forming a second through hole in the dielectric layer, the second through hole penetrating the first electrode layer and exposing at least a portion of the top surface of the conductive pad; forming the capacitor contact plug in the second through hole. In this embodiment, over-etching occurs, and the over-etching causes the second portion of the first electrode layer under the capacitor contact plug to be etched through, exposing the top surface of the conductive pad, and the capacitor contact plug is directly connected to the conductive pad to avoid short circuit leakage of the capacitor contact plug caused by direct connection between the capacitor contact plug and the substrate. Therefore, the conductive pad increases the etching window of the capacitor contact plug, provides additional etching margin, improves the conductive performance of the capacitor contact plug, and improves the reliability of the capacitor structure.

[0021] In some embodiments, a capacitor contact plug is formed above a conductive pad, including: forming a third through hole in the dielectric layer, the third through hole penetrating the first electrode layer and partially located in the conductive pad; forming a capacitor contact plug in the third through hole. In this embodiment, over-etching occurs, and the over-etching causes the second portion of the first electrode layer under the capacitor contact plug to be etched through and part of the conductive pad to be etched away, the capacitor contact plug is partially located in the conductive pad, and the capacitor contact plug is directly connected to the conductive pad to avoid short circuit leakage of the capacitor contact plug caused by direct connection between the capacitor contact plug and the substrate. Therefore, the conductive pad increases the etching window of the capacitor contact plug, provides additional etching margin, and increases the contact area of ​​the capacitor contact plug, reduces the contact resistance, improves the conductive performance of the capacitor contact plug, and improves the reliability of the capacitor structure.

[0022] In some embodiments, forming a dielectric layer includes: forming a first sub-dielectric layer having a top surface higher than a top surface of a second electrode layer, the first sub-dielectric layer covering an exposed surface of the second electrode layer and being partially located in a capacitor groove; during or after forming a through hole, removing a portion of the first sub-dielectric layer and exposing a portion of the top surface of the second electrode layer; forming a second sub-dielectric layer, the second sub-dielectric layer covering an exposed top surface of the second electrode layer, an exposed surface of the first sub-dielectric layer, and filling the through hole, the first sub-dielectric layer and the second sub-dielectric layer being used to jointly constitute a dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figure 2a A schematic structural diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figure 2b A schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0027] Figure 2c A schematic structural diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0028] Figure 3a It is a schematic structural diagram of a metal contact plug provided in an embodiment of the present disclosure;

[0029] Figure 3bIt is a schematic structural diagram of a metal contact plug provided in another embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of a cross-sectional structure of a substrate provided in some embodiments of the present disclosure;

[0032] Figure 6 In some embodiments of the present disclosure, Figure 5 A schematic diagram of a cross-sectional structure of a capacitor trench formed on a substrate shown;

[0033] Figure 7 In some embodiments of the present disclosure, Figure 6 A schematic cross-sectional structure diagram of a first patterned photoresist layer formed on the structure shown;

[0034] Figure 8 In some embodiments of the present disclosure, Figure 7 A schematic diagram of a cross-sectional structure of a groove formed on the structure shown;

[0035] Fig. 9 In some embodiments of the present disclosure, Figure 8 A schematic cross-sectional structure diagram of an isolation layer formed on the structure shown;

[0036] Fig.10 In some embodiments of the present disclosure, Fig. 9 A schematic cross-sectional structure diagram of a first sacrificial layer formed on the structure shown;

[0037] Fig.11 In some embodiments of the present disclosure, Fig.10 A schematic cross-sectional structure diagram of a second patterned photoresist layer formed on the structure shown;

[0038] Fig.12 In some embodiments of the present disclosure, Fig.11 A schematic diagram of a cross-sectional structure in which the second patterned photoresist layer is removed from the structure shown;

[0039] Fig.13 In some embodiments of the present disclosure, Fig.12 A schematic cross-sectional structure diagram of a conductive pad material layer formed on the structure shown;

[0040] Fig.14 In some embodiments of the present disclosure, Fig.13 A schematic diagram of a cross-sectional structure of a conductive pad formed on the structure shown;

[0041] Fig.15In some embodiments of the present disclosure, Fig.14 A schematic diagram of a cross-sectional structure in which a sacrificial layer is removed from the structure shown;

[0042] Fig.16 In some embodiments of the present disclosure, Fig.15 A schematic cross-sectional structure diagram of a first portion of a first electrode layer, an intermediate dielectric layer, a second electrode layer, a first sub-dielectric layer and a second sub-dielectric layer formed on the structure shown;

[0043] Fig.17 In some embodiments of the present disclosure, Fig.16 A schematic cross-sectional structure diagram of a third patterned photoresist layer formed on the structure shown;

[0044] Fig.18 In some embodiments of the present disclosure, Fig.17 A schematic cross-sectional structure diagram of a first groove formed on the structure shown;

[0045] Fig.19 In some embodiments of the present disclosure, Fig.18 A schematic cross-sectional structure diagram of a second groove formed on the structure shown;

[0046] Fig. 20 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure.

[0047] Description of reference numerals:

[0048] 01, stop layer; 100, semiconductor structure; 10, substrate; 20, isolation layer; 30, conductive pad; 40, capacitor structure; 41, first electrode layer; 411, first part of the first electrode layer; 412, second part of the first electrode layer; 42, intermediate dielectric layer; 43, second electrode layer; 44, dielectric layer; 441, first sub-dielectric layer; 442, second sub-dielectric layer; 50, capacitor contact plug; r, radius of contact area; d, diameter of contact area; h1, height of the first electrode layer; h2, height of the capacitor contact plug in the conductive pad; 101, capacitor groove; 102, first patterned photoresist layer; 103, groove; 104, first sacrificial layer; 105, second patterned photoresist layer; 106, conductive pad material layer; 107, first part of the second sub-dielectric layer; 108, third patterned photoresist layer; 109, first groove; 110, second groove; 60, metal contact plug; 70, contact plug area. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0055] As an important parameter in the silicon interposer, DTC can effectively improve the impedance and logic voltage drop of the PDN, and can also effectively improve the leakage current. Setting DTC on the silicon interposer can achieve circuit voltage stabilization, and can also prevent line crosstalk and coupling in the silicon interposer, playing a decoupling role. In actual production, due to the expensive material of the electrode plate and the increase in capacitance, the thickness of the electrode layer will continue to become thinner as the complexity of the process increases, and the thickness between the upper and lower plates of the capacitor continues to decrease to meet the needs of small-sized voids or deep trenches.

[0056] With the development of capacitors, single-sided capacitors can no longer meet the demand for high capacitance, and double-sided capacitors and multi-sided capacitors have become the new technical development direction. However, the electrode manufacturing technology of double-sided capacitors and multi-sided capacitors also makes the distance between the upper and lower electrode layers closer and closer, and the capacitor plates and high dielectric constant insulating layers are getting thinner and thinner. When the contact plug (CT) is to be connected to the lower electrode layer, since the upper and lower electrode layers and the high dielectric constant insulating layer are very thin, it is difficult to stop the etching on a certain layer, which makes the connection between the CT and the electrode plate difficult, resulting in a short circuit or open circuit.

[0057] like Figure 1 As shown, in the process of preparing DTC, in order to prevent the connection between the electrode layer and the CT, silicon nitride is usually used as a stop layer 01 to optimize the etching. However, this method cannot improve the performance of the electrode, is difficult to implement in a multi-faceted capacitor, and also affects the electrical performance of the multi-faceted capacitor.

[0058] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, which can at least avoid the problem of capacitor contact plug short circuit or open circuit caused by etching in a multi-faceted capacitor.

[0059] Please refer to Figure 2a According to one aspect of the present disclosure, a semiconductor structure 100 is provided, comprising a substrate 10, a capacitor contact plug 50, a conductive pad 30, and a capacitor structure 40 partially located in the substrate 10; a first electrode layer 41 of the capacitor structure 40 comprises a first portion 411 located in the substrate 10 and a second portion 412 located on the top surface of the substrate 10; the first portion 411 is electrically connected to the second portion 412; the first electrode layer 41 is adjacent to the substrate 10; the conductive pad 30 is at least partially located in the substrate 10 and is electrically connected to the second portion 412 of the first electrode layer 41; the capacitor contact plug 50 is located above the conductive pad 30 and is electrically connected to the conductive pad 30.

[0060] As an example, please refer to Figure 2a In the semiconductor structure 100 of the present embodiment, a conductive pad 30 is disposed in the substrate 10, and the conductive pad 30 is electrically connected to the second portion 412 of the first electrode layer 41. When etching the groove required for the capacitor contact plug 50, since the capacitor contact plug 50 is located above the conductive pad 30, even if over-etching occurs, it will only be etched onto or in the conductive pad 30, resulting in the capacitor contact plug 50 being electrically connected to the conductive pad 30. Therefore, the semiconductor structure 100 of the present embodiment increases the etching window of the capacitor contact plug 50 through the conductive pad 30, provides additional etching margin, avoids short circuit leakage caused by direct connection between the capacitor contact plug 50 and the substrate 10, improves the conductive performance of the capacitor contact plug 50, and improves the yield, performance and reliability of the semiconductor structure 100.

[0061] In some embodiments, please refer to Figure 2a The second portion 412 of the first electrode layer 41 is located between the conductive pad 30 and the capacitor contact plug 50, and the capacitor contact plug 50 is electrically connected to the second portion 412 of the first electrode layer 41. The semiconductor structure 100 of this embodiment does not produce over-etching, and the capacitor contact plug 50 is just electrically connected to the first electrode layer 41.

[0062] In some embodiments, please refer to Figure 2b , the capacitor contact plug 50 penetrates the second portion 412 of the first electrode layer 41 and is electrically connected to the conductive pad 30. In this embodiment, over-etching occurs, and the over-etching causes the second portion 412 of the first electrode layer 41 under the capacitor contact plug 50 to be etched through, exposing the top surface of the conductive pad 30, and the capacitor contact plug 50 is directly connected to the conductive pad 30, avoiding the capacitor contact plug 50 being directly connected to the substrate 10 and causing the capacitor contact plug 50 to short-circuit and leak. Therefore, the conductive pad 30 increases the etching window of the capacitor contact plug 50, provides additional etching margin, improves the conductive performance of the capacitor contact plug 50, and improves the reliability of the capacitor structure 40.

[0063] In some embodiments, please refer to Figure 2c , part of the capacitor contact plug 50 is located in the conductive pad 30. In this embodiment, over-etching occurs, and the over-etching causes the second part 412 of the first electrode layer 41 under the capacitor contact plug 50 to be etched through and part of the conductive pad 30 to be etched away. The capacitor contact plug 50 is partially located in the conductive pad 30, and the capacitor contact plug 50 is directly connected to the conductive pad 30, so as to avoid the capacitor contact plug 50 being directly connected to the substrate 10 and causing the capacitor contact plug 50 to short-circuit and leak. Therefore, the conductive pad 30 increases the etching window of the capacitor contact plug 50, provides additional etching margin, and increases the contact area of ​​the capacitor contact plug, reduces the contact resistance, improves the conductive performance of the capacitor contact plug 50, and improves the reliability of the capacitor structure 40.

[0064] As an example, see Figure 3a-3b , Figure 3a is the contact area S1 of the capacitor contact plug 50 without over-etching, Figure 3b is the contact area S2 of the capacitor contact plug 50 overetched to the inside of the conductive pad 30, r is the radius of the bottom area of ​​the capacitor contact plug 50 in contact with the second portion 412 of the first electrode layer 41, S1 =π*r 2d is the diameter of the bottom area of ​​the capacitor contact plug 50 in contact with the second portion 412 of the first electrode layer 41, S1 only includes the bottom area of ​​the capacitor contact plug 50 in contact with the second portion 412 of the first electrode layer 41, and S2 includes the bottom area of ​​the capacitor contact plug 50 in contact with the second portion 412 of the first electrode layer 41, the contact area of ​​the first electrode layer 41 at the height h1, and the contact area of ​​the capacitor contact plug 50 at the height h2 in the conductive pad 30, S2 = π*r 2 +π*d*h1+π*d*h2; S2 has two more areas than S1, so over-etching the capacitor contact plug 50 to the inside of the conductive pad 30 can increase the contact area of ​​the capacitor contact plug 50 and reduce the contact resistance.

[0065] In some embodiments, please refer to Figure 2a-2c The orthographic projection of the capacitor contact plug 50 on the top surface of the conductive pad 30 at least partially overlaps with the top surface of the conductive pad 30, so that even if over-etching occurs when etching the capacitor contact plug 50, the capacitor contact plug 50 can still contact the conductive pad 30 below and be electrically connected to the conductive pad 30, thereby avoiding direct connection between the capacitor contact plug 50 and the substrate 10, which may cause short circuit leakage of the capacitor contact plug 50.

[0066] In some embodiments, please refer to Figure 2a-2c The semiconductor structure 100 also includes an isolation layer 20, which is located between the conductive pad 30 and the substrate 10, and between the first electrode layer 41 and the substrate 10, so that the bottom surface of the capacitor structure 40 is isolated from the adjacent substrate 10, avoiding short circuit between the capacitor structure 40 and the substrate 10, thereby improving the conductive performance of the semiconductor structure 100.

[0067] As an example, please refer to Figure 2a-2c The thickness of the isolation layer 20 is 45 nm-55 nm. For example, the thickness of the isolation layer 20 can be 45 nm, 47 nm, 49 nm, 50 nm, 51 nm, 53 nm or 55 nm, etc.

[0068] In some embodiments, please refer to Figure 2a-2cThe capacitor structure 40 also includes an intermediate dielectric layer 42, a second electrode layer 43 and a dielectric layer 44. The intermediate dielectric layer 42 conformally covers the first electrode layer 41; the second electrode layer 43 conformally covers the intermediate dielectric layer 42; the dielectric layer 44 is partially located in the substrate 10, and the dielectric layer 44 covers the bottom and top surfaces of the second electrode layer 43. The first electrode layer 41 of the capacitor structure 40 can be used as a lower electrode, and the second electrode layer 43 can be used as an upper electrode. The intermediate dielectric layer 42 isolates the first electrode layer 41 and the second electrode layer 43 to avoid short circuits between adjacent electrode layers, thereby improving the conductive performance of the semiconductor structure 100; the dielectric layer 44 can fill the holes in the structure formed by the first electrode layer 41, the intermediate dielectric layer 42 and the second electrode layer 43, so that the surface of the capacitor structure 40 is smooth.

[0069] In some embodiments, please refer to Figure 2a-2c The dielectric layer 44 includes at least one of insulating gaps, insulating particles and insulating voids, which improves the isolation effect of the dielectric layer 44 while reducing the complexity and cost of the manufacturing process.

[0070] In some embodiments, please refer to Figure 2a-2c The dielectric layer 44 includes a first sub-dielectric layer 441 and a second sub-dielectric layer 442. The first sub-dielectric layer 441 is partially located in the substrate 10, and the first sub-dielectric layer 441 covers the bottom surface and at least a portion of the top surface of the second electrode layer 43; the second sub-dielectric layer 442 covers a portion of the top surface of the second electrode layer 43, and the second sub-dielectric layer 442 is partially located in the first sub-dielectric layer 441; wherein, the capacitor contact plug 50 is located in the second sub-dielectric layer 442, and the dielectric layer 44 covers the top of the capacitor structure 40 to prevent the capacitor structure 40 from being damaged in subsequent process steps, and the second sub-dielectric layer 442 also provides a placement position for the capacitor contact plug 50.

[0071] In some embodiments, please refer to Figure 4 Another aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0072] Step S202: providing a substrate;

[0073] Step S204: forming a conducting pad on the substrate, wherein the conducting pad is at least partially located in the substrate;

[0074] Step S206: forming a capacitor structure on the substrate, wherein the capacitor structure is partially located in the substrate; the first electrode layer of the capacitor structure includes a first portion located in the substrate and a second portion located on the top surface of the substrate; the first portion is electrically connected to the second portion; the first electrode layer is adjacent to the substrate; and the conductive pad is electrically connected to the second portion of the first electrode layer;

[0075] Step S208: forming a capacitor contact plug above the conductive pad, wherein the capacitor contact plug is electrically connected to the conductive pad.

[0076] As an example, please refer to Figure 4 The semiconductor structure manufactured by the method for manufacturing the semiconductor structure of the present embodiment sets a conductive pad in the substrate and sets the conductive pad to be electrically connected to the second part of the first electrode layer. When etching the groove required by the capacitor contact plug, since the capacitor contact plug is located above the conductive pad, even if over-etching occurs, it will only be etched onto or into the conductive pad, causing the capacitor contact plug to be electrically connected to the conductive pad. Therefore, the semiconductor structure manufactured by the method for manufacturing the semiconductor structure of the present embodiment increases the etching window of the capacitor contact plug through the conductive pad, provides additional etching margin, avoids short circuit leakage caused by direct connection between the capacitor contact plug and the substrate, improves the conductive performance of the capacitor contact plug, and improves the yield, performance and reliability of the semiconductor structure.

[0077] As an example, see Figure 5 The substrate 10 in step S202 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10 or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0078] In some embodiments, please refer to Figure 6-Figure 15 In step S204, a conductive pad 30 is formed on the substrate 10, comprising:

[0079] Step S2041: forming a capacitor trench 101 and a groove 103 in the substrate 10, wherein the depth of the groove 103 is smaller than the depth of the capacitor trench 101;

[0080] Step S2042: forming an isolation layer 20, wherein the isolation layer 20 covers the bottom surface and side walls of the recess 103, the bottom surface and side walls of the capacitor trench 101, and the top surface of the substrate 10;

[0081] Step S2043: forming a conducting pad 30 in the groove 103;

[0082] As an example, please refer to Figure 6-Figure 15In step S2041, an etching process can be used to form a capacitor groove 101 and a groove 103 in the substrate 10. When forming the groove 103, a first photoresist material layer is first coated on the top surface of the substrate 10 and the capacitor groove 101. After a series of steps such as exposure and development, a first patterned photoresist layer 102 is formed. The first patterned photoresist layer 102 has an opening pattern for defining the position and shape of the groove 103. Then, an etching process is used to etch the substrate 10 using the first patterned photoresist layer 102 with the opening pattern as a mask to form a groove 103 on the substrate 10. The depth of the groove 103 is less than the depth of the capacitor groove 101.

[0083] As an example, please refer to Figure 6-Figure 15 In step S2042, a deposition process can be used to deposit an isolation layer 20 on the bottom surface and side walls of the recess 103, the bottom surface and side walls of the capacitor trench 101, and the top surface of the substrate 10. The material of the isolation layer 20 includes oxides such as silicon dioxide, aluminum oxide, titanium oxide, chromium oxide, silicon oxide, or a combination thereof. The isolation layer 20 isolates the bottom surface of the capacitor structure 40 from the adjacent substrate 10, thereby avoiding short circuit between the capacitor structure 40 and the substrate 10 and improving the conductive performance of the semiconductor structure.

[0084] As an example, please refer to Figure 6-Figure 15In step S2043, a first sacrificial layer 104 is deposited on the bottom surface and sidewall of the groove 103, the bottom surface and sidewall of the capacitor trench 101, and the top surface of the isolation layer 20 by using a deposition process, and a second photoresist material layer is deposited on the top surface of the first sacrificial layer 104 by using a deposition process. After a series of steps such as exposure and development, a second patterned photoresist layer 105 is formed. The second patterned photoresist layer 105 has an opening pattern for defining the position and shape of the conductive pad 30, and then an etching process is used to form a second patterned photoresist layer 105 having an opening pattern. The first sacrificial layer 104 is etched using the second patterned photoresist layer 105 as a mask to remove the first sacrificial layer 104 in the groove 103, exposing the groove 103, depositing a conductive pad material layer 106 on the bottom surface and sidewall of the groove 103 and the top surface of the first sacrificial layer 104, removing the first sacrificial layer 104 and the conductive pad material layer 106 on the top surface of the isolation layer 20 by an etching process, forming a conductive pad 30 in the groove 103, and finally removing the first sacrificial layer 104 in the capacitor trench 101 by an etching process. The material of the first sacrificial layer 104 includes silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, single crystal silicon, carbon or a combination thereof; the material of the conductive pad material layer 106 includes tungsten, titanium, nickel, platinum, gold, aluminum, copper or a combination thereof. The conductive pad 30 increases the etching window of the capacitor contact plug 50, provides additional etching margin, avoids direct connection between the capacitor contact plug 50 and the substrate 10, causes a short circuit in the capacitor contact plug 50, generates leakage, and increases the contact area of ​​the capacitor contact plug 50, reduces the contact resistance, improves the conductive performance of the capacitor contact plug, and increases the yield, performance and reliability of the semiconductor structure.

[0085] As an example, please refer to Figure 6-Figure 15The deposition process may include, but is not limited to, one or more of the following processes: chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma enhanced chemical vapor deposition (PECVD), and spin-on dielectric (SOD). For example, the first sacrificial layer 104 may be deposited by a spin-on dielectric process, and a spin coater may be used for coating. The surface of the semiconductor structure is facing upward and fixed with a vacuum chuck, a predetermined amount of material is dripped, and then the semiconductor structure is rotated at high speed to uniformly fill the first sacrificial layer 104 on the bottom surface and sidewall of the groove 103, the bottom surface and sidewall of the capacitor trench 101, and the top surface of the isolation layer 20, and then heat treated at a preset temperature to completely remove the solvent and stabilize the first sacrificial layer 104. The preset temperature is 300° C. to 400° C., for example, the preset temperature may be 300° C., 320° C., 340° C., 360° C., 380° C. or 400° C., etc. The spin coating process requires a shorter drying time, and the first sacrificial layer 104 has a higher density and a uniform thickness, and a high-quality first sacrificial layer 104 can be efficiently manufactured.

[0086] As an example, please refer to Figure 6-Figure 15 , the etching process may include but is not limited to a dry etching process and / or a wet etching process. The dry etching process may include but is not limited to one or more of reactive ion etching (RIE) and inductively coupled plasma etching (ICP). For example, a wet etching process may be used to remove the first sacrificial layer 104, and the semiconductor structure may be immersed in a certain chemical reagent, which may react chemically with the first sacrificial layer 104 and be converted into a soluble compound, so that the first sacrificial layer 104 is removed. The etching rate and etching selectivity are controlled by selecting the chemical reagent, the ratio, and the temperature control. The wet etching process has a single procedure, simple equipment, low cost, high yield, and a good etching selectivity can be obtained through regulation.

[0087] In some embodiments, please refer to Fig.16 In step S206, a capacitor structure 40 is formed on the substrate 10, including:

[0088] Step S2061: forming a first electrode layer 41, wherein the first electrode layer 41 covers the surface of the isolation layer 20 and the top surface of the conductive pad 30;

[0089] Step S2062: forming an intermediate dielectric layer 42, wherein the intermediate dielectric layer 42 conformally covers the first electrode layer 41;

[0090] Step S2063: forming a second electrode layer 43, wherein the second electrode layer 43 conformally covers the intermediate dielectric layer 42;

[0091] Step S2064 : forming a dielectric layer that fills the capacitor trench 101 , wherein the top surface of the dielectric layer is higher than the top surface of the second electrode layer 43 .

[0092] As an example, please refer to Fig.16 In step 206, a deposition process is used to form a first electrode layer 41, an intermediate dielectric layer 42, a second electrode layer 43 and a dielectric layer 44. The material of the first electrode layer 41 includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, cobalt nitride, copper, aluminum, tungsten, cobalt, nickel, tantalum or a combination thereof; the material of the intermediate dielectric layer 42 includes aluminum oxide, zirconium oxide and a combination thereof, and the material of the intermediate dielectric layer 42 may also include other insulating materials with a high dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9; the material of the second electrode layer 43 includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, cobalt nitride, copper, aluminum, tungsten, cobalt, nickel, tantalum or a combination thereof. The first electrode layer 41 can be used as a lower electrode, and the second electrode layer 43 can be used as an upper electrode. The intermediate dielectric layer 42 isolates the first electrode layer 41 from the second electrode layer 43 to avoid short circuits between adjacent electrode layers and improve the conductivity of the semiconductor structure.

[0093] In some embodiments, please refer to Fig.16 In step S2064, a dielectric layer 44 is formed, including:

[0094] Step S20641: forming a first sub-dielectric layer 441 whose top surface is higher than the top surface of the second electrode layer 43 , wherein the first sub-dielectric layer 441 covers the exposed surface of the second electrode layer 43 and is partially located in the capacitor trench 101 ;

[0095] Step S20642: during or after forming the through hole, removing a portion of the first sub-dielectric layer 441 and exposing a portion of the top surface of the second electrode layer 43;

[0096] Step S20643: forming a second sub-dielectric layer 442 , which covers the exposed top surface of the second electrode layer 43 and the exposed surface of the first sub-dielectric layer 441 , and fills the through holes. The first sub-dielectric layer 441 and the second sub-dielectric layer 442 are used to jointly constitute the dielectric layer 44 .

[0097] As an example, please refer to Fig.16In step S20641, a deposition process may be used to deposit the first sub-dielectric layer 441 and the first portion 107 of the second sub-dielectric layer 442. The material of the first sub-dielectric layer 441 includes polysilicon, and the material of the first portion 107 of the second sub-dielectric layer 442 includes oxides such as silicon dioxide, aluminum oxide, titanium oxide, chromium oxide, silicon oxide, or a combination thereof.

[0098] As an example, see Figure 16-18 Step S20642 includes coating a third photoresist material layer on the top of the first portion 107 of the second sub-dielectric layer 442, and forming a third patterned photoresist layer 108 through a series of steps such as exposure and development. The third patterned photoresist layer 108 has an opening pattern for defining the position and shape of the first groove 109, and then an etching process is used to etch the dielectric layer 44, the second electrode layer 43 and the intermediate dielectric layer 42 using the third patterned photoresist layer 108 having the opening pattern as a mask to form the first groove 109.

[0099] As an example, see Figure 18-19 In step S2043, a second sacrificial layer is deposited on the bottom surface and sidewall of the first groove 109 and the top surface of the first part 107 of the second sub-dielectric layer 442 by a deposition process, and a fourth photoresist material layer is deposited on the top surface of the second sacrificial layer by a deposition process. After a series of steps such as exposure and development, a fourth patterned photoresist layer is formed. The fourth patterned photoresist layer has an opening pattern for defining the position and shape of the second groove 110. Then, an etching process is used to etch the second sacrificial layer, the first part 107 of the second sub-dielectric layer 442 and the first sub-dielectric layer 441 using the fourth patterned photoresist layer having the opening pattern as a mask to form the second groove 110. The second sacrificial layer is removed by an etching process. The material of the second sacrificial layer includes silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, single crystal silicon, carbon or a combination thereof.

[0100] As an example, please refer to Fig.19 In step S20643, a second portion of the second sub-dielectric layer 442 is deposited on the bottom surface and sidewalls of the first trench 109, the bottom surface and sidewalls of the second trench 110, and the top surface of the first portion 107 of the second sub-dielectric layer 442 using a deposition process to form the second sub-dielectric layer 442. The material of the second sub-dielectric layer 442 includes oxides such as silicon dioxide, aluminum oxide, titanium oxide, chromium oxide, silicon oxide, or a combination thereof.

[0101] In some embodiments, please refer to Figure 17-Figure 19 and Figure 2a In step S208, a capacitor contact plug 50 is formed above the conductive pad 30, including:

[0102] Step S2081: forming a through hole in the dielectric layer 44, wherein the orthographic projection of the through hole on the top surface of the conductive pad 30 at least partially overlaps with the top surface of the conductive pad 30;

[0103] Step S2082: forming a capacitor contact plug 50 in the through hole.

[0104] As an example, see Figure 17-Figure 19 and Figure 2a In step S2081, a fifth photoresist material layer is deposited on the top surface of the second sub-dielectric layer 442 by a deposition process, and a fifth patterned photoresist layer is formed after a series of steps such as exposure and development. The fifth patterned photoresist layer has an opening pattern for defining the position and shape of the through hole. Then, an etching process is used to etch the second sub-dielectric layer 442 using the fifth patterned photoresist layer having the opening pattern as a mask to form a through hole. The through hole is partially located in the first groove 109, and the orthographic projection of the through hole on the top surface of the conductive pad 30 at least partially overlaps with the top surface of the conductive pad 30. In step S2082, a capacitor contact plug 50 is formed in the through hole by a deposition process. The material of the capacitor contact plug 50 includes tungsten, titanium, nickel, platinum, gold, aluminum, copper or a combination thereof.

[0105] As an example, see Figure 5-Figure 19 The opening patterns defined by the first patterned photoresist layer 102, the second patterned photoresist layer 105, the third patterned photoresist layer 108, the fourth patterned photoresist layer and the fifth patterned photoresist layer are the same patterns, and the same mask can be used. By repeatedly using the same mask, the cost of the mask is reduced and costs are saved.

[0106] In some embodiments, please refer to Figure 2a In step S208, a capacitor contact plug 50 is formed above the conductive pad 30, including:

[0107] Step S2081a: forming a first through hole in the dielectric layer 44 , wherein the first through hole exposes the first electrode layer 41 and is located above the conducting pad 30 ;

[0108] Step S2082a: forming a capacitor contact plug 50 in the first through hole.

[0109] As an example, see Figure 2a The second portion of the first electrode layer 41 in step S2081a is located between the conductive pad 30 and the capacitor contact plug 50, and the capacitor contact plug 50 is electrically connected to the second portion 412 of the first electrode layer 41. The semiconductor structure of this embodiment does not produce over-etching, and the capacitor contact plug 50 is just electrically connected to the first electrode layer 41.

[0110] In some embodiments, please refer to Figure 2bIn step S208, a capacitor contact plug 50 is formed above the conductive pad 30, including:

[0111] Step S2081b: forming a second through hole in the dielectric layer 44 , wherein the second through hole penetrates the first electrode layer 41 and exposes at least a portion of the top surface of the conducting pad 30 ;

[0112] Step S2082b: forming a capacitor contact plug 50 in the second through hole.

[0113] As an example, see Figure 2b , the capacitor contact plug 50 in step S2081b penetrates the second portion 412 of the first electrode layer 41 and is electrically connected to the conductive pad 30. In this embodiment, over-etching occurs, and the over-etching causes the second portion 412 of the first electrode layer 41 under the capacitor contact plug 50 to be etched through, exposing the top surface of the conductive pad 30, and the capacitor contact plug 50 is directly connected to the conductive pad 30, avoiding the capacitor contact plug 50 being directly connected to the substrate 10 and causing the capacitor contact plug 50 to short-circuit and leak. Therefore, the conductive pad 30 increases the etching window of the capacitor contact plug 50, provides additional etching margin, improves the conductive performance of the capacitor contact plug 50, and improves the reliability of the capacitor structure 40.

[0114] In some embodiments, please refer to Figure 2c In step S208, a capacitor contact plug 50 is formed above the conductive pad 30, including:

[0115] Step S2081c: forming a third through hole in the dielectric layer 44 , wherein the third through hole penetrates the first electrode layer 41 and is partially located in the conductive pad 30 ;

[0116] Step S2082c: forming a capacitor contact plug 50 in the third through hole.

[0117] As an example, see Figure 2c , part of the capacitor contact plug 50 in step S2081c is located in the conductive pad 30. In this embodiment, over-etching occurs, and the over-etching causes the second part 412 of the first electrode layer 41 under the capacitor contact plug 50 to be etched through and part of the conductive pad 30 to be etched away, and the capacitor contact plug 50 is partially located in the conductive pad 30, and the capacitor contact plug 50 is directly connected to the conductive pad 30, so as to avoid the capacitor contact plug 50 being directly connected to the substrate 10 and causing the capacitor contact plug 50 to short-circuit and leak. Therefore, the conductive pad 30 increases the etching window of the capacitor contact plug 50, provides additional etching margin, and increases the contact area of ​​the capacitor contact plug 50, reduces the contact resistance, improves the conductive performance of the capacitor contact plug 50, and improves the reliability of the capacitor structure 40.

[0118] As an example, see Figure 2a-2c and Fig.19The capacitor contact plug 50 formed in this embodiment is a lower electrode capacitor contact plug 50. After the lower electrode capacitor contact plug 50 is formed, a sixth photoresist material layer can be deposited on the top surface of the second sub-dielectric layer 442 by a deposition process. After a series of steps such as exposure and development, a sixth patterned photoresist layer is formed. The sixth patterned photoresist layer has an opening pattern for defining the position and shape of the upper electrode through hole. Then, an etching process is used to etch the second sub-dielectric layer 442 using the sixth patterned photoresist layer having the opening pattern as a mask to form an upper electrode through hole. The upper electrode through hole is partially located in the second groove 110. Then, a deposition process is used to form an upper electrode capacitor contact plug in the upper electrode through hole. The upper electrode capacitor contact plug is electrically connected to the second electrode layer 43.

[0119] As an example, see Figure 2a-2c In this embodiment, a material with a high etching selectivity ratio between the second sub-dielectric layer 442 and the first electrode layer 41 can be selected to ensure that the through hole can be etched at least to the first electrode layer 41, thereby avoiding the problem that the capacitor contact plug 50 cannot be connected to the circuit board due to insufficient etching, resulting in an open circuit of the capacitor structure 40.

[0120] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0121] As an example, see Fig. 20 The contact plug region 70 defines an etching window for the lower electrode of the capacitor structure, so as to form a metal contact layer at a position corresponding to the etching window, thereby obtaining an array-arranged metal contact plug 60 .

[0122] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0123] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0124] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: It includes a substrate, a capacitor contact plug, a conductive pad, and a capacitor structure partially located in the substrate; The first electrode layer of the capacitor structure includes a first portion located in the substrate and a second portion located on the top surface of the substrate; the first portion is electrically connected to the second portion; the first electrode layer is adjacent to the substrate; The conducting pad is at least partially located in the substrate and is electrically connected to the second portion of the first electrode layer; The capacitor contact plug is located above the conductive pad and is electrically connected to the conductive pad.

2. The semiconductor structure according to claim 1, characterized in that A portion of the second portion is located between the conductive pad and the capacitor contact plug.

3. The semiconductor structure according to claim 1, characterized in that The capacitor contact plug passes through the second portion and is electrically connected to the conductive pad.

4. The semiconductor structure according to claim 1, characterized in that: A portion of the capacitor contact plug is located within the conductive pad.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: An orthographic projection of the capacitor contact plug on the top surface of the conductive pad at least partially overlaps with the top surface of the conductive pad.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Also includes: The isolation layer is located between the conductive pad and the substrate, and between the first electrode layer and the substrate.

7. The semiconductor structure according to claim 6, characterized in that: The capacitor structure further includes: an intermediate dielectric layer, conformally covering the first electrode layer; a second electrode layer, conformally covering the intermediate dielectric layer; A dielectric layer is partially located in the substrate, and the dielectric layer covers the bottom surface and the top surface of the second electrode layer.

8. The semiconductor structure according to claim 7, characterized in that: The dielectric layer includes at least one of insulating gaps, insulating particles and insulating voids.

9. The semiconductor structure according to claim 7, characterized in that: The dielectric layer comprises: A first sub-dielectric layer, partially located in the substrate, the first sub-dielectric layer covers the bottom surface and at least a portion of the top surface of the second electrode layer; a second sub-dielectric layer, covering a portion of the top surface of the second electrode layer, wherein a portion of the second sub-dielectric layer is located within the first sub-dielectric layer; Wherein, the capacitor contact plug is located in the second sub-dielectric layer.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a conductive pad on the substrate, wherein the conductive pad is at least partially located within the substrate; A capacitor structure is formed on the substrate, wherein the capacitor structure is partially located in the substrate; a first electrode layer of the capacitor structure includes a first portion located in the substrate and a second portion located on the top surface of the substrate; the first portion is electrically connected to the second portion; the first electrode layer is adjacent to the substrate; and the conductive pad is electrically connected to the second portion of the first electrode layer; A capacitor contact plug is formed above the conductive pad, and the capacitor contact plug is electrically connected to the conductive pad.

11. The preparation method according to claim 10, characterized in that: The step of forming a conductive pad on the substrate comprises: forming a capacitor trench and a groove in the substrate, wherein the depth of the groove is smaller than the depth of the capacitor trench; forming an isolation layer, wherein the isolation layer covers the bottom surface and side walls of the groove, the bottom surface and side walls of the capacitor trench, and the top surface of the substrate; forming the conductive pad in the groove; The forming of a capacitor structure on the substrate comprises: forming a first electrode layer, wherein the first electrode layer covers the surface of the isolation layer and the top surface of the conductive pad; forming an intermediate dielectric layer, wherein the intermediate dielectric layer conformally covers the first electrode layer; forming a second electrode layer, wherein the second electrode layer conformally covers the intermediate dielectric layer; A dielectric layer is formed to fill the capacitor trench, wherein a top surface of the dielectric layer is higher than a top surface of the second electrode layer.

12. The preparation method according to claim 11, characterized in that: The step of forming a capacitor contact plug above the conductive pad comprises: forming a through hole in the dielectric layer, wherein an orthographic projection of the through hole on the top surface of the conductive pad at least partially overlaps with the top surface of the conductive pad; The capacitor contact plug is formed in the through hole.

13. The preparation method according to claim 12, characterized in that: The step of forming a capacitor contact plug above the conductive pad comprises: forming a first through hole in the dielectric layer, wherein the first through hole exposes the first electrode layer and is located above the conducting pad; The capacitor contact plug is formed in the first through hole.

14. The preparation method according to claim 12, characterized in that: The step of forming a capacitor contact plug above the conductive pad comprises: forming a second through hole in the dielectric layer, wherein the second through hole penetrates the first electrode layer and exposes at least a portion of the top surface of the conducting pad; The capacitor contact plug is formed in the second through hole.

15. The preparation method according to claim 12, characterized in that: The forming of a capacitor contact plug above the conductive pad comprises: forming a third through hole in the dielectric layer, wherein the third through hole penetrates the first electrode layer and is partially located in the conductive pad; The capacitor contact plug is formed in the third through hole.

16. The preparation method according to any one of claims 11 to 15, characterized in that: Forming the dielectric layer includes: forming a first sub-dielectric layer having a top surface higher than that of the second electrode layer, wherein the first sub-dielectric layer covers an exposed surface of the second electrode layer and is partially located in the capacitor groove; During or after forming the through hole, removing a portion of the first sub-dielectric layer and exposing a portion of the top surface of the second electrode layer; A second sub-dielectric layer is formed, the second sub-dielectric layer covers the exposed top surface of the second electrode layer and the exposed surface of the first sub-dielectric layer and fills the through hole, and the first sub-dielectric layer and the second sub-dielectric layer are used to jointly constitute the dielectric layer.

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