Capacitor structure and preparation method thereof, memory and electronic equipment

Abstract

The invention relates to a capacitor structure and a preparation method thereof, a memory and electronic equipment. The capacitor structure comprises a substrate, a first electrode, a second electrode, a dielectric layer and a barrier layer, the first electrode is arranged on the substrate; the second electrode is sleeved outside the first electrode; the dielectric layer is arranged between the first electrode and the second electrode; the barrier layer is arranged between the dielectric layer and the first electrode. The method can improve the quality of the STO film.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a capacitor structure and a preparation method thereof, a memory, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] As DRAM is miniaturized, capacitors need to meet the requirements of high capacitance and low leakage at the same time. In the related art, a capacitor includes two electrodes arranged relatively to each other, and a dielectric layer arranged between the two electrodes. The material selection of the dielectric layer is particularly important for achieving capacitors with high capacitance and low leakage. Strontium titanate (English: strontium titanate, chemical formula: SrTiO3, abbreviated as: STO) has an ultra-high dielectric constant and can be used in the capacitor structure of DRAM. However, the quality of the STO film in the current capacitor structure is poor, and it is not possible to achieve ultra-thin STO films while taking into account high capacitance and low leakage. Summary of the invention

[0004] Based on this, it is necessary to provide a capacitor structure and a preparation method thereof, a memory, and an electronic device to address the problem of poor quality of ultra-thin STO films in the prior art.

[0005] In order to achieve the above object, in a first aspect, the present invention provides a capacitor structure, the capacitor structure comprising:

[0006] substrate;

[0007] A first electrode, disposed on the substrate;

[0008] A second electrode, sleeved outside the first electrode;

[0009] a dielectric layer, disposed between the first electrode and the second electrode;

[0010] The barrier layer is arranged between the dielectric layer and the first electrode.

[0011] The capacitor structure of the present invention comprises a substrate, a first electrode, a second electrode, a dielectric layer and a barrier layer, wherein the first electrode is arranged on the substrate, the second electrode is sleeved outside the first electrode, and the dielectric layer is arranged between the first electrode and the second electrode, so that charge storage can be realized. Moreover, the barrier layer is arranged between the dielectric layer and the first electrode, so that the first electrode can be prevented from participating in the formation process of the dielectric layer, resulting in poor quality of the dielectric layer, thereby improving the formation quality of the dielectric layer to meet the requirements of high capacitance value and low leakage.

[0012] In one of the embodiments, the material of the dielectric layer is strontium titanate and is doped with one of silicon, hafnium, yttrium, aluminum, zirconium, and gadolinium, and the thickness of the dielectric layer is 5 nm to 15 nm.

[0013] In one embodiment, the material of the barrier layer is titanium.

[0014] In one embodiment, the thickness of the barrier layer is 0.5 nm to 2 nm.

[0015] In one embodiment, the first electrode is an annular structure with a center line perpendicular to the substrate, the barrier layer covers all exposed surfaces of the first electrode, the dielectric layer covers all exposed surfaces of the barrier layer and fills the space within the annular structure, and the second electrode covers all exposed surfaces of the dielectric layer outside the annular structure.

[0016] In one embodiment, the substrate is a strip structure, the first electrode is arranged around the strip structure, the barrier layer is arranged around the first electrode, the dielectric layer is arranged around the barrier layer, and the second electrode is arranged around the dielectric layer.

[0017] In a second aspect, the present invention further provides a memory, comprising the capacitor structure provided in the first aspect.

[0018] The memory of the present invention includes the above capacitor structure, which can form a high-quality dielectric layer, so that the capacitor can meet the requirements of high capacitance and low leakage at the same time.

[0019] In one embodiment, the memory further includes a semiconductor layer, a word line and a bit line, the substrate includes a plurality of semiconductor layers respectively spaced apart along a first horizontal direction and a second horizontal direction, each of the semiconductor layers is a strip structure extending along a vertical direction, the word line extends along the first horizontal direction and is connected to the middle of each of the semiconductor layers spaced apart along the first horizontal direction, the bit line extends along the second horizontal direction and is connected to the first end of each of the semiconductor layers spaced apart along the second horizontal direction, and the capacitor structure is connected to the second end of the semiconductor layer.

[0020] In one embodiment, the memory further includes a semiconductor layer, a word line and a bit line, the substrate is a strip structure, the strip structure is one semiconductor layer, the word line extends in a vertical direction and is connected to the middle of each of the semiconductor layers spaced apart along the vertical direction, the bit line extends in a horizontal direction and is connected to the first end of each of the semiconductor layers spaced apart along the horizontal direction, and the capacitor structure is arranged around the semiconductor layer and is connected to the second end of the semiconductor layer.

[0021] In a third aspect, the present invention further provides an electronic device, comprising the memory provided in the second aspect.

[0022] The electronic device of the present invention comprises the above-mentioned memory, which has high storage density and can realize high-density and large-capacity data storage.

[0023] In a fourth aspect, the present invention further provides a method for preparing a capacitor structure, the method comprising:

[0024] providing a substrate;

[0025] A first electrode, a barrier layer, a dielectric layer and a second electrode are sequentially formed on the substrate, the second electrode is sleeved outside the first electrode, the dielectric layer is arranged between the first electrode and the second electrode, and the barrier layer is arranged between the dielectric layer and the first electrode.

[0026] The preparation method of the capacitor structure of the present invention first provides a substrate, and then sequentially forms a first electrode, a barrier layer, a dielectric layer and a second electrode on the substrate, wherein the second electrode is sleeved outside the first electrode, and the dielectric layer is arranged between the first electrode and the second electrode, so that charge storage can be realized. Moreover, the barrier layer is arranged between the dielectric layer and the first electrode, so that the first electrode can be prevented from participating in the formation process of the dielectric layer, resulting in poor quality of the dielectric layer, thereby improving the formation quality of the dielectric layer to meet the requirements of high capacitance value and low leakage.

[0027] In one embodiment, the step of sequentially forming a first electrode, a barrier layer, a dielectric layer, and a second electrode on the substrate includes:

[0028] Depositing an electrode material on the substrate and patterning it to form a first electrode, wherein the first electrode is a ring structure with a center line perpendicular to the substrate;

[0029] forming a barrier layer on the top and inner and outer walls of the annular structure;

[0030] Covering the barrier layer with a dielectric layer, wherein the dielectric layer fills the space in the annular structure;

[0031] A second electrode is covered on the dielectric layer.

[0032] In one embodiment, the substrate is a strip structure, and the first electrode, the barrier layer, the dielectric layer, and the second electrode are sequentially formed on the substrate, including:

[0033] forming a first electrode on the strip structure, wherein the first electrode is disposed around the strip structure;

[0034] forming a barrier layer on the first electrode, wherein the barrier layer is disposed around the first electrode;

[0035] forming a dielectric layer on the barrier layer, wherein the dielectric layer is disposed around the barrier layer;

[0036] A second electrode is formed on the dielectric layer, and the second electrode is disposed around the dielectric layer.

[0037] In one embodiment, the preparation method further comprises:

[0038] After forming the second electrode, rapid thermal annealing is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic diagram of a dielectric layer growth process in the related art;

[0041] Figure 2 is a cross-sectional schematic diagram of a capacitor structure provided in an embodiment;

[0042] Figure 3 Provided in one embodiment Figure 2 Schematic diagram of the cross section along the AA' direction;

[0043] Figure 4 is a cross-sectional schematic diagram of another capacitor structure provided in an embodiment;

[0044] Figure 5 Provided in one embodiment Figure 4 Schematic diagram of the cross section along the BB' direction;

[0045] Figure 6 is a cross-sectional schematic diagram of another capacitor structure provided in an embodiment;

[0046] Figure 7 A schematic diagram of the structure of a memory provided in an embodiment;

[0047] Figure 8 A schematic diagram of the structure of another memory provided in an embodiment;

[0048] Fig. 9 is a flow chart of a method for preparing a capacitor structure provided in an embodiment;

[0049] Fig.10 is a flow chart of another method for preparing a capacitor structure provided in an embodiment;

[0050] Fig.11 is a schematic cross-sectional view of a structure obtained in step S1001 in a method for preparing a capacitor structure provided in an embodiment;

[0051] Fig.12 is a schematic cross-sectional view of a structure obtained in step S1002 in a method for preparing a capacitor structure provided in an embodiment;

[0052] Fig.13 is a schematic cross-sectional view of a structure obtained in step S1003 in a method for preparing a capacitor structure provided in an embodiment;

[0053] Fig.14 is a schematic cross-sectional view of a structure obtained in step S1004 in a method for preparing a capacitor structure provided in an embodiment;

[0054] Fig.15 is a schematic cross-sectional view of a structure obtained in step S1005 in a method for preparing a capacitor structure provided in an embodiment;

[0055] Fig.16 is a schematic cross-sectional view of a structure obtained in step S1006 in a method for preparing a capacitor structure provided in an embodiment;

[0056] Fig.17 is a flow chart of a method for preparing another capacitor structure provided in an embodiment;

[0057] Fig.18 is a schematic cross-sectional view of a structure obtained in step S1701 in a method for preparing a capacitor structure provided in an embodiment;

[0058] Fig.19 is a schematic cross-sectional view of a structure obtained in step S1702 in a method for preparing a capacitor structure provided in an embodiment;

[0059] Fig. 20 is a schematic cross-sectional view of a structure obtained in step S1703 in a method for preparing a capacitor structure provided in an embodiment;

[0060] Fig.21is a schematic cross-sectional view of a structure obtained in step S1704 in a method for preparing a capacitor structure provided in an embodiment;

[0061] Fig. 22 FIG. 1 is a schematic cross-sectional view of a structure obtained in step S1705 in a method for preparing a capacitor structure provided in an embodiment.

[0062] Description of reference numerals:

[0063] 10. substrate, 20. first electrode, 30. second electrode, 40. dielectric layer, 50. barrier layer;

[0064] 61. capacitor structure, 62. semiconductor layer, 63. word line, 64. bit line;

[0065] 71. capacitor structure, 72. semiconductor layer, 73. word line, 74. bit line;

[0066] 80. Electrode materials. DETAILED DESCRIPTION

[0067] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0069] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0070] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0071] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0072] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0073] DRAM mainly uses capacitors to store charge. High-density and high-capacity DRAM requires capacitors that meet the requirements of high capacitance and low leakage. Capacitors are mainly composed of two electrodes set opposite to each other and a dielectric layer set between the two electrodes. The material selection of the dielectric layer is particularly important for achieving high capacitance and low leakage. The dielectric constant of an ideal dielectric layer is greater than 100, and the leakage current is less than 10 -7 A / cm 2 , with a thickness of less than 10nm. Strontium titanate is a material with a high dielectric constant. If a strontium titanate film with a thickness of less than 10nm is obtained, it can be used in the capacitor structure of DRAM.

[0074] Figure 1 Schematic diagram of the dielectric layer growth process in the related art, such as Figure 1 As shown, when the strontium titanate film is grown in the related art, the ruthenium (Ru) electrode first reacts with the oxygen source, so that the surface of the ruthenium electrode becomes a ruthenium dioxide (RuO2) layer. Then the titanium source introduced may react incompletely with part of the ruthenium dioxide layer, forming a titanium dioxide (TiO2) layer on part of the ruthenium electrode, and the part of the ruthenium dioxide layer that reacts at the same time turns back into a ruthenium electrode. Then the strontium source introduced reacts with the oxygen source to form a strontium oxide layer on the titanium dioxide layer. However, in the early stage of the formation of the strontium oxide layer, after the strontium source is introduced and before the oxygen source is introduced, part of the ruthenium dioxide layer first reacts with the introduced strontium source as an oxygen source. Due to the presence of carbon impurities on the surface of the ruthenium electrode, and the oxygen content of ruthenium oxide is not too much, it is not enough to react completely with the strontium precursor, so an incomplete reaction occurs, and compounds containing carbon impurities such as strontium carbonate (SrCO3) are generated. These impurity compounds will affect the quality of the strontium titanate film, causing the dielectric constant of the strontium titanate film to be low, thereby reducing the capacitance performance. At this time, the proportion of the low dielectric constant in the strontium titanate film is relatively high, causing the dielectric constant of the strontium titanate film to be less than 80.

[0075] Based on this, the present invention provides a capacitor structure and a preparation method thereof, a memory, and an electronic device. By adding a barrier layer between the ruthenium electrode and the dielectric layer, the oxidation of the electrode interface can be suppressed without increasing the size of the device. In this way, when a strontium titanate film is formed on the ruthenium electrode, an incomplete reaction between the strontium titanate precursor and the oxide layer formed on the surface of the ruthenium electrode can be avoided, and the formation of the strontium titanate film will not be affected, thereby improving the quality of the strontium titanate film, so that the dielectric constant of the strontium titanate is greater than 100 and the leakage current is less than 10 -7 A / cm 2 , with a thickness of less than 10nm. This reduces leakage while increasing the dielectric constant of the dielectric layer, significantly improving the storage capacity of the capacitor and achieving a capacitor with high capacitance and low leakage.

[0076] Figure 2 A cross-sectional schematic diagram of a capacitor structure provided by the present invention, such as Figure 2 As shown, the present invention provides a capacitor structure, which includes a substrate 10, a first electrode 20, a second electrode 30, a dielectric layer 40 and a barrier layer 50. The first electrode 20 is arranged on the substrate 10, and the second electrode 30 is sleeved outside the first electrode 20. The dielectric layer 40 is arranged between the first electrode 20 and the second electrode 30. The barrier layer 50 is arranged between the dielectric layer 40 and the first electrode 20.

[0077] In this embodiment, the capacitor structure includes a substrate 10, a first electrode 20, a second electrode 30, a dielectric layer 40 and a barrier layer 50. The first electrode 20 is arranged on the substrate 10, the second electrode 30 is sleeved outside the first electrode 20, and the dielectric layer 40 is arranged between the first electrode 20 and the second electrode 30, so that charge storage can be realized. Moreover, the barrier layer 50 is arranged between the dielectric layer 40 and the first electrode 20, which can prevent the carbon impurities on the surface of the first electrode 20 from participating in the formation process of the dielectric layer 40 to generate strontium carbonate and affect the quality of the strontium titanate film, thereby causing the dielectric constant of the strontium titanate film to be low, resulting in poor quality of the dielectric layer 40, so that the formation quality of the dielectric layer 40 can be improved to meet the requirements of high capacitance value and low leakage.

[0078] Exemplarily, the substrate 10 may be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0079] In one embodiment, the material of the first electrode 20 can be a metal element such as ruthenium or tungsten, or a conductive metal compound such as titanium nitride or tantalum nitride. Exemplarily, the material of the first electrode 20 is ruthenium, which is conducive to the formation of a strontium titanate film.

[0080] Optionally, the thickness of the first electrode 20 is 5 nm to 15 nm, such as 5 nm, 7.5 nm, 10 nm, 12.5 nm, 15 nm, etc., to meet the requirement of device size miniaturization.

[0081] Optionally, the material of the second electrode 30 may be a metal element such as ruthenium or tungsten, or a conductive metal compound such as titanium nitride or tantalum nitride. Exemplarily, the material of the first electrode 20 is the same as that of the second electrode 30 .

[0082] Optionally, the thickness of the second electrode 30 is 5 nm to 15 nm, such as 5 nm, 7.5 nm, 10 nm, 12.5 nm, 15 nm, etc., to meet the requirement of device size miniaturization.

[0083] In one embodiment, the material of the dielectric layer 40 is strontium titanate, and the thickness of the dielectric layer 40 is 5 nm to 15 nm, such as 5 nm, 7.5 nm, 10 nm, 12.5 nm, 15 nm, etc.

[0084] In this embodiment, the material of the dielectric layer 40 is strontium titanate, so that the dielectric layer 40 has an ultra-high dielectric constant. In addition, the thickness of the dielectric layer 40 is 5nm to 15nm, which is conducive to realizing a high-density and large-capacity memory.

[0085] Exemplarily, the dielectric layer 40 may be doped with one of silicon (Si), hafnium (Hf), yttrium (Y), aluminum (Al), zirconium (Zr), and gadolinium (Gd).

[0086] Optionally, the thickness of the dielectric layer 40 is 5 nm to 10 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc., to meet the requirement of device size miniaturization.

[0087] Exemplarily, the material of the barrier layer 50 is titanium.

[0088] In this embodiment, the material of the barrier layer 50 is titanium, which can, on the one hand, block the oxygen source introduced during the growth of the strontium titanate film from reacting with the ruthenium electrode, and on the other hand, the titanium dioxide layer generated by the reaction of titanium and the oxygen source can serve as a seed layer for the growth of the strontium titanate film.

[0089] Optionally, the thickness of the blocking layer 50 is 0.5 nm to 2 nm, such as 0.5 nm, 0.75 nm, 1 nm, 1.25 nm, 1.5 nm, 1.75 nm, 2 nm, etc.

[0090] In this embodiment, the thickness of the barrier layer 50 is 0.5 nm to 2 nm, which will not affect the miniaturization of the device size.

[0091] Exemplarily, the thickness of the barrier layer 50 is 0.5 nm to 1 nm, such as 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, etc., which meets the requirements of device size miniaturization.

[0092] Figure 3 The present invention provides Figure 2 Schematic diagram of the cross section in the AA' direction, combined with Figure 2 and Figure 3 In one embodiment, the first electrode 20 is an annular structure whose center line is perpendicular to the substrate 10, the barrier layer 50 covers all exposed surfaces of the first electrode 20, the dielectric layer 40 covers all exposed surfaces of the barrier layer 50 and fills the space within the annular structure, and the second electrode 30 covers all exposed surfaces of the dielectric layer 40 outside the annular structure.

[0093] In this embodiment, the first electrode 20 is an annular structure whose center line is perpendicular to the substrate 10, the barrier layer 50 covers all exposed surfaces of the first electrode 20, and the dielectric layer 40 covers all exposed surfaces of the barrier layer 50 and fills the space within the annular structure, which is beneficial to increase the thickness of the dielectric layer 40, thereby reducing the proportion of the low dielectric constant portion in the strontium titanate film, thereby improving the dielectric constant of the strontium titanate film.

[0094] Figure 4 A cross-sectional schematic diagram of another capacitor structure provided by the present invention, Figure 5 The present invention provides Figure 4 Schematic diagram of the cross section in the BB' direction, combined with Figure 4 and Figure 5 In another embodiment, the first electrodes 20 are spaced apart from each other and distributed on the substrate 10 , and the barrier layer 50 , the dielectric layer 40 and the second electrode 30 sequentially cover all exposed surfaces of the first electrodes 20 and the surfaces of the substrate 10 exposed between the first electrodes 20 .

[0095] Figure 6 A cross-sectional schematic diagram of another capacitor structure provided by the present invention is shown in FIG. Figure 6 As shown, in another embodiment, the substrate 10 is a strip structure, the first electrode 20 is arranged around the strip structure, the barrier layer 50 is arranged around the first electrode 20 , the dielectric layer 40 is arranged around the barrier layer 50 , and the second electrode 30 is arranged around the dielectric layer 40 .

[0096] In this embodiment, the substrate 10 is a strip structure, the first electrode 20 is arranged around the strip structure, the barrier layer 50 is arranged around the first electrode 20, the dielectric layer 40 is arranged around the barrier layer 50, the second electrode 30 is arranged around the dielectric layer 40, and the capacitor structure is a vertical stacking structure, which can further improve the storage density of the memory.

[0097] Based on the same inventive concept, the present invention further provides a memory, which includes the capacitor structure provided by any of the above embodiments.

[0098] In this embodiment, the memory includes the above capacitor structure, which can form a high-quality dielectric layer, so that the capacitor can meet the requirements of high capacitance and low leakage at the same time.

[0099] Figure 7 A schematic diagram of the structure of a memory provided by the present invention, such as Figure 7 As shown, in one embodiment, the memory includes a capacitor structure 61, a semiconductor layer 62, a word line 63 and a bit line 64, the substrate includes a plurality of semiconductor layers 62 spaced apart along a first horizontal direction and a second horizontal direction, each semiconductor layer 62 is a strip structure extending along a vertical direction, the word line 63 extends along the first horizontal direction and is connected to the middle of each semiconductor layer 62 spaced apart along the first horizontal direction, the bit line 64 extends along the second horizontal direction and is connected to the first end of each semiconductor layer 62 spaced apart along the second horizontal direction, and the capacitor structure 61 is connected to the second end of the semiconductor layer 62.

[0100] For example, a shallow trench isolation structure (STI) may be formed in the substrate, and the shallow trench isolation structure may isolate a plurality of active areas (AA) arranged at intervals in the substrate to form a semiconductor layer 62. The active area may be a P-type active area or an N-type active area. The P-type active area may form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) device, and the N-type active area may form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) device.

[0101] In an embodiment where the substrate includes a P-type substrate, a source region and a drain region can be formed by injecting N-type ions; correspondingly, in an embodiment where the substrate includes an N-type substrate, a source region and a drain region can be formed by injecting P-type ions. Among them, one of the source region and the drain region is connected to the bit line, and the other is connected to the capacitor. The disclosed embodiment does not specifically limit the types of P-type ions and N-type ions. As an example, P-type ions may include but are not limited to any one or more of boron (Boron, B) ions, gallium (Magnesium, Mg) ions or indium (Indium, In) ions, etc., and N-type impurity ions may include but are not limited to one or more of phosphorus (Phosphorus, P) ions, arsenic (Arsenic, As) ions or antimony (Antimony, Sb) ions.

[0102] Figure 8 A schematic diagram of the structure of another memory provided by the present invention, such as Figure 8 As shown, in another embodiment, the memory includes a capacitor structure 71, a semiconductor layer 72, a word line 73 and a bit line 74, the substrate is a strip structure, the strip structure is a semiconductor layer 72, the word line 73 extends in the vertical direction and is connected to the middle of each semiconductor layer 72 spaced apart along the vertical direction, the bit line 74 extends in the horizontal direction and is connected to the first end of each semiconductor layer 72 spaced apart along the horizontal direction, and the capacitor structure 71 is arranged around the semiconductor layer 72 and is connected to the second end of the semiconductor layer 72.

[0103] Based on the same inventive concept, the present invention further provides an electronic device, which includes the memory provided by the above embodiment.

[0104] In this embodiment, the electronic device includes the above-mentioned memory, which has high storage density and can realize high-density and large-capacity data storage.

[0105] Based on the same inventive concept, the present invention provides a method for preparing a capacitor structure, such as Fig. 9 As shown, the preparation method comprises the following steps:

[0106] S901, providing a substrate.

[0107] S902, forming a first electrode, a barrier layer, a dielectric layer and a second electrode in sequence on the substrate.

[0108] The second electrode is sleeved outside the first electrode, the dielectric layer is arranged between the first electrode and the second electrode, and the barrier layer is arranged between the dielectric layer and the first electrode.

[0109] In this embodiment, the preparation method of the capacitor structure first provides a substrate, and then sequentially forms a first electrode, a barrier layer, a dielectric layer, and a second electrode on the substrate, wherein the second electrode is sleeved outside the first electrode, and the dielectric layer is disposed between the first electrode and the second electrode, so that charge storage can be realized. Moreover, the barrier layer is disposed between the dielectric layer and the first electrode, so that the first electrode can be prevented from participating in the formation process of the dielectric layer, resulting in poor quality of the dielectric layer, thereby improving the formation quality of the dielectric layer to meet the requirements of high capacitance value and low leakage.

[0110] In one embodiment, Fig.10 As shown, the preparation method specifically comprises the following steps:

[0111] S1001, providing a substrate.

[0112] Fig.11 A schematic cross-sectional view of the structure obtained in step S1001 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.11 As shown, a substrate 10 is provided as a growth base.

[0113] Exemplarily, the material of the substrate is silicon (Si).

[0114] S1002, depositing electrode material on the substrate.

[0115] Fig.12 A schematic cross-sectional view of the structure obtained in step S1002 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.12 As shown, an electrode material layer 80 is deposited on the substrate 10 .

[0116] Optionally, the deposition process may include but is not limited to one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0117] Exemplarily, the first electrode is thin, and the electrode material can be deposited by ALD, and the interface roughness is low, and chemical mechanical polishing (English: Chemical Mechanical Polishing, abbreviated: CMP) is not required.

[0118] S1003, patterning the electrode material to form a first electrode.

[0119] Fig.13A schematic cross-sectional view of the structure obtained in step S1003 in the method for preparing a capacitor structure provided by an embodiment of the present invention, as shown in FIG. Fig.13 As shown, the electrode material layer 80 is patterned to form the first electrode 20 .

[0120] Optionally, a mask layer is first formed on the electrode material, and then the electrode material is etched through the hollowed-out area in the mask layer to achieve the patterning of the electrode material. Exemplarily, the mask layer may include a hard mask layer, and the hard mask layer may be a single-layer structure or a multi-layer stacked structure. A photoresist is coated on the hard mask layer, and a patterned photoresist layer is formed through a series of steps such as exposure and development, and the patterned photoresist layer defines the position and shape of the etching. Etching may include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP).

[0121] It can be understood that by executing steps S1101-S110, electrode material can be deposited on the substrate and patterned to form a first electrode, wherein the first electrode is a ring-shaped structure with a center line perpendicular to the substrate.

[0122] S1004, forming a barrier layer on the top and inner and outer walls of the annular structure.

[0123] Fig.14 A schematic cross-sectional view of the structure obtained in step S1004 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.14 As shown, all exposed surfaces of the first electrode 20 are covered with the barrier layer 50 .

[0124] Optionally, the barrier layer is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0125] For example, the barrier layer is thin and can be formed by ALD, and the interface roughness is low, so CMP is not required.

[0126] S1005, covering the barrier layer with a dielectric layer, so that the dielectric layer fills the space in the annular structure.

[0127] Fig.15 A schematic cross-sectional view of the structure obtained in step S1005 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.15 As shown, all exposed surfaces of the barrier layer 50 are covered with the dielectric layer 40, and the dielectric layer 40 also fills up the space within the annular structure.

[0128] Optionally, the dielectric layer is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0129] Exemplarily, the dielectric layer is thin and can be formed by ALD, and the interface roughness is low, so CMP is not required.

[0130] S1006, covering the dielectric layer with a second electrode.

[0131] Fig.16 A schematic cross-sectional view of the structure obtained in step S1006 in the method for preparing a capacitor structure according to an embodiment of the present invention, as shown in FIG. Fig.16 As shown, all exposed surfaces of the dielectric layer 40 are covered with the second electrode 30 .

[0132] Optionally, the second electrode is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0133] Exemplarily, the second electrode is thin and can be formed by ALD, and the interface roughness is low, and CMP is no longer required.

[0134] S1007, rapid thermal annealing.

[0135] Exemplarily, the annealing temperature is 500° C. to 600° C., such as 500° C., 510° C., 520° C., 530° C., 540° C., 550° C., 560° C., 570° C., 580° C., 590° C., 600° C., etc. The annealing time is 30s to 120s, such as 30s, 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, etc.

[0136] In another embodiment, Fig.17 As shown, the preparation method specifically comprises the following steps:

[0137] S1701, provide a substrate.

[0138] Fig.18 A schematic cross-sectional view of the structure obtained in step S1701 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.18 As shown, the substrate 10 is a strip-shaped structure, and the strip-shaped structure serves as a growth base.

[0139] Exemplarily, the strip-shaped structures are Si nanowires.

[0140] S1702, forming a first electrode on the strip structure.

[0141] Wherein, the first electrode is arranged around the strip structure.

[0142] Fig.19 A schematic cross-sectional view of the structure obtained in step S1702 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig.19 As shown, a first electrode 20 is surrounded by the strip-shaped structure.

[0143] Optionally, the first electrode is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0144] Exemplarily, the thickness of the first electrode is thin, and the electrode material can be deposited by ALD, and the interface roughness is low, and CMP is no longer required.

[0145] S1703, forming a blocking layer on the first electrode.

[0146] Wherein, the barrier layer is arranged around the first electrode.

[0147] Fig. 20 A schematic cross-sectional view of the structure obtained in step S1703 in the method for preparing a capacitor structure provided in an embodiment of the present invention, as shown in FIG. Fig. 20 As shown, each first electrode 20 is surrounded by a barrier layer 50 .

[0148] Optionally, the barrier layer is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0149] For example, the barrier layer is thin and can be formed by ALD, and the interface roughness is low, so CMP is not required.

[0150] S1704, forming a dielectric layer on the barrier layer, wherein the dielectric layer is disposed around the barrier layer.

[0151] Fig.21 A schematic cross-sectional view of the structure obtained in step S1704 in the method for preparing a capacitor structure according to an embodiment of the present invention, as shown in FIG. Fig.21 As shown, each barrier layer 50 is surrounded by a dielectric layer 40 .

[0152] Optionally, the dielectric layer is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0153] Exemplarily, the dielectric layer is thin and can be formed by ALD, and the interface roughness is low, so CMP is not required.

[0154] S1705, forming a second electrode on the dielectric layer, wherein the second electrode is disposed around the dielectric layer.

[0155] Fig. 22 A schematic cross-sectional view of the structure obtained in step S1705 in the method for preparing a capacitor structure according to an embodiment of the present invention, as shown in FIG. Fig. 22 As shown, each dielectric layer 40 is surrounded by a second electrode 30 .

[0156] Optionally, the second electrode is formed by one or more processes such as CVD, ALD, HDP, and SOD.

[0157] Exemplarily, the second electrode is thin and can be formed by ALD, and the interface roughness is low, and CMP is no longer required.

[0158] S1706, rapid thermal annealing.

[0159] Exemplarily, the annealing temperature is 500° C. to 600° C., such as 500° C., 510° C., 520° C., 530° C., 540° C., 550° C., 560° C., 570° C., 580° C., 590° C., 600° C., etc. The annealing time is 30s to 120s, such as 30s, 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, etc.

[0160] It should be understood that although Fig. 9 , Fig.10 , Fig.17 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig. 9 , Fig.10 , Fig.17 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0161] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A capacitor structure, characterized in that: The capacitor structure comprises: substrate; A first electrode is disposed on the substrate; A second electrode, sleeved outside the first electrode; a dielectric layer, disposed between the first electrode and the second electrode; The barrier layer is arranged between the dielectric layer and the first electrode.

2. The capacitor structure according to claim 1, characterized in that: The material of the dielectric layer is strontium titanate and is doped with one of silicon, hafnium, yttrium, aluminum, zirconium and gadolinium. The thickness of the dielectric layer is 5nm-15nm.

3. The capacitor structure according to claim 2, characterized in that: The material of the barrier layer is titanium.

4. The capacitor structure according to claim 3, characterized in that: The thickness of the barrier layer is 0.5 nm to 2 nm.

5. The capacitor structure according to any one of claims 1 to 4, characterized in that: The first electrode is an annular structure with a center line perpendicular to the substrate, the barrier layer covers all exposed surfaces of the first electrode, the dielectric layer covers all exposed surfaces of the barrier layer and fills the space within the annular structure, and the second electrode covers all exposed surfaces of the dielectric layer outside the annular structure.

6. The capacitor structure according to any one of claims 1 to 4, characterized in that: The substrate is a strip structure, the first electrode is arranged around the strip structure, the barrier layer is arranged around the first electrode, the dielectric layer is arranged around the barrier layer, and the second electrode is arranged around the dielectric layer.

7. A memory, characterized in that: The memory comprises the capacitor structure according to any one of claims 1-6.

8. The memory according to claim 7, characterized in that: The memory also includes a semiconductor layer, a word line and a bit line. The substrate includes a plurality of semiconductor layers spaced apart along a first horizontal direction and a second horizontal direction, each of the semiconductor layers is a strip structure extending along a vertical direction. The word line extends along the first horizontal direction and is connected to the middle of each of the semiconductor layers spaced apart along the first horizontal direction. The bit line extends along the second horizontal direction and is connected to the first end of each of the semiconductor layers spaced apart along the second horizontal direction. The capacitor structure is connected to the second end of the semiconductor layer.

9. The memory according to claim 7, characterized in that: The memory also includes a semiconductor layer, a word line and a bit line. The substrate is a strip structure, and the strip structure is a semiconductor layer. The word line extends in a vertical direction and is connected to the middle of each semiconductor layer spaced apart along the vertical direction. The bit line extends in a horizontal direction and is connected to the first end of each semiconductor layer spaced apart along the horizontal direction. The capacitor structure is arranged around the semiconductor layer and is connected to the second end of the semiconductor layer.

10. An electronic device, characterized in that: The electronic device comprises the memory as claimed in any one of claims 7 to 9.

11. A method for preparing a capacitor structure, characterized in that: The preparation method comprises: providing a substrate; A first electrode, a barrier layer, a dielectric layer and a second electrode are sequentially formed on the substrate, the second electrode is sleeved outside the first electrode, the dielectric layer is arranged between the first electrode and the second electrode, and the barrier layer is arranged between the dielectric layer and the first electrode.

12. The preparation method according to claim 11, characterized in that: The step of sequentially forming a first electrode, a barrier layer, a dielectric layer, and a second electrode on the substrate comprises: Depositing an electrode material on the substrate and patterning it to form a first electrode, wherein the first electrode is a ring structure with a center line perpendicular to the substrate; forming a barrier layer on the top and inner and outer walls of the annular structure; Covering the barrier layer with a dielectric layer, wherein the dielectric layer fills the space in the annular structure; A second electrode is covered on the dielectric layer.

13. The preparation method according to claim 11, characterized in that: The substrate is a strip-shaped structure, and the first electrode, the barrier layer, the dielectric layer, and the second electrode are sequentially formed on the substrate, including: forming a first electrode on the strip structure, wherein the first electrode is disposed around the strip structure; forming a barrier layer on the first electrode, wherein the barrier layer is disposed around the first electrode; forming a dielectric layer on the barrier layer, wherein the dielectric layer is disposed around the barrier layer; A second electrode is formed on the dielectric layer, and the second electrode is disposed around the dielectric layer.

14. The preparation method according to any one of claims 11 to 13, characterized in that: The preparation method further comprises: After forming the second electrode, rapid thermal annealing is performed.

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