Hand-in-hand type self-current-equalizing silicon carbide power module

Abstract

The invention relates to a hand-in-hand type self-current-equalizing silicon carbide power module. The power module comprises a metal substrate; a conductive metal layer is arranged on the upper surface of the metal substrate, and a plurality of direct-current power terminals, a plurality of alternating-current power terminals and a plurality of silicon carbide chips are arranged on the conductive metal layer; wherein the plurality of direct-current power terminals, the plurality of alternating-current power terminals and the plurality of silicon carbide chips form a plurality of mutual inductance elimination loops; according to the mutual inductance elimination loop, the parasitic inductance in the loop can be reduced by utilizing the mutual inductance cancellation effect between the two direct-current power terminals with opposite current directions, and when the current in the mutual inductance elimination loop adjacent to the mutual inductance elimination loop changes, the parasitic inductance in the loop can be reduced. An induced voltage is generated to suppress current imbalance caused by a mutual inductance cancellation loop adjacent to the mutual inductance cancellation loop. The method has an excellent current sharing effect when being applied to a power module with multiple parallel chips or under other complicated and changeable application working conditions, the problem of current stress difference caused by loss of devices is avoided, and the reliability is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power modules, and in particular relates to a hand-in-hand type self-current equalizing silicon carbide power module. Background Art

[0002] With the rapid development of new energy power generation and new energy vehicles in my country, the power processing capacity requirements for power modules are also increasing. In order to meet higher power requirements, multiple silicon carbide chips need to be integrated through module packaging to operate in parallel. However, in power modules with multiple parallel chips, due to the differences in the characteristics of each chip, unbalanced currents can cause device losses and current stress differences.

[0003] The existing traditional methods for suppressing uneven current in modules include source resistance method, source inductance matching method, active current equalization control method, chip screening method, etc., or new layout schemes are used to reduce parameter inconsistency between circuits. However, each of these methods has its limitations. The source resistance method will increase power loss; the source inductance matching method is complex in design; the active current equalization control method is costly and the control circuit is complex; the chip screening method is costly and it is difficult to completely eliminate the current imbalance caused by parameters. Under complex and changeable actual application conditions, the current equalization effect of these methods is difficult to guarantee. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a hand-in-hand type self-current equalizing silicon carbide power module. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a hand-in-hand type self-current equalizing silicon carbide power module, comprising: a metal substrate; a conductive metal layer is arranged on the upper surface of the metal substrate, and a plurality of DC power terminals, a plurality of AC power terminals and a plurality of silicon carbide chips are arranged on the conductive metal layer; wherein, two DC power terminals with opposite current directions among the plurality of DC power terminals, two AC power terminals among the plurality of AC power terminals, and two silicon carbide chips among the plurality of silicon carbide chips constitute a mutual inductance elimination loop; the mutual inductance elimination loop can utilize the mutual inductance cancellation effect between the two DC power terminals with opposite current directions to reduce the parasitic inductance within the mutual inductance elimination loop, and when the current in the mutual inductance elimination loop adjacent to the mutual inductance elimination loop changes, an induced voltage is generated to suppress the current imbalance caused by the mutual inductance elimination loop adjacent to the mutual inductance elimination loop.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: In view of the problem that the current equalization effect applied to the existing silicon carbide power module is difficult to ensure, the present invention proposes a hand-in-hand type self-current equalization silicon carbide power module, which utilizes multiple DC power terminals, AC power terminals and silicon carbide chips to form multiple mutual inductance elimination circuits. On the one hand, the mutual inductance elimination circuit can utilize the DC terminals with opposite commutation directions inside the circuit to produce a mutual inductance cancellation effect and reduce the parasitic inductance in the mutual inductance elimination circuit. On the other hand, it can respond to the unbalanced current appearing in other circuits to generate an induced voltage to suppress the current imbalance phenomenon. When applied to power modules with multiple parallel chips or other complex and changeable application conditions, it has an excellent current equalization effect, avoids the problem of current stress difference caused by device loss, and has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a three-dimensional structural diagram of a hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention;

[0008] Figure 2 is a front view of a hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention;

[0009] Figure 3 It is a layered schematic diagram of a hand-in-hand type self-current equalizing silicon carbide power module provided in an embodiment of the present invention;

[0010] Figure 4 is a first top view of a hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention;

[0011] Figure 5 is a second top view of the hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention;

[0012] Figure 6 is a circuit connection diagram of multiple mutual inductance elimination loops provided in an embodiment of the present invention;

[0013] Figure 7 is the current direction in the first mutual inductance elimination loop a provided in an embodiment of the present invention;

[0014] Figure 8 It is a schematic diagram of the composition of a driving circuit provided by an embodiment of the present invention.

[0015] Reference numerals:

[0016] 1. First silicon carbide chip; 2. Second silicon carbide chip; 3. Third silicon carbide chip; 4. Fourth silicon carbide chip; 5. Fifth silicon carbide chip; 6. Sixth silicon carbide chip; 7. Seventh silicon carbide chip; 8. Eighth silicon carbide chip; 9-34. Metal bonding wire; 35. Under-board metal layer; 36. Metal substrate; 37. First conductive metal layer; 38. Second conductive metal layer; 39A. Third conductive metal layer (left side); 39B. Third conductive metal layer (right side); 40. First DC + DC power terminal; 41, first DC － DC power terminal; 42, second DC + DC power terminal; 43, second DC － DC power terminal; 44, third DC + DC power terminal; 45, third DC － DC power terminal; 46, fourth DC － DC power terminal; 47, fourth DC + DC power terminal; 48, fifth DC + DC power terminal; 49, fifth DC － DC power terminal; 50, sixth DC － DC power terminal; 51, sixth DC + DC power terminal; 52, seventh DC － DC power terminal; 53, seventh DC + DC power terminal; 54, eighth DC － DC power terminal; 55, eighth DC + DC power terminal; 56, first AC power terminal; 57, second AC power terminal; 58, third AC power terminal; 59, fourth AC power terminal; 60, fifth AC power terminal; 61, sixth AC power terminal; 62, seventh AC power terminal; 63, eighth AC power terminal; 64, source drive terminal; 65, first drive metal layer; 66, second drive metal layer; 67, third drive metal layer; 68, drive resistor; 69, gate drive terminal; 70, first drive circuit; 71, second drive circuit; 73, third drive circuit; 74, fifth drive circuit; 75, sixth drive circuit; 76, seventh drive circuit; 77, eighth drive circuit; a, first mutual inductance elimination circuit; b, second mutual inductance elimination circuit; c, third mutual inductance elimination circuit; d, fourth mutual inductance elimination circuit; M aa , the inductance in the first mutual inductance elimination loop a cancels out; M ab , the inductances of the first mutual inductance elimination loop a and the second mutual inductance elimination loop b cancel each other; M bb , the inductance in the second mutual inductance elimination loop b cancels out; M bc, the inductances of the second mutual inductance elimination loop b and the third mutual inductance elimination loop c cancel each other; M cc , the inductance in the third mutual inductance elimination loop c cancels out; M cd , the inductances of the third mutual inductance elimination loop c and the fourth mutual inductance elimination loop d cancel each other; M dd , the inductance in the fourth mutual inductance elimination loop d cancels each other; M da , the inductance of the fourth mutual inductance elimination loop d cancels out the inductance of the first mutual inductance elimination loop a. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0018] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0019] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0020] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0021] In view of the problem that the current equalization effect of existing silicon carbide power modules is difficult to ensure, the present invention proposes a hand-in-hand self-current equalization silicon carbide power module. The technical solution proposed by the present invention is now described in detail in conjunction with the accompanying drawings.

[0022] Figure 1 is a three-dimensional structural diagram of a hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention; Figure 2 is a front view of a hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention; Figure 3 1 is a schematic diagram of the layering of the hand-in-hand self-current balancing silicon carbide power module provided by the embodiment of the present invention. Figure 3 As shown, the hand-in-hand type self-current equalizing silicon carbide power module includes: a metal substrate 36; a conductive metal layer is provided on the upper surface of the metal substrate 36, and a plurality of DC power terminals, a plurality of AC power terminals and a plurality of silicon carbide chips are provided on the conductive metal layer; wherein, two DC power terminals with opposite current directions among the plurality of DC power terminals, two AC power terminals among the plurality of AC power terminals, and two silicon carbide chips among the plurality of silicon carbide chips constitute a mutual inductance elimination loop; the mutual inductance elimination loop can utilize the mutual inductance cancellation effect between the two DC power terminals with opposite current directions to reduce the parasitic inductance within the mutual inductance elimination loop, and when the current in the mutual inductance elimination loop adjacent to the mutual inductance elimination loop changes, an induced voltage is generated to suppress the current imbalance caused by the mutual inductance elimination loop adjacent to the mutual inductance elimination loop.

[0023] Here, the metal substrate 36 is an aluminum nitride substrate. The hand-in-hand type self-current equalizing silicon carbide power module also includes: a sub-board metal layer 35; the sub-board metal layer 35 is arranged on the lower surface of the metal substrate 36. The sub-board metal layer 35 is used for heat dissipation, and the heat dissipation method includes natural air cooling, forced air cooling and liquid cooling.

[0024] Figure 4 It is a first top view of the hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention. Figure 5 FIG. 2 is a second top view of the hand-in-hand type self-current equalizing silicon carbide power module provided by an embodiment of the present invention. Figure 4 and Figure 5As shown, the hand-in-hand type self-current equalizing silicon carbide power module also includes: a plurality of metal bonding wires (black thick lines numbered 9-32 in the figure); the conductive metal layer includes: a first conductive metal layer 37, on which a second conductive metal layer 38 and a third conductive metal layer 39 (specifically 39A and 39B) are arranged; the third conductive metal layer 39A and the third conductive metal layer 39B are mirror-arranged on both sides of the second conductive metal layer 38; the first conductive metal layer 37, the second conductive metal layer 38 and the third conductive metal layer 39 are electrically connected through a plurality of metal bonding wires; a plurality of DC power terminals (numbered 40-55 in the figure) are partially arranged on the second conductive metal layer 38, and the other part is arranged on the third conductive metal layer 39; a plurality of AC power terminals (numbered 56-63 in the figure) are arranged on the first conductive metal layer 37; a plurality of silicon carbide chips are partially arranged on the first conductive metal layer 37, and the other part is arranged on the second conductive metal layer 38.

[0025] Here, if Figure 4 and Figure 5 As shown, the first conductive metal layer 37 is in a rectangular shape, the second conductive metal layer 38 is in a "W" shape, and the third conductive metal layer 39 is in two symmetrical "T" shapes.

[0026] Here, the plurality of DC power terminals include: a plurality of DC + DC power terminals and multiple DC - DC power terminals; multiple DC + The DC power terminals are arranged on the second conductive metal layer 38. - The DC power terminals are arranged on the third conductive metal layer 39. + DC power terminals and multiple DC - The DC power terminals are alternately arranged at equal intervals around the center of the second conductive metal layer 38 so that each DC power terminal is adjacent to two DC power terminals whose current directions are opposite to that of the DC power terminal.

[0027] Here, multiple DCs + The DC power terminal specifically includes: a first DC + DC power terminal 40, second DC + DC power terminal 42, third DC + DC power terminal 44, fourth DC + DC power terminal 47, fifth DC + DC power terminal 48, sixth DC + DC power terminal 51, seventh DC + DC power terminal 53 and the eighth DC + DC power terminal 55.

[0028] Here, multiple DCs- The DC power terminal specifically includes: a first DC - DC power terminal 41, second DC - DC power terminal 43, third DC - DC power terminal 45, fourth DC - DC power terminal 46, fifth DC - DC power terminal 49, sixth DC - DC power terminal 50, seventh DC - DC power terminal 52 and the eighth DC - DC power terminal 54.

[0029] Here, multiple DCs + DC power terminals and multiple DC - The DC power terminals are alternately arranged equidistantly around the center of the second conductive metal layer 38, which can be understood as: + DC power terminals and DC - The DC terminals together form a square shape, one DC + The two terminals closest to the DC power terminal are both DC - DC power terminal, one DC - The two terminals closest to the DC power terminal are both DC + DC power terminals, DC + DC power terminals and DC - The circulation directions of the DC power terminals are opposite to each other to achieve the effect of mutual inductance cancellation.

[0030] Specifically, the first DC + The right side of the DC power terminal 40 is the first DC － DC power terminal 41, the lower side is the third DC － DC power terminal 45; second DC + To the right of the DC power terminal 42 is the second DC － DC power terminal 43, the left side is the first DC － DC power terminal 41, third DC + The left side of DC power terminal 44 is the second DC － DC power terminal 43, the lower side is the fourth DC － DC power terminal 46, fourth DC + The upper side of the DC power terminal 47 is the third DC － DC power terminal 45, the lower side is the fifth DC － DC power terminal 49, fifth DC + The upper side of the DC power terminal 48 is the fourth DC － DC power terminal 46, the lower side is the sixth DC －DC power terminal 50, sixth DC + The upper side of the DC power terminal 51 is the fifth DC － DC power terminal 49, the right side is the seventh DC － DC power terminal 52, seventh DC + The left side of DC power terminal 53 is the seventh DC － DC power terminal 52, the right side is the eighth DC － DC power terminal 54, eighth DC + The left side of DC power terminal 55 is the eighth DC － DC power terminal 54, the upper side is the third DC － DC power terminal 50, first DC － The left side of the DC power terminal 41 is the first DC + DC power terminal 40, on the right is the second DC + DC power terminal 42, second DC － The left side of DC power terminal 43 is the second DC + DC power terminal 42, on the right is the third DC + DC power terminal 44, third DC － The upper side of the DC power terminal 45 is the first DC + DC power terminal 40, the lower side is the fourth DC + DC power terminal 47, fourth DC － The upper side of the DC power terminal 46 is the third DC + DC power terminal 44, the lower side is the fifth DC + DC power terminal 48, fifth DC － The upper side of the DC power terminal 49 is the fourth DC + DC power terminal 47, the lower side is the sixth DC + DC power terminal 51, sixth DC － The upper side of the DC power terminal 50 is the fifth DC + DC power terminal 48, the lower side is the eighth DC + DC power terminal 55, seventh DC － The left side of the DC power terminal 52 is the sixth DC + DC power terminal 51, the right side is the seventh DC + DC power terminal 53, eighth DC － The left side of DC power terminal 54 is the seventh DC + DC power terminal 53, the right side is the eighth DC + DC power terminal 55.

[0031] Continue to refer to Figure 4 and Figure 5, multiple silicon carbide chips are used to control the current direction of multiple AC power terminals; the multiple silicon carbide chips include: a first silicon carbide chip 1, a second silicon carbide chip 2, a third silicon carbide chip 3, a fourth silicon carbide chip 4, a fifth silicon carbide chip 5, a sixth silicon carbide chip 6, a seventh silicon carbide chip 7 and an eighth silicon carbide chip 8; the first silicon carbide chip 1, the fourth silicon carbide chip 4, the fifth silicon carbide chip 5 and the eighth silicon carbide chip 8 are respectively welded at the four ends of the first conductive metal layer 37, and the second silicon carbide chip 2, the third silicon carbide chip 3, the sixth silicon carbide chip 6 and the seventh silicon carbide chip 7 are respectively welded at the four ends of the second conductive metal layer 38.

[0032] Here, the drain electrodes of the second silicon carbide power chip 2, the third silicon carbide power chip 3, the sixth silicon carbide power chip 6, and the seventh silicon carbide power chip 7 are welded on the second conductive metal layer 38 through pads, and the source electrodes of the silicon carbide power chips on the second conductive metal layer 38 are connected to the first conductive metal layer 37 through metal bonding wires.

[0033] Continue to refer to Figure 4 and Figure 5 , multiple AC power terminals include: a first AC power terminal 56, a second AC power terminal 57, a third AC power terminal 58, a fourth AC power terminal 59, a fifth AC power terminal 60, a sixth AC power terminal 61, a seventh AC power terminal 62 and an eighth AC power terminal 63; the first AC power terminal 56, the second AC power terminal 57, the third AC power terminal 58 and the fourth AC power terminal 59 are evenly arranged between the first silicon carbide chip 1 and the fifth silicon carbide chip 5; the fifth AC power terminal 60, the sixth AC power terminal 61, the seventh AC power terminal 62 and the eighth AC power terminal 63 are evenly arranged between the fourth silicon carbide chip 4 and the eighth silicon carbide chip 8.

[0034] Figure 6 FIG. 1 is a circuit connection diagram of multiple mutual inductance elimination loops provided in an embodiment of the present invention. Figure 6 As shown, a plurality of DC power terminals, a plurality of AC power terminals and a plurality of silicon carbide chips constitute four mutual inductance elimination loops, and the four mutual inductance elimination loops include: a first mutual inductance elimination loop a, a second mutual inductance elimination loop b, a third mutual inductance elimination loop c and a fourth mutual inductance elimination loop d; the first mutual inductance elimination loop a, the second mutual inductance elimination loop b, the third mutual inductance elimination loop c and the fourth mutual inductance elimination loop d are connected in parallel; and the first mutual inductance elimination loop a, the second mutual inductance elimination loop b, the third mutual inductance elimination loop c and the fourth mutual inductance elimination loop d are arranged symmetrically to each other; the DC in the first mutual inductance elimination loop a + The DC power terminal is adjacent to the DC in the second mutual inductance elimination loop b. - DC power terminal, and the DC in the fourth mutual inductance elimination loop d -DC power terminal; DC in the second mutual inductance elimination loop b + The DC power terminal is adjacent to the DC in the first mutual inductance elimination loop a. - DC power terminal, and DC in the third mutual inductance elimination loop c - DC power terminal; DC in the third mutual inductance elimination loop c + The DC power terminal is adjacent to the DC in the second mutual inductance elimination loop b. - DC power terminal, and the DC in the fourth mutual inductance elimination loop d - DC power terminal; the DC in the fourth mutual inductance elimination loop d + The DC power terminal is adjacent to the DC in the first mutual inductance elimination loop a. - DC power terminal, and DC in the third mutual inductance elimination loop c - DC power terminals.

[0035] Here, the four mutual inductance elimination loops together form a hand-in-hand closed loop structure. When the current in any of the mutual inductance elimination loops is unbalanced, an induced voltage will be generated in the adjacent parallel loop, thereby improving the current balance of the parallel loops.

[0036] Here, the second silicon carbide chip 2 and the first silicon carbide chip 1 in the first mutual inductance elimination loop a constitute an upper tube chip and a lower tube chip; the third silicon carbide chip 3 and the fourth silicon carbide chip 4 in the second mutual inductance elimination loop b constitute an upper tube chip and a lower tube chip; the seventh silicon carbide chip 7 and the eighth silicon carbide chip 8 in the third mutual inductance elimination loop c constitute an upper tube chip and a lower tube chip; the sixth silicon carbide chip 6 and the fifth silicon carbide chip 5 in the fourth mutual inductance elimination loop d constitute an upper tube chip and a lower tube chip.

[0037] Here, in the mutual inductance elimination loop, the current flows from the DC + The DC power terminal flows in, passes through the silicon carbide chip set on the second conductive metal layer, the AC power terminal set on the first conductive metal layer, the silicon carbide chip set on the first conductive metal layer, and the DC power terminal set on the third conductive metal layer. - DC power flows out of the terminals.

[0038] For example, Figure 7 is the current direction in the first mutual inductance elimination loop a provided in the embodiment of the present invention, such as Figure 7 As shown, the current is respectively from the first DC + DC power terminal 40, second DC + DC power terminal 42, fourth DC + The DC power terminal 47 flows in, passes through the second silicon carbide chip 2 and the first silicon carbide chip 1, and flows from the first DC - DC power terminal 41 and the third DC- The DC power terminal 45 flows out. + DC power terminal 42 and fourth DC + The DC power terminal 47 is used in conjunction.

[0039] In addition, in the second mutual inductance elimination loop b (not shown in the figure), the current is respectively from the second DC + DC power terminal 42, third DC + DC power terminal 44, fifth DC + The DC power terminal 48 flows in, passes through the third silicon carbide chip 3 and the fourth silicon carbide chip 4, and flows from the second DC - DC power terminal 43 and fourth DC - The DC power flows out of terminal 46.

[0040] Here, in the third mutual inductance elimination loop c (not shown in the figure), the current is respectively from the fifth DC + DC power terminal 48, seventh DC + DC power terminal 53 and the eighth DC + The DC power terminal 55 flows in, passes through the seventh silicon carbide chip 7 and the eighth silicon carbide chip 8, and flows from the sixth DC - DC power terminal 50 and the eighth DC - The DC power flows out of terminal 54.

[0041] Here, in the fourth mutual inductance elimination loop d (not shown in the figure), the current is respectively from the fourth DC + DC power terminal 47, sixth DC + DC power terminal 51 and seventh DC + The DC power terminal 53 flows in, passes through the sixth silicon carbide chip 6 and the fifth silicon carbide chip 5, and is - DC power terminal 49 and seventh DC - The DC power flows out of terminal 52.

[0042] See also Figure 3 The hand-in-hand type self-current equalizing silicon carbide power module also includes: multiple drive circuits (numbered 70-77 in the figure), which are arranged on the metal substrate 36 and symmetrically arranged on the outside of the second conductive metal layer 38; the multiple drive circuits are electrically connected to the multiple silicon carbide chips located on the second conductive metal layer 38 and the third conductive metal layer 39 through multiple metal bonding wires; wherein one drive circuit corresponds to one metal bonding wire, and two metal bonding wires correspond to one silicon carbide chip; multiple drive circuits are used to control the opening or closing of multiple silicon carbide chips.

[0043] Figure 8 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present invention. Figure 8 As shown, each driving circuit includes: a first driving metal layer 65, a second driving metal layer 66, a third driving metal layer 67, a source driving terminal 64, a gate driving terminal 69, and a driving resistor 68; each driving metal layer is used to drive the source driving terminal, the gate driving terminal, and the driving resistor; the first driving metal layer 65, the second driving metal layer 66, and the third driving metal layer 67 are arranged at intervals, the second driving metal layer 66 and the third driving metal layer 67 are electrically connected through the driving resistor 68, the source driving terminal 64 is arranged on the first driving metal layer 65, and the gate driving terminal 69 is arranged on the third driving metal layer 67; the first driving metal layer 66 in a driving circuit is electrically connected to a silicon carbide chip corresponding to a metal bonding wire through a metal bonding wire.

[0044] Here, the source drive terminal 64 specifically refers to a Kelvin source drive terminal. Specifically, the gate of the first silicon carbide chip 1 is connected to the second drive metal layer 66 through a metal bonding wire 9, the source drive terminal 64 is connected to the first drive metal layer 65 through a metal bonding wire 10, and another Kelvin source drive terminal is connected to the third conductive metal layer 39 through a metal bonding wire 25, forming a lower tube commutation loop.

[0045] Here, the gate of the second silicon carbide chip 2 is connected to the second driving metal layer 66 through the metal bonding wire 12, the source driving terminal 64 is connected to the first driving metal layer through the metal bonding wire 11, and the other source driving terminal 64 is connected to the first conductive metal layer 37 through the metal bonding wire 26, forming an upper tube commutation loop.

[0046] Here, the gate of the third silicon carbide chip 3 is connected to the second driving metal layer 66 through a metal bonding wire 13, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 14, and the other source driving terminal 64 is connected to the first conductive metal layer 37 through a metal bonding wire 27, forming an upper tube commutation loop.

[0047] Here, the gate of the fourth silicon carbide chip 4 is connected to the second driving metal layer through a metal bonding wire 16, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 15, and another source driving terminal 64 is connected to the third conductive metal layer 39 through a metal bonding wire 28, forming a lower tube commutation loop.

[0048] Here, the gate of the fifth silicon carbide chip 5 is connected to the second driving metal layer through a metal bonding wire 17, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 18, and another source driving terminal 64 is connected to the third conductive metal layer 39 through a metal bonding wire 29, forming a lower tube commutation loop.

[0049] Here, the gate of the sixth silicon carbide chip 6 is connected to the second driving metal layer through a metal bonding wire 20, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 19, and another source driving terminal 64 is connected to the first conductive metal layer 37 through a metal bonding wire 30, forming an upper tube commutation circuit.

[0050] Here, the gate of the seventh silicon carbide chip 7 is connected to the second driving metal layer through a metal bonding wire 21, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 22, and the other source driving terminal 64 is connected to the first conductive metal layer 37 through a metal bonding wire 31, forming an upper tube commutation circuit.

[0051] Here, the gate of the eighth silicon carbide chip 8 is connected to the second driving metal layer through a metal bonding wire 24, the source driving terminal 64 is connected to the first driving metal layer 65 through a metal bonding wire 23, and another source driving terminal 64 is connected to the third conductive metal layer 39 through a metal bonding wire 32, forming a lower tube commutation loop.

[0052] Corresponding to the hand-in-hand type self-current equalizing silicon carbide power module proposed in the present invention, the present invention also proposes a method for preparing the hand-in-hand type self-current equalizing silicon carbide power module. The method comprises: S1, applying a certain thickness of solder paste (Sn96.5-Ag3.0-Cu0.5) on a metal substrate through a steel mesh, and placing a plurality of silicon carbide chips and a plurality of driving resistors at designated positions through a chip mounter; S2, after completing the S1 operation, placing it in a graphite fixture for vacuum welding, maintaining the temperature at about 492K, and after completing the welding, using an ultrasonic cleaning device to remove the residual solder paste; S3, using a bonding interconnection device to selectively connect electrodes of a plurality of silicon carbide chips, a plurality of driving metal layers, and a plurality of conductive metal layers; S4, applying a certain thickness of solder paste (Sn96.5-Ag3.0-Cu0.5) on a metal substrate through a steel mesh, using a graphite fixture to fix the metal substrate, a plurality of DC power terminals, a plurality of AC power terminals, a plurality of driving terminals, and a plurality of driving resistors, and placing them in a vacuum welding furnace for vacuum welding at a welding temperature of 453K; S5, using an ultrasonic cleaning device again to remove the residual solder paste to complete the preparation.

[0053] In view of the problem that the current equalization effect applied to the existing silicon carbide power modules is difficult to ensure, the present invention proposes a hand-in-hand type self-current equalization silicon carbide power module. The module utilizes multiple DC power terminals, AC power terminals and silicon carbide chips to form multiple mutual inductance elimination circuits. On the one hand, the mutual inductance elimination circuit can utilize the DC terminals with opposite commutation directions inside the circuit to produce a mutual inductance cancellation effect and reduce the parasitic inductance in the mutual inductance elimination circuit. On the other hand, it can respond to the unbalanced current appearing in other circuits to generate an induced voltage to suppress the current imbalance phenomenon. In the power module of multiple parallel chips or other complex and changeable application conditions, it can have an excellent current equalization effect, avoid the problem of device loss and current stress difference, and has high reliability.

[0054] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A hand-in-hand type self-current equalizing silicon carbide power module, characterized in that: include: metal substrate; A conductive metal layer is disposed on the upper surface of the metal substrate, and a plurality of DC power terminals, a plurality of AC power terminals and a plurality of silicon carbide chips are disposed on the conductive metal layer; Among them, two DC power terminals with opposite current directions among the multiple DC power terminals, two AC power terminals among the multiple AC power terminals, and two silicon carbide chips among the multiple silicon carbide chips constitute a mutual inductance elimination loop; the mutual inductance elimination loop can utilize the mutual inductance cancellation effect between the two DC power terminals with opposite current directions to reduce the parasitic inductance in the mutual inductance elimination loop, and when the current in the mutual inductance elimination loop adjacent to the mutual inductance elimination loop changes, an induced voltage is generated to suppress the current imbalance caused by the mutual inductance elimination loop adjacent to the mutual inductance elimination loop.

2. The hand-in-hand self-current-balancing silicon carbide power module according to claim 1, characterized in that: The hand-in-hand type self-current equalizing silicon carbide power module further includes: a plurality of metal bonding wires; the conductive metal layer includes: a first conductive metal layer, on which a second conductive metal layer and a third conductive metal layer are arranged; the third conductive metal layer is mirror-arranged on both sides of the second conductive metal layer; The first conductive metal layer, the second conductive metal layer and the third conductive metal layer are electrically connected through the plurality of metal bonding wires; A portion of the plurality of DC power terminals is disposed on the second conductive metal layer, and another portion is disposed on the third conductive metal layer; and the plurality of AC power terminals is disposed on the first conductive metal layer; A portion of the plurality of silicon carbide chips is disposed on the first conductive metal layer, and another portion is disposed on the second conductive metal layer.

3. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 2, characterized in that: The plurality of DC power terminals include: a plurality of DC + DC power terminals and multiple DC - DC power terminal; the plurality of DC + The DC power terminals are arranged on the second conductive metal layer, and the plurality of DC - The DC power terminals are arranged on the third conductive metal layer, and the plurality of DC + DC power terminals and the plurality of DC - The DC power terminals are alternately arranged at equal intervals around the center of the second conductive metal layer, so that each DC power terminal is adjacent to two DC power terminals whose current directions are opposite to that of the DC power terminal.

4. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 3, characterized in that: In the mutual inductance elimination loop, the current flows from the DC + The DC power terminal flows into the silicon carbide chip arranged on the second conductive metal layer, the AC power terminal arranged on the first conductive metal layer, the silicon carbide chip arranged on the first conductive metal layer, and the DC power terminal arranged on the third conductive metal layer. - DC power flows out of the terminals.

5. The hand-in-hand self-current-balancing silicon carbide power module according to claim 3, characterized in that: The plurality of DC power terminals, the plurality of AC power terminals and the plurality of silicon carbide chips constitute four mutual inductance elimination loops, and the four mutual inductance elimination loops include: a first mutual inductance elimination loop, a second mutual inductance elimination loop, a third mutual inductance elimination loop and a fourth mutual inductance elimination loop; The first mutual inductance elimination circuit, the second mutual inductance elimination circuit, the third mutual inductance elimination circuit and the fourth mutual inductance elimination circuit are connected in parallel; and the first mutual inductance elimination circuit, the second mutual inductance elimination circuit, the third mutual inductance elimination circuit and the fourth mutual inductance elimination circuit are arranged symmetrically to each other; The DC in the first mutual inductance elimination loop + The DC power terminal is adjacent to the DC - DC power terminal, and the DC in the fourth mutual inductance elimination loop - DC power terminals; The DC in the second mutual inductance elimination loop + The DC power terminal is adjacent to the DC - DC power terminal, and the DC in the third mutual inductance elimination loop - DC power terminals; The DC in the third mutual inductance elimination loop + The DC power terminal is adjacent to the DC - DC power terminal, and the DC in the fourth mutual inductance elimination loop - DC power terminals; The DC in the fourth mutual inductance elimination loop + The DC power terminal is adjacent to the DC - DC power terminal, and the DC in the third mutual inductance elimination loop - DC power terminals.

6. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 2, characterized in that: The plurality of silicon carbide chips are used to control the current direction of the plurality of AC power terminals; the plurality of silicon carbide chips include: a first silicon carbide chip, a second silicon carbide chip, a third silicon carbide chip, a fourth silicon carbide chip, a fifth silicon carbide chip, a sixth silicon carbide chip, a seventh silicon carbide chip and an eighth silicon carbide chip; The first silicon carbide chip, the fourth silicon carbide chip, the fifth silicon carbide chip and the eighth silicon carbide chip are respectively welded on the four ends of the first conductive metal layer, and the second silicon carbide chip, the third silicon carbide chip, the sixth silicon carbide chip and the seventh silicon carbide chip are respectively welded on the four ends of the second conductive metal layer.

7. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 6, characterized in that: The plurality of AC power terminals include: a first AC power terminal, a second AC power terminal, a third AC power terminal, a fourth AC power terminal, a fifth AC power terminal, a sixth AC power terminal, a seventh AC power terminal and an eighth AC power terminal; The first AC power terminal, the second AC power terminal, the third AC power terminal and the fourth AC power terminal are evenly arranged between the first silicon carbide chip and the fifth silicon carbide chip; The fifth AC power terminal, the sixth AC power terminal, the seventh AC power terminal and the eighth AC power terminal are evenly arranged between the fourth silicon carbide chip and the eighth silicon carbide chip.

8. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 2, characterized in that: The hand-in-hand type self-current equalizing silicon carbide power module further includes: a plurality of drive circuits, the plurality of drive circuits are arranged on the metal substrate and symmetrically arranged on the outer side of the second conductive metal layer; The multiple driving circuits are electrically connected to the multiple silicon carbide chips located on the second conductive metal layer and the third conductive metal layer respectively through the multiple metal bonding wires; wherein one driving circuit corresponds to one metal bonding wire, and two metal bonding wires correspond to one silicon carbide chip; The multiple driving circuits are used to control the opening or closing of the multiple silicon carbide chips.

9. The hand-in-hand self-current-balancing silicon carbide power module according to claim 8, characterized in that: Each driving circuit includes: a first driving metal layer, a second driving metal layer, a third driving metal layer, a source driving terminal, a gate driving terminal, and a driving resistor; each driving metal layer is used to drive the source driving terminal, the gate driving terminal, and the driving resistor; The first driving metal layer, the second driving metal layer, and the third driving metal layer are arranged at intervals, the second driving metal layer and the third driving metal layer are electrically connected through the driving resistor, the source driving terminal is arranged on the first driving metal layer, and the gate driving terminal is arranged on the third driving metal layer; The first driving metal layer in a driving loop is electrically connected to a silicon carbide chip corresponding to the metal bonding wire through the metal bonding wire.

10. The hand-in-hand type self-current equalizing silicon carbide power module according to claim 1, characterized in that: The hand-in-hand type self-current equalizing silicon carbide power module further includes: a sub-board metal layer; the sub-board metal layer is arranged on the lower surface of the metal substrate.

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