Dynamic random access memory chip and working eye pattern jitter improvement method

Abstract

The invention discloses a dynamic random access memory chip and a working eye pattern jitter improvement method, the dynamic random access memory chip comprises a dynamic random access memory and a silicon capacitor which are sealed in a substrate, and the silicon capacitor is connected in parallel with a power supply pin end of the dynamic random access memory. The DRAM Die and the silicon capacitor are directly sealed in the packaging substrate, so that the equivalent inductance can be reduced to the minimum extent, the maximum capacitance performance benefit can be obtained, the stray noise of a power supply can be effectively filtered out under the high working frequency, and the DRAM high-frequency working signal quality can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to a dynamic random access memory chip and a method for improving working eye diagram jitter. Background Art

[0002] Due to process deviations in the DRAM manufacturing process, the working eye diagram waveform of the DRAM chip with large process deviations has many stray waveforms, resulting in many glitches in the eye diagram and unclear eye diagram, which leads to misreading when reading data. Summary of the invention

[0003] The present application provides a dynamic random access memory chip and a method for improving working eye diagram jitter to solve the problems existing in the related art.

[0004] In a first aspect, the present invention provides a dynamic random access memory chip, comprising a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory.

[0005] Optionally, during sealing, the silicon capacitor is arranged around the dynamic random access memory.

[0006] Optionally, during sealing, the silicon capacitor is arranged above the dynamic memory.

[0007] Optionally, during sealing, an RDL layer is laid above the dynamic memory, and the silicon capacitor is connected to a power pin end of the dynamic memory through the RDL layer.

[0008] Optionally, the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, including: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

[0009] Optionally, when multiple silicon capacitors are connected in parallel, the silicon capacitors are connected in parallel.

[0010] In a second aspect, the present invention provides a method for improving working eye diagram jitter, which is implemented based on the dynamic random access memory chip described in any one of the first aspects, wherein before the working eye diagram signal is output, the dynamic random access memory chip filters the power supply noise signal.

[0011] In a third aspect, the present invention provides a method for improving working eye diagram jitter, which is implemented based on the dynamic random access memory chip described in any implementation method of the first aspect, wherein before the working eye diagram signal is output, the dynamic random access memory chip filters the power supply noise signal.

[0012] In a fourth aspect, the present invention provides an electronic device terminal, comprising the dynamic random access memory chip described in any one of the first aspects.

[0013] The present invention discloses a dynamic random access memory chip and a method for improving working eye diagram jitter, wherein the dynamic random access memory chip comprises a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory. By sealing the DRAM Die and the silicon capacitor directly in the packaging substrate, the equivalent inductance can be reduced to a minimum, the maximum capacitance performance benefit can be obtained, and at high working frequencies, the power supply stray noise can be effectively filtered out, so that the quality of the DRAM high-frequency working signal is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 A schematic diagram of an application circuit structure of a dynamic random access memory chip of the present application;

[0016] Figure 2 A side view of a packaging structure of a dynamic random access memory chip of the present application;

[0017] Figure 3 A top view of a packaging structure of a dynamic random access memory chip of the present application;

[0018] Figure 4a A structural side view of a dynamic random access memory chip packaged for this application;

[0019] Figure 4b A top view of the structure of the dynamic random access memory chip packaged for this application;

[0020] Figure 4c A schematic diagram of a specific structure of a dynamic random access memory chip of the present application;

[0021] Figure 5 A side view of another packaging structure of a dynamic random access memory chip of the present application;

[0022] Figure 6 A top view of another packaging structure of a dynamic random access memory chip of the present application;

[0023] Figure 7a A side view of another packaging structure of the dynamic random access memory chip packaged for this application;

[0024] Figure 7b A top view of another packaging structure of the dynamic random access memory chip packaged for this application;

[0025] Figure 7c This is another specific structural schematic diagram of a dynamic random access memory chip of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0027] The following is combined with Figure 1 An exemplary description is given of a dynamic random access memory chip, which includes a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory.

[0028] In this embodiment, due to process deviations in the DRAM manufacturing process, the working eye diagram waveform of the DRAM chip with large process deviations has many stray waveforms, resulting in many burrs in the eye diagram, and the eye diagram is not clear, resulting in misreading when reading data. In order to solve this problem, the DRAM power supply itself can be made cleaner, reducing the impact of power load changes, thereby enhancing the signal quality of DRAM data.

[0029] This embodiment can minimize the equivalent inductance and obtain the maximum capacitor performance benefit by directly sealing the DRAM Die and the silicon capacitor in the packaging substrate. At high operating frequencies, it can effectively filter out power supply stray noise, thereby effectively improving the quality of DRAM high-frequency operating signals.

[0030] As an optional implementation of this embodiment, when the package is closed, the silicon capacitor is arranged around the dynamic random access memory.

[0031] In this optional implementation, if the package of the dynamic random access memory is a single-die particle chip, the silicon capacitors are distributed on both sides. Figure 2 The side view after sealing is shown. Figure 3 The top view after sealing is shown. Figure 2 and Figure 3 It can be known that the silicon capacitors are arranged around the dynamic random access memory, and after packaging, the power pins are connected in parallel with the silicon capacitors.

[0032] Schematic diagram reference after packaging is completed Figure 4a is a side view, Figure 4b This is a top view.

[0033] More specifically, refer to Figure 4c The package size of dynamic random access memory chips follows the JEDEC standard. If the package is a single-die particle chip with ample internal space, the silicon capacitors can be distributed on both sides of the die. C101~C104, C201~C204, C301~C304 are all silicon capacitors distributed between the pad (P101) of the carrier and the pad (P201) of the DRAM Die, as well as between the pad (P102) of the carrier and the pad (P202) of the DRAM Die. The relationship between the size of the capacitors is that C101 is greater than C102, C201 is greater than C202, and C301 is greater than C302; C104 is greater than C103, C204 is greater than C203, and C304 is greater than C303. In terms of placement position, C101, C201 and C301 are close to P101; C102, C202 and C302 are close to P201; C103, C203 and C303 are close to P202; C104, C204 and C304 are close to P102; C101 and C102 are in parallel, C201 and C202 are in parallel, C301 and C302 are in parallel; C103 and C104 are in parallel, C203 and C204 are in parallel, C303 and C304 are in parallel; all capacitors are connected in parallel between VDD and GND.

[0034] As an optional implementation of this embodiment, when the package is closed, the silicon capacitor is arranged above the dynamic memory.

[0035] In this optional implementation, reference Figure 5 The side view after sealing is shown. Figure 6 The top view after sealing is shown. Figure 5 and Figure 6 It can be known that the silicon capacitor is arranged on top of the dynamic random access memory, and this structure can shorten the pin distance.

[0036] Schematic diagram reference after packaging is completed Figure 7a is a side view, Figure 7b This is a top view.

[0037] More specifically, see Figure 7c The package size of dynamic random access memory chips follows the JEDEC standard. If the package is a multi-die chip with limited internal space, the silicon capacitor needs to be placed directly above the DRAM die. After the silicon capacitor is placed in this way, the distribution of the silicon capacitor is similar to that of the DRAM die. Figure 4cExcept for the different positional relationships, other relationships are the same. The positional relationships of the silicon capacitors need to be swapped, as described below: C101 and C102 are swapped, C201 and C202 are swapped, C301 and C302 are swapped; C104 and C103 are swapped, C204 and C203 are swapped, and C304 and C303 are swapped.

[0038] As an optional implementation of this embodiment, during sealing, an RDL layer is provided above the dynamic memory, and the silicon capacitor is connected to a power pin end of the dynamic memory through the RDL layer.

[0039] In this optional implementation, an RDL layer is provided above the dynamic memory, and then the power pin end and the silicon capacitor are connected based on the RDL layer.

[0040] As an optional implementation of this embodiment, the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, including: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

[0041] As an optional implementation of this embodiment, when multiple silicon capacitors are connected in parallel, the silicon capacitors are in a parallel relationship.

[0042] In this optional implementation, one or more silicon capacitors are connected in parallel to the DRAM Die power pins for packaging and sealing. The specific number of silicon capacitors can be added according to the actual circuit simulation results.

[0043] The packaged DRAM chip does not require PCB board-level capacitors for decoupling and filtering.

[0044] As an optional implementation of this embodiment, the dynamic random access memory chip is used to filter the power supply noise signal under the high frequency signal.

[0045] By connecting one or more silicon capacitors in parallel to the DRAM Die power pin for filtering, the DRAM chip's working eye diagram is smoother and the data reading is more accurate. Using DRAM Die and silicon capacitors to seal directly in the package substrate can minimize the equivalent inductance and obtain the maximum capacitor performance benefits. Even at high operating frequencies, the power supply stray noise can still be effectively filtered out, effectively improving the quality of DRAM high-frequency operating signals.

[0046] The above structure overcomes the defects of the related art in adding a ground capacitor to the power supply path for decoupling and filtering. Specifically, in the power supply circuit, it is generally required to place the decoupling capacitor and the filter capacitor as close to the working IC as possible, so as to minimize the equivalent inductance of the capacitor and achieve a relatively ideal filtering effect. However, no matter how close to the working IC, there is still a distance between the die of the working IC and the IC power pin, which is still interfered by noise under high-frequency signals, making the power supply signal noise very large.

[0047] The present application also provides a method for improving the jitter of a working eye diagram, which is implemented based on a dynamic random access memory chip, wherein the dynamic random access memory chip filters the power supply noise signal before the working eye diagram signal is output. The dynamic random access memory chip includes: a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory. When sealed, the silicon capacitor is arranged around the dynamic random access memory. When sealed, the silicon capacitor is arranged above the dynamic memory. When sealed, an RDL layer is laid above the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer. The silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, including: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors. When multiple silicon capacitors are connected in parallel, each silicon capacitor is in a parallel relationship.

[0048] The present application also provides an electronic device terminal, which can be a terminal device with different uses, and a dynamic random access memory chip is integrated in the device content, and the dynamic random access memory chip includes a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory. When sealed, the silicon capacitor is arranged around the dynamic random access memory. When sealed, the silicon capacitor is arranged above the dynamic memory. When sealed, an RDL layer is laid above the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer. The silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, including: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors. When multiple silicon capacitors are connected in parallel, each silicon capacitor is in a parallel relationship. The dynamic random access memory chip is used to filter the power supply noise signal under the high-frequency signal.

[0049] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A dynamic random access memory chip, It is characterized in that include: A dynamic random access memory and a silicon capacitor are sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory.

2. The dynamic random access memory chip according to claim 1, It is characterized in that When the package is closed, the silicon capacitor is arranged around the dynamic random access memory.

3. The dynamic random access memory chip according to claim 1, It is characterized in that When the package is closed, the silicon capacitor is arranged above the dynamic memory.

4. The dynamic random access memory chip according to claim 3, It is characterized in that During the sealing process, an RDL layer is laid on the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer.

5. The dynamic random access memory chip according to claim 1, It is characterized in that The silicon capacitor connected in parallel to the power pin end of the dynamic random access memory includes: Each power pin of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

6. The dynamic random access memory chip according to claim 5, It is characterized in that When multiple silicon capacitors are connected in parallel, the silicon capacitors are in a parallel relationship.

7. A method for improving the jitter of the working eye diagram, It is characterized in that The method is implemented based on the dynamic random access memory chip according to any one of claims 1 to 6, wherein the dynamic random access memory chip filters the power supply noise signal before outputting the working eye diagram signal.

8. An electronic equipment terminal, It is characterized in that A dynamic random access memory chip comprising any one of items 1-6.

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