Power semiconductor device and forming method thereof

Abstract

The invention discloses a power semiconductor device and a forming method thereof, and relates to the power semiconductor device, in order to consider two parameters of low resistance and high threshold voltage of a transistor at the same time, a barrier layer is divided into two parts, the aluminum content of a second barrier layer located below a P-type cover layer is small, and the aluminum content of a second barrier layer located below the P-type cover layer is small. The threshold voltage of the transistor can reach a high value, and the opportunity that the transistor is started by mistake is reduced. The aluminum content of the first barrier layers located on the left side and the right side below the P-type cover layer is large, the electron density of two-dimensional electron gas located in the area is improved, the resistance of the transistor is reduced, the resistance and the threshold voltage can be reduced at the same time, and the performance of the transistor is greatly improved.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, in particular to a method for manufacturing a power gallium nitride device. Background Art

[0002] Compared with silicon materials, gallium nitride materials have larger energy band gaps, higher electron mobility, saturated electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors are common power devices and are widely used in high-frequency applications such as radio frequency and microwave.

[0003] An existing GaN high electron mobility transistor structure is as follows Figure 1 As shown, the conventional barrier layer 103 forms a heterojunction with the channel layer located therebelow, and a conventional two-dimensional electron gas (2DEG) 110 is formed on the surface of the channel layer below the heterojunction. The material of the conventional barrier layer 103 is generally aluminum gallium nitride (AlGaN). X Ga 1-X N), X is the aluminum content of aluminum gallium nitride (0 ≤ X ≤ 1). The larger the value of X, the larger the aluminum content of the traditional barrier layer 103, the higher the electron density of the traditional two-dimensional electron gas 110, the lower the resistance of the transistor, and the lower the threshold voltage. Conversely, the smaller the value of X, the smaller the aluminum content of the traditional barrier layer 103, the lower the electron density of the traditional two-dimensional electron gas 110, the higher the resistance of the transistor, and the higher the threshold voltage. Therefore, Figure 1 Transistors are limited in reducing resistance and increasing threshold voltage at the same time, and can only be achieved by adjusting the AlGaN (Al X Ga 1-X N) with an aluminum content of X, or a trade-off between the two. Summary of the invention

[0004] In order to take into account both the low resistance and high threshold voltage parameters of the transistor, the present invention provides the following technical solution: a power semiconductor device, the device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, a source metal layer on one side of the gate metal layer and a drain metal layer on the other side, characterized in that the barrier layer comprises a first barrier layer and a second barrier layer, and the material of the first barrier layer is Al Y Ga 1-Y N, the material of the second barrier layer is Al Z Ga 1-ZN, wherein 0<Y≤1, 0≤Z<1, and Y>Z, the second barrier layer is located below the P-type cap layer; the first barrier layer and the second barrier layer respectively form heterojunctions with the channel layer located thereunder, and a first two-dimensional electron gas and a second two-dimensional electron gas are respectively formed on the surface of the channel layer located thereunder, and the length of the first two-dimensional electron gas is greater than the length of the second two-dimensional electron gas.

[0005] Furthermore, the width of the second barrier layer is equal to that of the P-type cap layer, and the first barrier layer is located on the left and right sides of the second barrier layer.

[0006] Furthermore, the width of the second barrier layer is greater than the width of the P-type cap layer, and the first barrier layer is located on the left and right sides of the second barrier layer.

[0007] Furthermore, the second barrier layer extends upward and toward both sides to cover at least a portion of the upper surface of the first barrier layer.

[0008] Furthermore, the second barrier layer extends upward and to both sides to cover the entire upper surface of the first barrier layer.

[0009] The present invention also provides a method for forming a power semiconductor device, the method comprising the following steps: The first step is to form a buffer layer on the substrate layer, then form a channel layer on the buffer layer, and then form a preliminary first barrier layer on the channel layer; In the first step, the material of the substrate layer is silicon, gallium nitride, silicon carbide or sapphire; the buffer layer contains one or more materials of aluminum gallium nitride, aluminum nitride, and gallium nitride, or the buffer layer contains carbon and iron doped elements; the material of the channel layer is gallium nitride; the material of the preliminary first barrier layer is aluminum gallium nitride.

[0010] The second step is to form a patterned first barrier layer on the preliminary first barrier layer; The third step is to form a preliminary second barrier layer; Step 4, etching is performed on the preliminary second barrier layer to form a patterned second barrier layer; In the fifth step, a preliminary P-type cap layer is formed on the surfaces of the first barrier layer and the second barrier layer; the material of the preliminary P-type cap layer is doped gallium nitride or aluminum gallium nitride.

[0011] Step 6: forming a preliminary gate metal layer on the surface of the preliminary P-type cap layer, wherein the preliminary gate metal layer forms a Schottky contact with the preliminary P-type cap layer therebelow; Step 7: etching the preliminary gate metal layer and the preliminary P-type cap layer to form a patterned gate metal layer and a patterned P-type cap layer respectively; In the eighth step, a source metal layer is formed on one side of the gate metal layer, and a drain metal layer is formed on the other side.

[0012] The present invention also provides another method for forming a power semiconductor device, the method comprising the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a preliminary protection layer is formed on the channel layer; The second step is to etch the preliminary protective layer to form a patterned protective layer; The third step is to form a first barrier layer on the surface of the channel layer; Step 4: removing the protective layer on the surface of the channel layer, and then forming a preliminary second barrier layer; Step 6, etching is performed on the preliminary second barrier layer to form a patterned second barrier layer; Step 7: forming a preliminary P-type cap layer on the surface of the first barrier layer and the second barrier layer; Step 8: forming a preliminary gate metal layer on the surface of the preliminary P-type cap layer, wherein the preliminary gate metal layer forms a Schottky contact with the preliminary P-type cap layer therebelow; Step 9, etching the preliminary gate metal layer and the preliminary P-type cap layer to form a patterned gate metal layer and a patterned P-type cap layer respectively; In the tenth step, a source metal layer is formed on one side of the gate metal layer, and a drain metal layer is formed on the other side.

[0013] The beneficial effect of the present invention is that the barrier layer is divided into two parts, and the aluminum content of the second barrier layer located below the P-type cap layer is relatively small, which ensures that the threshold voltage of the transistor can reach a higher value and reduces the chance of the transistor being turned on by mistake. The aluminum content of the first barrier layer located on the left and right sides below the P-type cap layer is relatively large, which increases the electron density of the two-dimensional electron gas located in this area and reduces the resistance of the transistor. The present invention can simultaneously reduce the resistance and increase the threshold voltage, greatly improving the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional schematic diagram of an existing high electron mobility transistor structure; Figure 2 A schematic cross-sectional view of a device structure according to an embodiment of the present invention; Figure 3 is a cross-sectional schematic diagram of a device structure of another embodiment of the present invention; Figure 4 is an embodiment of a method for manufacturing a device structure of the present invention; Figure 5-Figure 12 A schematic diagram of the steps of a method for forming a device structure of the present invention; Fig.13- Figure 17 is a schematic diagram of the steps of another method for forming a device structure of the present invention. DETAILED DESCRIPTION

[0015] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", and "horizontal" described in this document correspond to the relative positions of the reference diagrams, and are not limited to fixed directions in specific implementations. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0016] Example 1 Figure 2 Schematic cross-sectional view of a device structure according to a first embodiment of the present invention, the structure comprises: a substrate layer 200 at the bottom; a buffer layer 201 located above the substrate layer 200; A channel layer 202 located above the buffer layer 201; a barrier layer 203 located above the channel layer 202; P-type cap layer 204 located above the barrier layer 203; The gate metal layer 205 is located above the P-type cap layer 204; The source metal layer 206 is located on the left of the gate metal layer 205 and the drain metal layer 207 is located on the right.

[0017] In the above structure, the barrier layer 203 is composed of a first barrier layer 203a and a second barrier layer 203b. The second barrier layer 203b is located below the P-type cap layer 204, and the first barrier layer 203a is located on the left and right sides of the second barrier layer 203b.

[0018] In the above structure, the material of the first barrier layer 203a is usually aluminum gallium nitride (Al Y Ga 1-Y N), Y is the aluminum content of the first barrier layer 203a (0 < Y ≤ 1). The material of the second barrier layer 203b is usually aluminum gallium nitride (Al Z Ga 1-Z N), Z is the aluminum content of the second barrier layer 203b (0 ≤ Z < 1). The aluminum content of the first barrier layer 203a is greater than the aluminum content of the second barrier layer 203b (Y>Z).

[0019] In the above structure, the first barrier layer 203a forms a heterojunction with the channel layer 202 located thereunder, and forms a first two-dimensional electron gas 210a on the surface of the channel layer 202 located thereunder. The second barrier layer 203b forms a heterojunction with the channel layer 202 located thereunder, and forms a second two-dimensional electron gas 210b on the surface of the channel layer 202 located thereunder.

[0020] In the above structure, when the device is turned on, the first two-dimensional electron gas 210a and the second two-dimensional electron gas 210b form a current channel between the source metal layer 206 and the drain metal layer 207. Since the length of the first two-dimensional electron gas 210a is greater than that of the second two-dimensional electron gas 210b, the resistance ratio of the first two-dimensional electron gas 210a is also greater. By increasing the aluminum content Y of the first barrier layer 203a, the electron density of the first two-dimensional electron gas 210a will increase, and the resistance of the device will decrease.

[0021] In the above structure, when the device is turned off, the P-type cap layer 204 depletes the second two-dimensional electron gas 210b on the surface of the channel layer 202 below the second barrier layer 203b thereunder, forming an enhancement-mode device. By reducing the aluminum content Z of the second barrier layer 203b, the threshold voltage of the device can reach a higher value, reducing the chance of the device being turned on by mistake.

[0022] Example 2 A variation of the device embodiment of the present invention is as follows Figure 3 As shown, and Figure 2 The difference between the embodiments is that the thickness and width of the second barrier layer 203b are also relatively large. Figure 2 The second barrier layer 203b of the device has a large thickness and width, and covers the first barrier layer 203a.

[0023] In the above structure, the surface of the second barrier layer 203b has not been etched, the process is relatively simple, there are relatively small defects on the surface, the leakage current of the device is relatively low, and the reliability is relatively good.

[0024] Example 3 A variation of the device embodiment of the present invention is as follows Figure 4 As shown, and Figure 2 The difference between the embodiments is that the width of the second barrier layer 203b is slightly larger than the width of the P-type cap layer 204 located above it. Therefore, the length of the second two-dimensional electron gas 410b is larger than that of the P-type cap layer 204 located above it. Figure 2 In the embodiment, the length of the second two-dimensional electron gas 210 b is large.

[0025] In the above structure, since the width of the second barrier layer 203 b is greater than the width of the P-type cap layer 204 located thereon, the process window of the P-type cap layer 204 is expanded, and the consistency of the device threshold voltage is improved.

[0026] Example 4 According to the structural features of the above-mentioned embodiments of the present invention, combined with the existing GaN high electron mobility transistor manufacturing process, a variety of methods for forming the device embodiments of the present invention can be obtained. An exemplary method for forming the device embodiment of the present invention is as follows: Figure 5-Figure 12 Shown: In the first step, a buffer layer 201 is formed on the substrate layer 200, a channel layer 202 is formed on the buffer layer 201, and then a preliminary first barrier layer 293a is formed on the channel layer 202. Figure 5 shown.

[0027] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.

[0028] The buffer layer 201 may include one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which is beneficial to reduce leakage current.

[0029] The material of the channel layer 202 is usually gallium nitride (GaN), but may also be other materials, whose energy band gap is smaller than the energy band gap of the material of the preliminary first barrier layer 293 a located thereon.

[0030] The material of the preliminary first barrier layer 293a is generally aluminum gallium nitride (Al Y Ga 1-Y N), whose energy band gap is greater than the energy band gap of the material of the channel layer 202 located thereunder. Y is the aluminum content of the preliminary first barrier layer 293a (0 < Y ≤ 1).

[0031] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.

[0032] In the second step, photolithography, dry etching, wet etching and other process steps are performed on the preliminary first barrier layer 293a to form a patterned first barrier layer, such as Figure 6 shown.

[0033] The third step is to form a preliminary second barrier layer 293b, such as Figure 7 shown.

[0034] The material of the preliminary second barrier layer 293b is generally aluminum gallium nitride (Al Z Ga 1-ZN), whose energy band gap is greater than the energy band gap of the material of the channel layer 202 located thereunder. Z is the aluminum content of the preliminary second barrier layer 293b (0 ≤ Z < 1), which is smaller than the aluminum content of the first barrier layer (Y>Z).

[0035] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.

[0036] In the fourth step, photolithography, dry etching, wet etching and other process steps are performed on the preliminary second barrier layer 293b to form a patterned second barrier layer 203b, such as Figure 8 As shown; the patterned second barrier layer 203b can also be as Figure 3 The shape of the second barrier layer 203b is shown; In the fifth step, a preliminary P-type cap layer 294 is formed on the surface of the first barrier layer and the second barrier layer 203b, such as Fig. 9 shown.

[0037] The material of the preliminary P-type cap layer 294 is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials. The doped material contains magnesium (Mg) or other suitable P-type doping elements.

[0038] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.

[0039] Step 6: forming a preliminary gate metal layer 295 on the surface of the preliminary P-type cap layer 294, such as Fig.10 shown.

[0040] The preliminary gate metal layer 295 may be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.

[0041] Typically, the preliminary gate metal layer 295 forms a Schottky contact with the preliminary P-type cap layer 294 thereunder.

[0042] In the seventh step, the preliminary gate metal layer 295 and the preliminary P-type cap layer 294 are subjected to photolithography, dry etching, wet etching and other process steps to form a patterned gate metal layer 205 and a patterned P-type cap layer 204, respectively. Fig.11 shown.

[0043] In the eighth step, a source metal layer 206 is formed on the left side of the gate metal layer 205 and a drain metal layer 207 is formed on the right side thereof. Fig.12 shown.

[0044] The source metal layer 207 and the drain metal layer 208 may be formed by evaporation, sputtering and other processes, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.

[0045] The method of forming the patterned source metal layer 206 and the drain metal layer 207 may include photolithography, dry etching, wet etching and other process steps.

[0046] Typically, the source metal layer 206 and the drain metal layer 207 form ohmic contacts with the channel layer 202 thereunder.

[0047] Example 5 Another exemplary method of forming a device embodiment of the present invention is as follows Figure 13-Figure 17 Shown: In the first step, a buffer layer 201 is formed on the substrate layer 200, a channel layer 202 is formed on the buffer layer 201, and then a preliminary protection layer 590 is formed on the channel layer 202. Fig.13 The material of the preliminary protection layer 590 is generally silicon oxide such as silicon dioxide.

[0048] In the second step, photolithography, dry etching, wet etching and other process steps are performed on the preliminary protection layer 590 to form a patterned protection layer 500, such as Fig.14 shown.

[0049] In the third step, a first barrier layer 203a is formed on the surface of the channel layer 202, such as Fig.15 shown.

[0050] In the fourth step, the protection layer 500 on the surface of the channel layer 202 is removed by wet etching. Fig.16 shown.

[0051] Step 5: forming a preliminary second barrier layer 293b, such as Fig.17 The fifth step of Example 5 is the same as the third step of Example 4, and the subsequent steps are also the same.

[0052] The difference between the fifth embodiment and the fourth embodiment is that the process of the fifth embodiment is more complicated because the protective layer is used in the process. On the other hand, the fourth embodiment requires the preliminary dry etching of the first barrier layer 293a on the surface of the channel layer 202 ( Figure 6 ), Embodiment 5 does not require etching of any barrier layer on the surface of the channel layer 202. Therefore, the damage on the surface of the channel layer 202 in Embodiment 5 is less than that in Embodiment 4, and the performance and reliability of the device are better.

[0053] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

Claims

1. A power semiconductor device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, a source metal layer on one side of the gate metal layer and a drain metal layer on the other side, characterized in that: The barrier layer includes a first barrier layer and a second barrier layer, and the material of the first barrier layer is Al Y Ga 1- Y N, the material of the second barrier layer is Al Z Ga 1-Z N, wherein 0<Y≤1, 0≤Z<1, and Y>Z, the second barrier layer is located below the P-type cap layer; the first barrier layer and the second barrier layer respectively form heterojunctions with the channel layer located thereunder, and a first two-dimensional electron gas and a second two-dimensional electron gas are respectively formed on the surface of the channel layer located thereunder, and the length of the first two-dimensional electron gas is greater than the length of the second two-dimensional electron gas.

2. The power semiconductor device according to claim 1, characterized in that: The width of the second barrier layer is equal to that of the P-type cap layer, and the first barrier layer is located on the left and right sides of the second barrier layer.

3. The power semiconductor device according to claim 1, characterized in that: The width of the second barrier layer is greater than that of the P-type cap layer, and the first barrier layer is located on the left and right sides of the second barrier layer.

4. The power semiconductor device according to claim 1, characterized in that: The second barrier layer extends upward and toward both sides to cover at least a portion of the upper surface of the first barrier layer.

5. The power semiconductor device according to claim 4, characterized in that: The second barrier layer extends upward and to both sides to cover the entire upper surface of the first barrier layer.

6. The method for forming a power semiconductor device according to any one of claims 1 to 5, characterized in that: The forming method comprises the following steps: The first step is to form a buffer layer on the substrate layer, then form a channel layer on the buffer layer, and then form a preliminary first barrier layer on the channel layer; The second step is to form a patterned first barrier layer on the preliminary first barrier layer; The third step is to form a preliminary second barrier layer; Step 4, etching is performed on the preliminary second barrier layer to form a patterned second barrier layer; Step 5: forming a preliminary P-type cap layer on the surface of the first barrier layer and the second barrier layer; Step 6: forming a preliminary gate metal layer on the surface of the preliminary P-type cap layer, wherein the preliminary gate metal layer forms a Schottky contact with the preliminary P-type cap layer therebelow; Step 7: etching the preliminary gate metal layer and the preliminary P-type cap layer to form a patterned gate metal layer and a patterned P-type cap layer respectively; In the eighth step, a source metal layer is formed on one side of the gate metal layer, and a drain metal layer is formed on the other side.

7. The method for forming a power semiconductor device according to claim 6, wherein: In the first step, the material of the substrate layer is silicon, gallium nitride, silicon carbide or sapphire; The buffer layer contains one or more materials of aluminum gallium nitride, aluminum nitride, and gallium nitride, or the buffer layer contains carbon and iron doped elements; The material of the channel layer is gallium nitride; The material of the preliminary first barrier layer is aluminum gallium nitride.

8. The method for forming a power semiconductor device according to claim 6, wherein: In the fifth step, the material of the preliminary P-type cap layer is doped gallium nitride or aluminum gallium nitride.

9. The method for forming a power semiconductor device according to any one of claims 1 to 5, characterized in that: The forming method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a preliminary protection layer is formed on the channel layer; The second step is to etch the preliminary protective layer to form a patterned protective layer; The third step is to form a first barrier layer on the surface of the channel layer; Step 4: removing the protective layer on the surface of the channel layer, and then forming a preliminary second barrier layer; Step 6, etching is performed on the preliminary second barrier layer to form a patterned second barrier layer; Step 7: forming a preliminary P-type cap layer on the surface of the first barrier layer and the second barrier layer; Step 8: forming a preliminary gate metal layer on the surface of the preliminary P-type cap layer, wherein the preliminary gate metal layer forms a Schottky contact with the preliminary P-type cap layer therebelow; Step 9, etching the preliminary gate metal layer and the preliminary P-type cap layer to form a patterned gate metal layer and a patterned P-type cap layer respectively; In the tenth step, a source metal layer is formed on one side of the gate metal layer, and a drain metal layer is formed on the other side.

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