Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, in the semiconductor device, a first conductive type epitaxial layer comprises two source electrode trenches arranged at intervals, the bottom surfaces of the source electrode trenches are covered with third oxide layers, the side walls of the source electrode trenches are sequentially covered with first oxide layers, high-k insulating dielectric layers and second oxide layers from bottom to top, the surface of the oxide layer and the surface of the high-k insulating dielectric layer in the source trench are filled with a source polycrystalline silicon layer; and a gate oxide layer, a gate polycrystalline silicon layer, a second conductive type base region, a first conductive type source region and a second conductive type heavily doped region are arranged between the two source trenches. A new electric field peak value is introduced through the high-k insulating dielectric layer, so that the electric field distribution of the drift region is more uniform, the critical breakdown electric field of the device is improved, and the conduction loss is reduced; meanwhile, the length and position of the high-k insulating dielectric layer are set, and the electric field uniformity optimization effect of the drift region is improved; in addition, the silicon nitride layer in the hard mask layer is used as an etching barrier layer, so that the control precision of the depth of the source trench is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the field of medium and low voltage power devices, trench power MOSFET (Metal-Oxide-SemiconductorField-EffectTransistor) is widely used due to its advantages of low on-resistance, fast switching speed, high cell density, and low drive current, such as motor drive, power management, synchronous rectification, energy storage control, etc. However, since its breakdown voltage is positively correlated with on-resistance, reducing on-resistance generally leads to degradation of breakdown voltage, making it difficult to significantly reduce on-resistance.

[0003] Shielded-Gate Trench MOSFET (SGT MOSFET) based on charge coupling effect can make the compromise relationship between on-resistance and breakdown voltage better than the silicon limit theory of ordinary trench MOSFET. At the same time, due to the electric field shielding effect of the shielding gate, the electric field coupling between the gate and the drain is shielded, and the gate-drain capacitance is reduced, making SGT MOSFET gradually become a mainstream device in the medium and low voltage field.

[0004] However, the electric field distribution in the drift region of the traditional sidewall oxide layer structure SGT MOSFET is still not uniform enough, and its breakdown voltage improvement and on-resistance reduction are still greatly limited, making it difficult to meet the current semiconductor industry's requirements for high-voltage, low-loss device products.

[0005] Therefore, optimizing the electric field distribution in the drift region of the traditional sidewall oxide layer structure SGT MOSFET to increase the breakdown voltage of the trench power MOSFET and reduce the on-resistance and conduction loss has become one of the urgent problems to be solved.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0007] In view of the above shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of limited improvement of breakdown voltage and limited reduction of on-resistance of trench power MOSFET in the prior art.

[0008] To achieve the above object, the present invention provides a semiconductor device, the semiconductor device comprising: a first conductivity type substrate, a first conductivity type epitaxial layer, a source oxide layer, a source polysilicon layer, a high-k insulating dielectric layer, a gate polysilicon layer, a gate oxide layer, a second conductivity type base region, a first conductivity type source region, and a second conductivity type heavily doped region;

[0009] The first conductive type epitaxial layer is located on the first conductive type substrate; the first conductive type epitaxial layer includes two source trenches spaced apart, the source oxide layer includes a first oxide layer, a second oxide layer and a third oxide layer, the bottom surface of the source trench is covered with the third oxide layer, the sidewall of the source trench is sequentially covered with the first oxide layer, the high-k insulating dielectric layer and the second oxide layer from bottom to top, and the source polysilicon layer is filled in the surface of the source oxide layer and the high-k insulating dielectric layer in the source trench;

[0010] A gate trench is also provided between the two source trenches, and the bottom surface of the gate trench is higher than the bottom surface of the source trench; the bottom surface and sidewall of the gate trench are covered with the gate oxide layer, and the gate polysilicon layer is filled in the gate trench;

[0011] The second conductivity type base region, the first conductivity type source region and the second conductivity type heavily doped region are arranged between the gate trench and the source trench.

[0012] Optionally, the second conductivity type base region is located below the first conductivity type source region and the second conductivity type heavily doped region, the first conductivity type source region is located on a side close to the gate trench, and the second conductivity type heavily doped region is located on a side close to the source trench.

[0013] Optionally, the semiconductor device also includes a lead layer, which includes a source lead, a gate lead and a back gold lead, an effective electrical connection is formed between the source lead and the source polysilicon layer, an effective electrical connection is formed between the gate lead and the gate polysilicon layer, and an effective electrical connection is formed between the back gold lead and the first conductive type substrate.

[0014] Optionally, the material of the high-k insulating dielectric layer is one or any combination of more than one of Si3N4, HfO2 or ZrO2.

[0015] Optionally, the first conductivity type is P type, and the second conductivity type is N type; or the first conductivity type is N type, and the second conductivity type is P type.

[0016] Optionally, a direction from the first conductive type epitaxial layer to the first conductive type substrate is a first direction;

[0017] The length of the first oxide layer along the first direction is 1 / 8-2 / 5 of the length of the source trench along the first direction; and / or the length of the second oxide layer along the first direction is 1 / 8-2 / 5 of the length of the source trench along the first direction.

[0018] Optionally, a length of the first oxide layer along the first direction is greater than 1 micron, and / or a length of the second oxide layer along the first direction is greater than 1 micron.

[0019] The present invention also provides a method for preparing a semiconductor device, the method being used to prepare any one of the semiconductor devices described above, the method comprising:

[0020] Providing a first conductive type substrate, and disposing a first conductive type epitaxial layer on the first conductive type substrate;

[0021] Disposing two source trenches spaced apart from each other on the upper surface of the first conductive type epitaxial layer;

[0022] Covering the surface exposed by the source trench with a source oxide layer;

[0023] Filling a source polysilicon layer on the surface of the source oxide layer in the source trench;

[0024] The source oxide layer on the sidewall of the source trench is etched to a preset depth to obtain a first oxide layer, and a temporary trench is formed between the source trench and the source polysilicon layer; a third oxide layer is located at the bottom of the source trench;

[0025] The direction from the first conductive type epitaxial layer to the first conductive type substrate is a first direction, and a high-k insulating dielectric layer with a preset length along the first direction is arranged in the temporary trench;

[0026] A second oxide layer is provided on the high-k insulating dielectric layer until the second oxide layer is higher than the surface of the source polysilicon layer, and the first oxide layer, the second oxide layer and the third oxide layer are all the source oxide layer;

[0027] Disposing a gate trench between the two source trenches;

[0028] Disposing a gate oxide layer and a gate polysilicon layer in the gate trench;

[0029] A second conductive type base region, a first conductive type source region and a second conductive type heavily doped region are disposed in a region between the gate trench and the source trench.

[0030] Optionally, the method for forming the source trench includes: setting a hard mask layer on the first conductive type epitaxial layer; patterning and etching the hard mask layer to expose the surface of the first conductive type epitaxial layer at a position preset for setting the source trench; and etching the first conductive type epitaxial layer using the patterned hard mask layer as a mask to obtain the source trench.

[0031] Optionally, the hard mask layer includes an oxide layer, a silicon nitride layer and an oxide layer in sequence from top to bottom.

[0032] As described above, the semiconductor device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0033] The present invention introduces a new electric field peak by setting a high-k insulating dielectric layer, so that the electric field distribution in the drift region is more uniform, the critical breakdown electric field of the device is increased, and it is beneficial to further reduce the on-resistance and conduction loss;

[0034] The present invention improves the optimization effect of the high-k insulating dielectric layer on the uniformity of the electric field distribution in the drift region by setting the length and position of the high-k insulating dielectric layer;

[0035] The present invention uses the silicon nitride layer in the hard mask layer as an etching barrier layer, which can improve the control accuracy of etching the source trench depth and improve the electric field uniformity of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram showing the structure of the semiconductor device in the present invention.

[0037] Figure 2 It is a schematic structural diagram of a SGT MOSFET with a sidewall oxide layer structure in the prior art.

[0038] Figure 3 It shows a comparison diagram of the electric field intensity variation along the first direction in the drift region of the SGT MOSFET of the prior art with a sidewall oxide layer structure and the SGT MOSFET of the present invention.

[0039] Figure 4 It is a schematic structural diagram showing the step 1 of the method for preparing a semiconductor device in the present invention in which a first conductive type epitaxial layer is provided.

[0040] Figure 5 It is a schematic structural diagram of setting a hard mask layer in an example of step 2 of the method for preparing a semiconductor device in the present invention.

[0041] Figure 6 It is a schematic diagram of the structure presented by setting a source trench in an example of step 2 of the method for preparing a semiconductor device in the present invention.

[0042] Figure 7 It is a schematic structural diagram showing the step 3 of setting a source oxide layer in the method for preparing a semiconductor device in the present invention.

[0043] Figure 8 It is a schematic structural diagram showing the step 4 of the method for preparing a semiconductor device in the present invention in which a source polysilicon layer is provided.

[0044] Fig. 9 It is a schematic diagram showing the structure of the first oxide layer obtained in step 5 of the method for preparing a semiconductor device in the present invention.

[0045] Fig.10 It is a schematic structural diagram showing the step 6 of the method for preparing a semiconductor device in the present invention in which a high-k insulating dielectric layer is provided.

[0046] Fig.11 It is a schematic structural diagram showing the second oxide layer provided in step 7 of the method for preparing a semiconductor device in the present invention.

[0047] Fig.12 It is a schematic structural diagram showing the formation of gate trenches in step 8 of the method for manufacturing a semiconductor device in the present invention.

[0048] Fig.13 It is a schematic structural diagram showing the step 9 of the method for preparing a semiconductor device in the present invention in which a gate oxide layer and a gate polysilicon layer are provided.

[0049] Fig.14 It is a schematic structural diagram showing the arrangement of a second conductivity type base region, a first conductivity type source region and a second conductivity type heavily doped region in step 10 of the method for preparing a semiconductor device in the present invention.

[0050] Fig.15 It is a schematic structural diagram of setting a lead layer in an example of step 10 of the method for preparing a semiconductor device in the present invention.

[0051] Component number description

[0052] 10. First conductivity type substrate; 20. First conductivity type epitaxial layer; 31. Source trench; 32. First oxide layer; 33. Second oxide layer; 34. Third oxide layer; 35. High-k insulating dielectric layer; 36. Source polysilicon layer; 37. Temporary trench; 38. Source oxide layer; 41. Gate polysilicon layer; 42. Gate oxide layer; 43. Gate trench; 44. Protective oxide layer; 51. Second conductivity type base region; 52. Second conductivity type heavily doped region; 53. First conductivity type source region; 61. Source lead; 62. Gate lead; 63. Back gold lead; 70. Hard mask layer; 71. Oxide layer; 72. Silicon nitride layer; 81. Sidewall insulating layer. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0055] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0056] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0057] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0058] The present invention provides a semiconductor device, the semiconductor device comprising: a first conductive type substrate 10, a first conductive type epitaxial layer 20, a source oxide layer 38, a source polysilicon layer 36, a high-k insulating dielectric layer 35, a gate polysilicon layer 41, a gate oxide layer 42, a second conductive type base region 51, a first conductive type source region 53, and a second conductive type heavily doped region 52;

[0059] The first conductive type epitaxial layer 20 is located on the first conductive type substrate 10; the first conductive type epitaxial layer 20 includes two source trenches 31 spaced apart from each other, the source oxide layer 38 includes a first oxide layer 32, a second oxide layer 33 and a third oxide layer 34, the bottom surface of the source trench 31 is covered with the third oxide layer 34, the sidewalls of the source trench 31 are sequentially covered with the first oxide layer 32, the high-k insulating dielectric layer 35 and the second oxide layer 33 from bottom to top, and the source polysilicon layer 36 is filled in the surface of the source oxide layer 38 and the high-k insulating dielectric layer 35 in the source trench 31;

[0060] A gate trench 43 is further provided between the two source trenches 31 , and the bottom surface of the gate trench 43 is higher than the bottom surface of the source trench 31 ; the bottom surface and sidewall of the gate trench 43 are covered with the gate oxide layer 42 , and the gate polysilicon layer 41 is filled in the gate trench 43 ;

[0061] The second conductivity type base region 51 , the first conductivity type source region 53 , and the second conductivity type heavily doped region 52 are disposed between the gate trench 43 and the source trench 31 .

[0062] like Figure 2 The figure shows a schematic diagram of the structure of a conventional sidewall oxide layer structure SGT MOSFET (shielded-gate trench MOSFET) in the prior art, wherein a source trench 31 extends deep into the epitaxial layer, and a polysilicon connected to the source exists inside the source trench 31; the source polysilicon layer 36, the sidewall insulating layer 81 and the first conductive type epitaxial layer 20 (drift region) form a metal-oxide-semiconductor structure, so that the source polysilicon layer 36 can play a role similar to a body field plate, assisting in depleting the epitaxial drift region, and at the same time introducing a new electric field peak at the bottom of the trench, modulating the original triangular electric field distribution into a shape approximately rectangular, greatly improving the withstand voltage of the device, and therefore the on-resistance can be further reduced by increasing the doping concentration of the epitaxial layer; on the other hand, the grounded source polysilicon layer 36 reduces the electric field coupling between the gate and the drain through the electric field shielding effect, so that the gate-drain capacitance that affects the switching speed is partially converted into the gate-source capacitance and the drain-source capacitance, effectively reducing the switching loss. However, the electric field strength of the SGT MOSFET with the sidewall oxide layer structure is relatively low near the middle of the source trench 31 , resulting in uneven electric field distribution in the drift region, which limits the improvement of the breakdown voltage and the reduction of the on-resistance.

[0063] The present invention introduces a high-k insulating dielectric layer 35 in the middle of the source oxide layer 38 on the inner side wall of the source trench 31, and utilizes the modulation effect of the high-k insulating dielectric layer 35 on the electric field of the drift region. Figure 3FIG. 1 is a comparison diagram of the electric field intensity change in the drift region along the first direction between the sidewall oxide layer structure SGT MOSFET of the prior art and the semiconductor device (SGT MOSFET) of the present invention, wherein the horizontal axis is the vertical coordinate of the drift region (first conductive type epitaxial layer 20) along the first direction, and the vertical axis is the electric field intensity at the longitudinal coordinate position of the corresponding drift region, and the direction from the first conductive type epitaxial layer 20 to the first conductive type substrate 10 is the first direction, wherein the SGT MOSFET of the present invention makes the SGT In addition to the two electric field peaks O1 at the interface of the drift region between the second conductive type base region 51 and the first conductive type epitaxial layer 20 and the electric field peak O2 at the bottom of the source trench 31 in the prior art, a new electric field peak O3 is introduced in the middle of the drift region near the high-k insulating dielectric layer 35, so that the electric field distribution in the drift region is more uniform, thereby improving the critical breakdown electric field of the drift region of the device compared with the prior art. Under the condition of a given breakdown voltage, the doping concentration of the drift region can be further increased to reduce the on-resistance, reduce the conduction loss, and improve the electrical performance of the sidewall oxide layer structure SGT MOSFET.

[0064] Specifically, the two source trenches 31 mentioned in the present invention are only used to illustrate the structure of an SGT MOSFET unit device, and a plurality of appropriate number of source trenches 31 may be provided according to the number and specific structure of the devices, all within the protection scope of the present invention.

[0065] Specifically, the first oxide layer 32 and the third oxide layer 34 are integrated and are only used to distinguish different positions.

[0066] Specifically, the first conductivity type substrate 10 is heavily doped with the first conductivity type, and the first conductivity type epitaxial layer 20 is lightly doped with the first conductivity type.

[0067] In one embodiment, the first conductive type substrate 10 is a silicon substrate.

[0068] In one embodiment, Figure 1 As shown, the second conductive type base region 51 is located below the first conductive type source region 53 and the second conductive type heavily doped region 52, the first conductive type source region 53 is located on a side close to the gate trench 43, and the second conductive type heavily doped region 52 is located on a side close to the source trench 31.

[0069] In one embodiment, Figure 1As shown, the semiconductor device also includes a lead layer, which includes a source lead 61, a gate lead 62 and a back gold lead 63, an effective electrical connection is formed between the source lead 61 and the source polysilicon layer 36, an effective electrical connection is formed between the gate lead 62 and the gate polysilicon layer 41, and an effective electrical connection is formed between the back gold lead 63 and the first conductive type substrate 10.

[0070] In one embodiment, the semiconductor device further comprises a passivation protection layer, wherein the passivation protection layer covers a position on the surface of the semiconductor device where no electrical connection is performed.

[0071] In one embodiment, the material of the high-k insulating dielectric layer 35 is one or any combination of Si3N4, HfO2 or ZrO2. Specifically, the material of the high-k insulating dielectric layer 35 can also be other suitable high-k materials or any combination of one or more. Specifically, according to common knowledge in the art, "high-k" means that the relative dielectric constant is greater than 3.9.

[0072] In one embodiment, the first conductivity type is P type, and the second conductivity type is N type.

[0073] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0074] In one embodiment, the direction from the first conductive type epitaxial layer 20 to the first conductive type substrate 10 is a first direction;

[0075] The length of the first oxide layer 32 along the first direction is 1 / 8-2 / 5 of the length of the source trench 31 along the first direction; and / or the length of the second oxide layer 33 along the first direction is 1 / 8-2 / 5 of the length of the source trench 31 along the first direction.

[0076] The present invention sets the relative position of the high-k insulating dielectric layer 35 in the source trench 31 by setting the proportional relationship between the length of the first oxide layer 32 and the second oxide layer 33 along the first direction and the total length of the source trench 31, so that the high-k insulating dielectric layer 35 is located as close as possible to a position in the middle of the source trench 31 where the electric field strength is relatively low, thereby improving the optimization effect of the high-k insulating dielectric layer 35 on the uniformity of the electric field distribution in the drift region.

[0077] In one embodiment, the length of the first oxide layer 32 along the first direction is greater than 1 micron, and / or the length of the second oxide layer 33 along the first direction is greater than 1 micron.

[0078] The present invention sets the length of the first oxide layer 32 and the second oxide layer 33 along the first direction, thereby actually setting the length range of the high-k insulating dielectric layer 35 in the source trench 31, so that the high-k insulating dielectric layer 35 is located as close as possible to the position in the middle of the source trench 31 where the electric field strength is relatively low, thereby improving the optimization effect of the high-k insulating dielectric layer 35 on the uniformity of the electric field distribution in the drift region.

[0079] The present invention also provides a method for preparing a semiconductor device, the method being used to prepare any one of the semiconductor devices described above, the method comprising:

[0080] Step 1: providing a first conductive type substrate 10, and disposing a first conductive type epitaxial layer 20 on the first conductive type substrate 10;

[0081] Step 2: two source trenches 31 spaced apart from each other are provided on the upper surface of the first conductive type epitaxial layer 20;

[0082] Step 3: Covering the surface exposed by the source trench 31 with a source oxide layer 38 ;

[0083] Step 4: Filling a source polysilicon layer 36 on the surface of the source oxide layer 38 in the source trench 31;

[0084] Step 5: etching the source oxide layer 38 on the sidewall of the source trench 31 to a preset depth to obtain a first oxide layer 32, and forming a temporary trench 37 between the source trench 31 and the source polysilicon layer 36; the third oxide layer 34 is located at the bottom of the source trench 31;

[0085] Step 6: The direction from the first conductive type epitaxial layer 20 to the first conductive type substrate 10 is a first direction, and a high-k insulating dielectric layer 35 with a preset length along the first direction is provided in the temporary trench 37;

[0086] Step 7: Disposing a second oxide layer 33 on the high-k insulating dielectric layer 35 until the second oxide layer 33 is higher than the surface of the source polysilicon layer 36 , and the first oxide layer 32 , the second oxide layer 33 and the third oxide layer 34 are all the source oxide layer 38 ;

[0087] Step 8: Disposing a gate trench 43 between the two source trenches 31;

[0088] Step 9: Disposing a gate oxide layer 42 and a gate polysilicon layer 41 in the gate trench 43;

[0089] Step 10: Dispose a second conductivity type base region 51 , a first conductivity type source region 53 , and a second conductivity type heavily doped region 52 in the region between the gate trench 43 and the source trench 31 .

[0090] The method for preparing the semiconductor device of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor device protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0091] First, proceed to step 1, such as Figure 4 As shown, a first conductive type substrate 10 is provided, and a first conductive type epitaxial layer 20 is disposed on the first conductive type substrate 10 .

[0092] Then, step 2 is performed to form two source trenches 31 spaced apart from each other on the upper surface of the first conductive type epitaxial layer 20 .

[0093] In one embodiment, the method of forming the source trench 31 includes: Figure 5 As shown, a hard mask layer 70 is disposed on the first conductive type epitaxial layer 20; the hard mask layer 70 is patterned and etched to reveal the surface of the first conductive type epitaxial layer 20 where the source trench 31 is preset; as shown Figure 6 As shown, the first conductive type epitaxial layer 20 is etched using the patterned hard mask layer 70 as a mask to obtain the source trench 31 .

[0094] In one embodiment, Figure 5 As shown, the hard mask layer 70 includes an oxide layer 71 , a silicon nitride layer 72 and an oxide layer 71 in sequence from top to bottom.

[0095] The present invention sets the silicon nitride layer 72 contained in the hard mask layer 70 as an etching barrier layer, and can stop etching when the source trench 31 is etched to a certain depth, thereby improving the control accuracy of the depth of the etching source trench 31, so as to further improve the control accuracy of the high-k insulating dielectric layer 35 on the uniformity of the electric field in the drift region, so as to further improve the breakdown voltage of the device and reduce the on-resistance.

[0096] Next, proceed to step 3, such as Figure 7 As shown, the surface exposed by the source trench 31 is covered with a source oxide layer 38 .

[0097] In one embodiment, Figure 7As shown, after the hard mask layer 70 is set and the source trench 31 is etched, the residual hard mask layer 70 is not removed, and there will still be residual hard mask layer 70 on the upper surface of the first conductive type epitaxial layer 20. Therefore, when the source oxide layer 38 is set, the source oxide layer 38 will not only cover the exposed surface of the source trench 31, but also cover the residual hard mask layer 70.

[0098] In one embodiment, a source oxide layer 38 is formed on the inner surface of the source trench 31 by chemical vapor deposition process or other suitable methods.

[0099] Then, proceed to step 4, such as Figure 8 As shown, a source polysilicon layer 36 is filled on the surface of the source oxide layer 38 in the source trench 31 .

[0100] In one embodiment, Figure 8 As shown, since the source oxide layer 38 covers the hard mask layer 70 remaining on the upper surface of the first conductive type epitaxial layer 20, when the source polysilicon layer 36 directly and completely fills the source trench 31, the height of the source polysilicon layer 36 will be higher than the upper surface of the first conductive type epitaxial layer 20. Therefore, it is necessary to dry-etch the source polysilicon layer 36 to the target depth after depositing the source polysilicon layer 36 so that the source polysilicon layer 36 is flush with the upper surface of the first conductive type epitaxial layer 20.

[0101] Next, proceed to step 5, such as Fig. 9 As shown, the source oxide layer 38 on the sidewall of the source trench 31 is etched to a preset depth to obtain a first oxide layer 32, and a temporary trench 37 is formed between the source trench 31 and the source polysilicon layer 36; the third oxide layer 34 is located at the bottom of the source trench 31.

[0102] Specifically, the preset depth is a preset depth along a first direction, and the direction from the first conductive type epitaxial layer 20 to the first conductive type substrate 10 is the first direction.

[0103] In one embodiment, the source oxide layer 38 on the sidewall of the source trench 31 is etched to a preset depth by wet etching. Specifically, the preset depth is set according to the position in the drift region where the electric field strength needs to be enhanced to improve the uniformity of the electric field distribution.

[0104] Then, proceed to step 6, such as Fig.10 As shown, the direction from the first conductive type epitaxial layer 20 to the first conductive type substrate 10 is a first direction, and a high-k insulating dielectric layer 35 with a preset length along the first direction is arranged in the temporary trench 37 .

[0105] In one embodiment, the method of setting the high-k insulating dielectric layer 35 of a preset length includes: depositing the high-k insulating dielectric layer 35 to fill the temporary trench 37, and then etching back the high-k insulating dielectric layer 35 until the high-k insulating dielectric layer 35 has a preset length along the first direction.

[0106] Next, proceed to step 7, such as Fig.11 As shown, a second oxide layer 33 is disposed on the high-k insulating dielectric layer 35 until the second oxide layer 33 is higher than the surface of the source polysilicon layer 36 , and the first oxide layer 32 , the second oxide layer 33 and the third oxide layer 34 are all the source oxide layer 38 .

[0107] In one embodiment, Fig.11 As shown, the method for setting the second oxide layer 33 on the high-k insulating dielectric layer 35 includes: setting a filling oxide layer by a high-density plasma chemical vapor deposition method, the filling oxide layer covers the surface of the source polysilicon layer 36 and the hard mask layer 70 and fills the temporary groove 37; using chemical mechanical polishing to remove the oxide layer 71 and the filling oxide layer above the silicon nitride layer 72 in the hard mask layer 70, the silicon nitride layer 72 serves as an etching barrier layer for chemical mechanical polishing, and determines the final etching depth of the chemical mechanical polishing; then depositing an oxide layer to supplement the consumed oxide layer 71 of the top layer of the hard mask layer, and at the same time forming a second oxide layer 33 in the temporary groove 37 on the side wall of the source groove 31 near the source polysilicon.

[0108] Then, step 8 is performed to set a gate trench 43 between the two source trenches 31 .

[0109] In one embodiment, the method of providing the gate trench 43 between the two source trenches 31 includes: Fig.11 As shown, the surface of the region where the gate trench 43 is set is covered by a hard mask layer 70 to improve the etching accuracy of the gate trench 43, and the source trench is protected by a thick second oxide layer 33; Fig.12 As shown, the hard mask layer 70 is patterned to define a region where the gate trench 43 is to be set, and the gate trench 43 is formed by etching using the hard mask layer 70 as a mask.

[0110] Next, proceed to step 9, such as Fig.13 As shown, a gate oxide layer 42 and a gate polysilicon layer 41 are disposed in the gate trench 43 .

[0111] In one embodiment, the method for setting a gate oxide layer 42 and a gate polysilicon layer 41 in the gate trench 43 includes: thermally growing a thin sacrificial oxide layer on the surface exposed by the gate trench 43 and etching it back, and then using a thermal oxidation process to form a gate oxide layer 42; depositing a gate polysilicon layer 41 and etching it back to the surface or below the surface of the first conductive type epitaxial layer 20, removing the oxide layer 71 and the silicon nitride layer 72 on the surface of the first conductive type epitaxial layer 20; and then setting a protective oxide layer 44 on the flush surface.

[0112] Finally, proceed to step 10, such as Fig.14 As shown, a second conductivity type base region 51 , a first conductivity type source region 53 , and a second conductivity type heavily doped region 52 are disposed in the region between the gate trench 43 and the source trench 31 .

[0113] In one embodiment, the second conductivity type base region 51 , the first conductivity type source region 53 , and the second conductivity type heavily doped region 52 are formed respectively by ion implantation and high temperature annealing.

[0114] In one embodiment, Fig.15 As shown, after forming the second conductive type base region 51, the first conductive type source region 53 and the second conductive type heavily doped region 52, the protective oxide layer 44 on the surface is removed, and an interlayer dielectric layer, a contact hole and a lead layer are also formed; a passivation layer is deposited on the surface of the formed device, and the passivation layer is patterned and etched with a mask to form a metal lead area for electrical connection of the lead layer, and corresponding gate leads 62 and source leads 61 are set in the metal lead area, and the patterned passivation layer is used as an interlayer dielectric layer; finally, the substrate 10 of the first conductive type substrate 10 away from the first conductive type epitaxial layer 20 is thinned, and the back gold process is performed on the side of the thinned first conductive type substrate 10 away from the first conductive type epitaxial layer 20 to form a back gold lead 63.

[0115] In summary, the semiconductor device and preparation method thereof of the present invention can introduce a new electric field peak by introducing a high-k insulating dielectric layer, thereby making the electric field distribution in the drift region more uniform, improving the critical breakdown electric field of the device, and facilitating further reducing the on-resistance and conduction loss; at the same time, by setting the length and position of the high-k insulating dielectric layer, the optimization effect of the high-k insulating dielectric layer on the uniformity of the electric field distribution in the drift region is improved; in addition, by using the silicon nitride layer in the hard mask layer as an etching barrier layer, the control accuracy of etching the source trench depth can be improved, and the electric field uniformity in the drift region can be improved.

[0116] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a first conductive type substrate, a first conductive type epitaxial layer, a source oxide layer, a source polysilicon layer, a high-k insulating dielectric layer, a gate polysilicon layer, a gate oxide layer, a second conductive type base region, a first conductive type source region, and a second conductive type heavily doped region; The first conductive type epitaxial layer is located on the first conductive type substrate; the first conductive type epitaxial layer includes two source trenches spaced apart, the source oxide layer includes a first oxide layer, a second oxide layer and a third oxide layer, the bottom surface of the source trench is covered with the third oxide layer, the sidewall of the source trench is sequentially covered with the first oxide layer, the high-k insulating dielectric layer and the second oxide layer from bottom to top, and the source polysilicon layer is filled in the surface of the source oxide layer and the high-k insulating dielectric layer in the source trench; A gate trench is also provided between the two source trenches, and the bottom surface of the gate trench is higher than the bottom surface of the source trench; the bottom surface and sidewall of the gate trench are covered with the gate oxide layer, and the gate polysilicon layer is filled in the gate trench; The second conductivity type base region, the first conductivity type source region and the second conductivity type heavily doped region are arranged between the gate trench and the source trench.

2. The semiconductor device according to claim 1, wherein: The second conductivity type base region is located below the first conductivity type source region and the second conductivity type heavily doped region, the first conductivity type source region is located on a side close to the gate trench, and the second conductivity type heavily doped region is located on a side close to the source trench.

3. The semiconductor device according to claim 1, wherein: The semiconductor device also includes a lead layer, which includes a source lead, a gate lead and a back-gold lead. An effective electrical connection is formed between the source lead and the source polysilicon layer, an effective electrical connection is formed between the gate lead and the gate polysilicon layer, and an effective electrical connection is formed between the back-gold lead and the first conductive type substrate.

4. The semiconductor device according to claim 1, wherein: The material of the high-k insulating dielectric layer is one of Si3N4, HfO2 or ZrO2 or any combination of more than one of them.

5. The semiconductor device according to claim 1, wherein: The first conductivity type is P type, and the second conductivity type is N type; or the first conductivity type is N type, and the second conductivity type is P type.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: A direction from the first conductive type epitaxial layer to the first conductive type substrate is a first direction; The length of the first oxide layer along the first direction is 1 / 8-2 / 5 of the length of the source trench along the first direction; and / or the length of the second oxide layer along the first direction is 1 / 8-2 / 5 of the length of the source trench along the first direction.

7. The semiconductor device according to claim 6, characterized in that The length of the first oxide layer along the first direction is greater than 1 micron, and / or the length of the second oxide layer along the first direction is greater than 1 micron.

8. A method for preparing a semiconductor device, characterized in that: The preparation method is used to prepare the semiconductor device according to any one of claims 1 to 7, and the preparation method comprises: Providing a first conductive type substrate, and disposing a first conductive type epitaxial layer on the first conductive type substrate; Disposing two source trenches spaced apart from each other on the upper surface of the first conductive type epitaxial layer; Covering the surface exposed by the source trench with a source oxide layer; Filling a source polysilicon layer on the surface of the source oxide layer in the source trench; The source oxide layer on the side wall of the source trench is etched to a preset depth to obtain a first oxide layer, and a temporary trench is formed between the source trench and the source polysilicon layer; a third oxide layer is located at the bottom of the source trench; a direction from the first conductive type epitaxial layer to the first conductive type substrate is a first direction, and a high-k insulating dielectric layer is provided in the temporary trench with a preset length along the first direction; A second oxide layer is provided on the high-k insulating dielectric layer until the second oxide layer is higher than the surface of the source polysilicon layer, and the first oxide layer, the second oxide layer and the third oxide layer are all the source oxide layer; Disposing a gate trench between the two source trenches; Disposing a gate oxide layer and a gate polysilicon layer in the gate trench; A second conductive type base region, a first conductive type source region and a second conductive type heavily doped region are disposed in a region between the gate trench and the source trench.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The method for forming the source trench includes: setting a hard mask layer on the first conductive type epitaxial layer; patterning and etching the hard mask layer to expose the surface of the first conductive type epitaxial layer where the source trench is preset; and etching the first conductive type epitaxial layer using the patterned hard mask layer as a mask to obtain the source trench.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The hard mask layer includes an oxide layer, a silicon nitride layer and an oxide layer in sequence from top to bottom.

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