Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a drift region; the isolation structure is located in the drift region and comprises at least one first branch part and at least one second branch part, the size of the second branch part in the first direction is smaller than that of the first branch part in the first direction, the first branch part and the second branch part are alternately arranged in the second direction, and the first branch part and the second branch part are adjacent to each other; the second direction is parallel to the surface of the substrate, and the first direction is a direction from the substrate top surface to the substrate bottom surface. When the electrons flow out of the source electrode, a part of the electrons do not need to move downwards to the bottom of the first part along the side wall surface of the first part and then flow to the drain electrode, but move to the bottom of the second part along the side wall surface of the second part and then flow to the drain electrode. The flow path of the electrons flowing out along the second subsection is shorter than the flow path of the electrons flowing out along the first subsection, so that the characteristic on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] A lateral metal oxide semiconductor field effect transistor (MOSFET) is a metal oxide semiconductor field effect transistor in which the current flow direction is parallel to the cross-sectional direction of the wafer substrate. Conventional lateral metal oxide semiconductor field effect transistors (Lateral Double-Diffused MOSFET, LDMOS) use double diffusion technology. In order to further improve the breakdown voltage of lateral metal oxide semiconductor field effect transistor devices, it is necessary to overcome the surface charge effect of the device. In power lateral metal oxide semiconductor field effect transistor devices, the two most important performance parameters are breakdown voltage and characteristic on-resistance.

[0003] The deep trench isolation (DTI) structure effectively reduces the relative occupied area of ​​the device and increases the effective length of the drift region by replacing the lateral width with the longitudinal depth, thereby providing a higher breakdown voltage for the high-voltage device.

[0004] However, the increase in device breakdown voltage often increases the characteristic on-resistance of the device, and the isolation structure of current devices needs to be optimized. Summary of the invention

[0005] The problem solved by the present invention is how to etch a deep groove structure with a height difference to optimize the isolation structure and utilize an additional low-resistance current path so that the isolation structure has a smaller characteristic on-resistance while providing a higher breakdown voltage for the high-voltage device.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate comprises a drift region; an isolation structure located in the drift region, wherein the isolation structure comprises at least one first division and at least one second division, wherein a size of the second division along a first direction is smaller than a size of the first division along the first direction, the first division and the second division are alternately arranged along a second direction, the first division and the second division are adjacent to each other, the second direction is parallel to the surface of the substrate, and the first direction is a direction from the top surface of the substrate to the bottom surface of the substrate.

[0007] Optionally, the isolation structure further includes: a third section, the third section is adjacent to the first section and the second section, and a projection of the third section on the substrate surface is within a projection range of the second section on the substrate surface.

[0008] Optionally, a size of the third section in a third direction is smaller than a size of the first section in the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate.

[0009] Optionally, a sum of a size of the third section along the first direction and a size of the second section along the first direction is not greater than a size of the first section along the first direction.

[0010] Optionally, a ratio of a size of the first subsection along the first direction to a size of the first subsection in the third direction is in a range of 1.5 to 8.

[0011] Optionally, it further includes: a source and a drain, and along the third direction, the source and the drain are respectively located on both sides of the isolation structure.

[0012] Optionally, it further includes: a gate, which is located on a side of the source away from the isolation structure along the third direction.

[0013] Optionally, the base includes a substrate, an insulating layer located on a surface of the substrate, and a semiconductor layer located on a surface of the insulating layer, and the semiconductor layer includes the drift region.

[0014] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a drift region; etching the substrate of the drift region to form a first opening; after forming the first opening, forming a first mask layer on the substrate, the first mask layer exposing the substrate of the drift region; using the first mask layer as a mask, etching the substrate of the drift region to form an isolation trench; filling the isolation trench to form an isolation structure, the isolation structure comprising at least one first division and at least one second division, the size of the second division along the first direction is smaller than the size of the first division along the first direction, the first division and the second division are alternately arranged along the second direction, the first division and the second division are adjacent to each other, the second direction is parallel to the surface of the substrate, and the first direction is the direction from the top surface of the substrate to the bottom surface of the substrate.

[0015] Optionally, in the step of forming an isolation trench, the isolation trench includes a first region and a second region, the first region and the second region are alternately arranged along the second direction, the isolation trench of the first region corresponds to the first opening, and the isolation trench of the second region is connected to the isolation trench of the first region; in the step of filling the isolation trench to form an isolation structure, the isolation trench of the first region and the isolation trench of the second region are filled to form the first division and the second division, respectively.

[0016] Optionally, a depth of the first opening is greater than a difference between a dimension of the first section along the first direction and a dimension of the second section along the first direction.

[0017] Optionally, after forming the first opening and before forming the first mask layer, it also includes: forming a second opening in the drift region, the second opening is arranged along a second direction with the first opening, a size of the second opening in a third direction is not larger than a size of the first opening in the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate.

[0018] Optionally, the depth of the second opening is not greater than the depth of the first opening.

[0019] Optionally, the first mask layer is a hard mask.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the semiconductor structure of the technical solution of the present invention, the isolation structure includes at least one first subdivision and at least one second subdivision, the size of the second subdivision along the first direction is smaller than the size of the first subdivision along the first direction, and the first direction is the direction from the top surface of the substrate to the bottom surface of the substrate. When electrons flow out from the source, a part of the electrons do not need to move down along the side wall surface of the first subdivision to the bottom of the first subdivision and then flow to the drain, but move along the side wall surface of the second subdivision to the bottom of the second subdivision and then flow to the drain. The flow path of the electrons flowing out along the second subdivision is shorter than the flow path of the electrons flowing out along the first subdivision, so that the characteristic on-resistance of the device is reduced.

[0022] In an optional solution of the present invention, the isolation structure further includes: a third division, the third division is adjacent to the first division and the second division, and the projection of the third division on the substrate surface is located within the projection range of the second division on the substrate surface. The size of the third division in the third direction is smaller than the size of the first division in the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate. The sum of the size of the third division along the first direction and the size of the second division along the first direction is not greater than the size of the first division along the first direction. When electrons flow out from the source, a part of the electrons do not need to move down along the side wall surface of the first division to the bottom of the first division and then flow to the drain, but move down along the side wall surface of the second division to the bottom of the second division, and then move down along the side wall of the third division to the bottom of the third division and then flow to the drain. The flow path of the electrons flowing out along the second division and the third division is shorter than the flow path of the electrons flowing out along the first division, so that the characteristic on-resistance of the device is reduced.

[0023] In an optional solution of the present invention, the ratio of the size of the first subsection along the first direction to the size of the first subsection in the third direction is in the range of 1.5 to 8. The depth-to-width ratio of the isolation structure is large, which reduces the relative occupied area of ​​the semiconductor device and increases the effective length of the drift region, thereby improving the breakdown voltage of the semiconductor device.

[0024] In the method for forming a semiconductor structure of the technical solution of the present invention, after forming the first opening, the substrate of the drift region is etched to form an isolation trench. In the isolation trench, the depth of the area corresponding to the first opening is greater than the depth of the area not corresponding to the first opening, so that the size of the first division of the isolation structure formed by filling the isolation trench along the first direction is greater than the size of the second division along the first direction. When electrons flow out from the source, a part of the electrons do not need to move down along the side wall surface of the first division to the bottom of the first division and then flow to the drain, but move along the side wall surface of the second division to the bottom of the second division and then flow to the drain. The flow path of the electrons flowing out along the second division is shorter than the flow path of the electrons flowing out along the first division, so that the characteristic on-resistance of the device is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 is a schematic structural diagram of a semiconductor structure according to an embodiment;

[0026] Figures 4 to 15 is a schematic structural diagram of each step of a process for forming a semiconductor structure according to an embodiment of the present invention;

[0027] Figures 16 to 33 is a schematic structural diagram of each step of a process for forming a semiconductor structure according to another embodiment of the present invention;

[0028] Fig.34 is a three-dimensional diagram of a semiconductor structure according to an embodiment of the present invention;

[0029] Fig.35 is a three-dimensional diagram of a semiconductor structure according to another embodiment of the present invention;

[0030] Fig.36 is a three-dimensional diagram of a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, the characteristic on-resistance of the lateral metal oxide semiconductor field effect transistor with deep trench isolation structure in the prior art is relatively large. The reasons for the problem are analyzed in combination with a semiconductor structure:

[0032] Please refer to Figures 1 to 3 , Figure 2 and Figure 3 They are Figure 1In the cross-sectional view at the AA1 position and the BB1 ​​position, the semiconductor structure comprises:

[0033] A substrate 100, wherein the substrate 100 includes a drift region I;

[0034] The isolation structure 101 is located in the drift region I, and the isolation structure 101 has a first size h along a direction from the top surface of the substrate 100 to the bottom surface of the substrate 100 .

[0035] The semiconductor structure further includes: a source (not shown) and a drain (not shown). Along the first direction Y, the source and the drain are respectively located at two sides of the isolation structure 101 .

[0036] The ratio of the first dimension h of the isolation structure 101 along the top surface of the substrate 100 pointing to the bottom surface of the substrate 100 to the dimension of the isolation structure 101 along the first direction Y is greater than a first threshold value. The first threshold value is 5:1, and the first dimension h is greater than 1 μm.

[0037] By replacing the lateral width with the longitudinal depth, the isolation structure 101 with a high aspect ratio effectively reduces the relative occupied area of ​​the device and increases the effective length of the drift region, providing a higher breakdown voltage for the high-voltage device. However, the increase in the device breakdown voltage often increases the characteristic on-resistance of the device, resulting in an increase in the characteristic conductive resistance of the device.

[0038] To solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a drift region; etching the substrate of the drift region to form a first opening; after forming the first opening, forming a first mask layer on the substrate, wherein the first mask layer exposes the substrate of the drift region; using the first mask layer as a mask, etching the substrate of the drift region to form an isolation trench; filling the isolation trench to form an isolation structure, wherein the isolation structure comprises at least one first section and at least one second section, wherein the size of the second section along the first direction is smaller than the size of the first section along the first direction, the first section and the second section are alternately arranged along the second direction, the first section and the second section are adjacent to each other, the second direction is parallel to the surface of the substrate, and the first direction is the direction from the top surface of the substrate to the bottom surface of the substrate.

[0039] In the method for forming a semiconductor structure of the technical solution of the present invention, after forming the first opening, the substrate of the drift region is etched to form an isolation trench. In the isolation trench, the depth of the area corresponding to the first opening is greater than the depth of the area not corresponding to the first opening, so that the size of the first division of the isolation structure formed by filling the isolation trench along the first direction is greater than the size of the second division along the first direction. When electrons flow out from the source, a part of the electrons do not need to move down along the side wall surface of the first division to the bottom of the first division and then flow to the drain, but move along the side wall surface of the second division to the bottom of the second division and then flow to the drain. The flow path of the electrons flowing out along the second division is shorter than the flow path of the electrons flowing out along the first division, so that the characteristic on-resistance of the device is reduced.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 15 It is a structural schematic diagram of each step of a process for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 In the cross-sectional view at position CC1, a substrate 200 is provided, wherein the substrate 200 has a drift region I.

[0043] Specifically, in some embodiments of the present invention, the base 200 includes a substrate, an insulating layer located on a surface of the substrate, and a semiconductor layer located on a surface of the insulating layer, and the semiconductor layer includes the drift region I.

[0044] The material of the substrate includes silicon. The material of the insulating layer includes silicon oxide. The material of the semiconductor layer includes silicon.

[0045] The semiconductor layer of the drift region I provides a structural basis for the subsequent formation of an isolation structure 205 .

[0046] In other embodiments, the base includes a substrate and an epitaxial layer located on the substrate, the epitaxial layer includes the drift region, the substrate is made of silicon, and the epitaxial layer is made of silicon.

[0047] Please refer to Figures 6 to 9 , etching the substrate 200 of the drift region I to form a first opening 202.

[0048] The steps of forming the first opening 202 include: Figure 6 and Figure 7 As shown, Figure 7 yes Figure 6 In the cross-sectional view at position CC1, a second mask layer 201 is formed on the substrate 200; Figure 8 and Fig. 9 As shown, Fig. 9 yes Figure 8 In the cross-sectional view at position CC1, the substrate 200 of the drift region I is etched using the second mask layer 201 as a mask to form a first opening 202.

[0049] The first opening 202 defines the position of the first region II of the isolation trench 204 to be formed subsequently. The first opening 202 provides a structural basis for the first region II of the isolation trench 204 to be formed subsequently.

[0050] Specifically, in some embodiments of the present invention, the number of the first openings 202 is greater than one, and the first openings 202 are arranged along the second direction X. In other embodiments, the number of the first opening may be one.

[0051] The first opening 202 has a depth in the first direction Z and the first opening 202 is located before the isolation trench 204 (eg, Fig.13 As shown in FIG. 2 ) is formed, so that the isolation trench 204 (as shown in FIG. 2 ) formed on the basis of the first opening 202 is formed. Fig.13 ), the depth of the area corresponding to the first opening 202 is greater than the depth of the area not corresponding to the first opening 202, so that different areas of the isolation trench 204 have different depths. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0052] Specifically, in some embodiments of the present invention, the second mask layer 201 is a hard mask, which is suitable for etching a material with a relatively large thickness to form a first opening 202 with a relatively large depth.

[0053] In the step of forming the second mask layer 201 on the substrate 200, the second mask layer 201 exposes the substrate 200. The step of forming the second mask layer 201 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; after exposing and developing the photoresist layer, etching the initial hard mask to form the second mask layer 201.

[0054] After forming the first opening 202 , the method further includes: removing the second mask layer 201 .

[0055] Please refer to Fig.10 and Fig.11 , Fig.11 yes Fig.10In the cross-sectional view at position CC1, after forming the first opening 202, a first mask layer 203 is formed on the substrate 200, and the first mask layer 203 exposes the substrate 200 in the drift region I.

[0056] The first mask layer 203 is used to define the position of the isolation trench 204 .

[0057] After forming the first opening 202, in the step of forming a first mask layer 203 on the substrate 200, the step of forming the first mask layer 203 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; after exposing and developing the photoresist layer, etching the initial hard mask to form the first mask layer 203.

[0058] Specifically, in some embodiments of the present invention, the first mask layer 203 is made of the same material as the second mask layer 201. The first mask layer 203 is a hard mask. The hard mask is suitable for etching a material with a relatively large thickness to form an isolation trench 204 with a relatively large depth.

[0059] Please refer to Fig.12 and Fig.13 , Fig.13 yes Fig.12 In the cross-sectional view at position CC1, the first mask layer 203 is used as a mask to etch the substrate 200 of the drift region I to form an isolation trench 204.

[0060] First, the first opening 202 is formed in the drift region I, so that the drift region I has two regions with different depths: a region corresponding to the first opening 202 and a region not corresponding to the first opening 202. Then, the substrate 200 of the drift region I with the depth difference is etched to form an isolation groove 204, so that the isolation groove 204 has two regions with different depths: a region corresponding to the first opening 202 and a region corresponding to the non-first opening 202. In the isolation groove 204, the depth of the region corresponding to the first opening 202 is greater than the depth of the region not corresponding to the first opening 202.

[0061] In the step of forming the isolation trench 204, the isolation trench 204 includes a first region II and a second region III, the first region II and the second region III are alternately arranged along the second direction X, the isolation trench 204 of the first region II corresponds to the first opening 202, and the isolation trench 204 of the second region III is connected to the isolation trench 204 of the first region II.

[0062] The first area II and the second area III are alternately arranged along the second direction X, that is, along the second direction X, the first area II is adjacent to the second area III, and the second area III is adjacent to the first area II.

[0063] The isolation trench 204 provides a structural basis for the subsequent formation of an isolation structure 205 .

[0064] Specifically, in some embodiments of the present invention, the depth of the first opening 202 is greater than the difference between the depth H1 of the first region II and the depth H2 of the second region III of the isolation trench 204 .

[0065] Please refer to Fig.14 and Fig.15 , Fig.15 yes Fig.14 In the cross-sectional view at position CC1, the isolation trench 204 is filled to form an isolation structure 205, and the isolation structure 205 includes at least one first section A and at least one second section B, the dimension H2 of the second section B along the first direction Z is smaller than the dimension H1 of the first section A along the first direction Z, the first section A and the second section B are alternately arranged along the second direction X, the first section A and the second section B are adjacent to each other, the second direction X is parallel to the surface of the substrate 200, and the first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0066] The isolation structure 205 has a first sub-portion A and a second sub-portion B of different depths. When electrons flow out from the source, a portion of the electrons do not need to move downward along the sidewall surface of the first sub-portion A to the bottom of the first sub-portion A and then flow to the drain, but move along the sidewall surface of the second sub-portion B to the bottom of the second sub-portion B and then flow to the drain. The flow path of the electrons flowing out along the second sub-portion B is shorter than the flow path of the electrons flowing out along the first sub-portion A, so that the characteristic on-resistance of the device is reduced. In the step of filling the isolation trench 204 to form the isolation structure 205, the isolation trench 204 of the first region II and the isolation trench 204 of the second region III are filled to form the first sub-portion A and the second sub-portion B, respectively. The depth of the first opening 202 is greater than the difference between the dimension H1 of the first sub-portion A along the first direction Z and the dimension H2 of the second sub-portion B along the first direction Z.

[0067] The ratio of the size of the first sub-portion A along the first direction Z to the size of the first sub-portion A along the third direction Y is in a range of 1.5 to 8. The size of the first sub-portion A along the first direction Z is greater than 1 μm.

[0068] Specifically, in some embodiments of the present invention, the size range of the first subsection A along the first direction Z is: 10 μm to 25 μm; the size range of the first subsection A along the second direction X is: 1 μm to 5 μm; the size range of the first subsection A along the third direction Y is: 3 μm to 15 μm. The size range of the second subsection B along the first direction Z is: 3 μm to 15 μm; the size range of the second subsection B along the second direction X is: 1 μm to 3 μm; the size range of the second subsection B along the third direction Y is: 3 μm to 15 μm.

[0069] The isolation structure 205 is made of an insulating material, and the insulating material includes silicon oxide.

[0070] Figures 16 to 33 It is a structural schematic diagram of each step of a process for forming a semiconductor structure according to another embodiment of the present invention.

[0071] Please Figures 4 to 9 Based on reference Figures 16 to 33 After forming the first opening 202, it also includes: forming a second opening 302 in the drift region I, the second opening 302 and the first opening 202 are arranged along the second direction X, the size of the second opening 302 in the third direction Y is not greater than the size of the first opening 202 in the third direction Y, the third direction Y is perpendicular to the second direction X, and the third direction Y is parallel to the surface of the substrate 200.

[0072] The steps of forming the second opening 302 include:

[0073] like Figures 16 to 18 As shown, Fig.17 yes Fig.16 Cross-sectional view at CC1 position, Fig.18 yes Fig.16 A cross-sectional view at position DD1, where a third mask layer 301 is formed on the substrate 200;

[0074] like Figures 19 to 21 As shown, Fig. 20 yes Fig.19 Cross-sectional view at CC1 position, Fig.21 yes Fig.19 A cross-sectional view at position DD1, using the third mask layer 301 as a mask, etching the substrate 200 of the drift region I to form a second opening 302;

[0075] like Figure 22 to Figure 24 As shown, Fig.23 yes Fig. 22 Cross-sectional view at CC1 position, Fig.24 yes Fig. 22 In the cross-sectional view at position DD1, the third mask layer 301 is removed.

[0076] The second opening 302 provides a structural basis for forming a trench structure 304. The third mask layer 301 defines an isolation structure 305 (eg, Fig.33 The third section C of FIG. 200 is located parallel to the surface of the substrate 200.

[0077] The second opening 302 and the first opening 202 are arranged along the second direction X, and a region corresponding to the second opening 302 in the second direction X does not overlap with a region corresponding to the first opening 202 in the second direction X.

[0078] The depth of the second opening 302 is not greater than the depth of the first opening 202. That is, the size of the second opening 302 in the first direction Z is smaller than the size of the first opening 202 in the first direction Z. Specifically, in some embodiments of the present invention, the depth of the second opening 302 is smaller than the depth of the first opening 202. In other embodiments, the depth of the second opening may also be equal to the depth of the first opening.

[0079] Please refer to Figure 25 to Figure 27 , Fig.26 yes Fig.25 Cross-sectional view at CC1 position, Fig. 27 yes Fig.25 In the cross-sectional view at position DD1, after the second opening 302 is formed, a first mask layer 303 is formed on the substrate 200, and the first mask layer 303 exposes the drift region I of the substrate 200.

[0080] The first mask layer 303 is used to define the isolation trench 304 (eg Fig.29 shown).

[0081] After forming the second opening 302, in the step of forming a first mask layer 303 on the substrate 200, the step of forming the first mask layer 203 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; after exposing and developing the photoresist layer, etching the initial hard mask to form the first mask layer 303.

[0082] Specifically, in some embodiments of the present invention, the first mask layer 303 is made of the same material as the second mask layer 201. The first mask layer 303 is a hard mask. The hard mask is suitable for etching a material with a relatively large thickness to form an isolation trench 304 with a relatively large depth.

[0083] Please refer to Figures 28 to 30 , Fig.29 yes Fig.28 Cross-sectional view at CC1 position, Fig.30 yes Fig.28 In the cross-sectional view at position DD1, the substrate 200 of the drift region I is etched using the first mask layer 303 as a mask to form an isolation trench 304.

[0084] First, the first opening 202 and the second opening 302 are formed in the drift region I, so that the drift region I has three regions with different depths: a region corresponding to the first opening 202, a region corresponding to the second opening 302, and a region corresponding to non-first opening 202 and non-second opening 302. Then, the substrate 200 of the drift region I with the depth difference is etched to form an isolation groove 304, so that the isolation groove 304 has three regions with different depths: a region corresponding to the first opening 202, a region corresponding to the second opening 302, and a region corresponding to non-first opening 202 and non-second opening 302. In the isolation groove 304, the depth of the region corresponding to the first opening 202 is greater than the depth of the region corresponding to the second opening 302, and the depth of the region corresponding to the second opening 302 is greater than the depth of the region not corresponding to the first opening 202 and not corresponding to the second opening 302.

[0085] In the isolation trench 304 , the area corresponding to the second opening 302 is located in the second region III of the substrate 200 .

[0086] In the step of forming the isolation trench 304, the isolation trench 304 includes a first region II and a second region III, the first region II and the second region III are alternately arranged along the second direction X, the isolation trench 304 of the first region II corresponds to the first opening 202, and the isolation trench 304 of the second region III is connected to the isolation trench 304 of the first region II.

[0087] The first area II and the second area III are alternately arranged along the second direction X, that is, along the second direction X, the first area II is adjacent to the second area III, and the second area III is adjacent to the first area II.

[0088] The isolation trench 304 provides a structural basis for the subsequent formation of an isolation structure 305 .

[0089] Please refer to Figure 31 to Figure 33 , Fig.32 yes Fig.31 Cross-sectional view at CC1 position, Fig.33 yes Fig.31In the cross-sectional view at position DD1, the isolation trench 204 is filled to form an isolation structure 305, and the isolation structure 305 includes at least one first division A and at least one second division B, the dimension H2 of the second division B along the first direction Z is smaller than the dimension H1 of the first division A along the first direction Z, the first division A and the second division B are alternately arranged along the second direction X, the first division A and the second division B are adjacent to each other, the second direction X is parallel to the surface of the substrate 200, and the first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0090] The isolation structure 305 further includes: a third sub-section C, the third sub-section C is adjacent to the first sub-section A and the second sub-section B, and the projection of the third sub-section C on the surface of the substrate 200 is within the projection range of the second sub-section B on the surface of the substrate 200. The third sub-section C (such as Fig.33 The projection of the second opening 302 (as shown) on the surface of the substrate 200 corresponds to Fig. 27 ) is projected onto the surface of the substrate 200.

[0091] The size of the third division C in the third direction Y is smaller than the size of the second division B in the third direction Y, and the size of the second division B in the third direction Y is the same as the size of the first division A in the third direction Y. Therefore, the size of the third division C in the third direction Y is smaller than the size of the first division A in the third direction Y. The third direction Y is perpendicular to the second direction X, and the third direction Y is parallel to the surface of the substrate 200.

[0092] The sum of the size of the third subsection C along the first direction Z and the size of the second subsection B along the first direction Z is not greater than the size of the first subsection A along the first direction Z. When electrons flow out from the source, a portion of the electrons do not need to move downward along the sidewall surface of the first subsection A to the bottom of the first subsection A and then flow to the drain, but move downward along the sidewall surface of the second subsection B to the bottom of the second subsection B, and then move downward along the sidewall of the third subsection C to the bottom of the third subsection C and then flow to the drain. The flow path of the electrons flowing out along the second subsection B and the third subsection C is shorter than the flow path of the electrons flowing out along the first subsection A, so that the characteristic on-resistance of the device is reduced.

[0093] The ratio of the size of the first subsection A along the first direction Z to the size of the first subsection A along the third direction Y is in the range of 1.5 to 8. The size of the first subsection A along the first direction Z is greater than 1 μm. Specifically, in some embodiments of the present invention, the size of the first subsection A along the first direction Z ranges from 10 μm to 25 μm; the size of the first subsection A along the second direction X ranges from 1 μm to 5 μm; the size of the first subsection A along the third direction Y ranges from 3 μm to 15 μm. The size of the second subsection B along the first direction Z ranges from 3 μm to 15 μm; the size of the second subsection B along the second direction X ranges from 1 μm to 3 μm; the size of the second subsection B along the third direction Y ranges from 3 μm to 15 μm. The size range of the third section C along the first direction Z is: 1 μm to 3 μm; the size range of the third section C along the second direction X is: 5 μm to 10 μm.

[0094] The isolation structure 305 is made of an insulating material, and the insulating material includes silicon oxide.

[0095] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Fig.14 and Fig.15 , and combined with reference Fig.34 , Fig.15 yes Fig.14 Cross-sectional view at CC1 position, Fig.34 It is a stereoscopic diagram of an embodiment of the present invention, comprising: a substrate 200, wherein the substrate 200 comprises a drift region I; an isolation structure 205 located in the drift region I, wherein the isolation structure 205 comprises at least one first subdivision A and at least one second subdivision B, wherein a dimension H2 of the second subdivision B along a first direction Z is smaller than a dimension H1 of the first subdivision A along the first direction Z, wherein the first subdivision A and the second subdivision B are alternately arranged along a second direction X, wherein the first subdivision A and the second subdivision B are adjacent to each other, wherein the second direction X is parallel to the surface of the substrate 200, and wherein the first direction Z is a direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0096] In the semiconductor structure of the technical solution of the present invention, the isolation structure includes at least one first sub-section A and at least one second sub-section B, the size of the second sub-section B along the first direction Z is smaller than the size of the first sub-section A along the first direction Z, and the first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200. When electrons flow out from the source, a part of the electrons do not need to move down along the side wall surface of the first sub-section A to the bottom of the first sub-section A and then flow to the drain, but move along the side wall surface of the second sub-section B to the bottom of the second sub-section B and then flow to the drain. The flow path of the electrons flowing out along the second sub-section B is shorter than the flow path of the electrons flowing out along the first sub-section A, so that the characteristic on-resistance of the device is reduced.

[0097] The semiconductor structure includes a substrate 200 , wherein the substrate 200 includes a drift region I.

[0098] The base 200 includes a substrate, an insulating layer located on a surface of the substrate, and a semiconductor layer located on a surface of the insulating layer, wherein the semiconductor layer includes the drift region I.

[0099] The semiconductor structure includes: an isolation structure 205 located in the drift region I, the isolation structure 205 includes at least one first subdivision A and at least one second subdivision B, the dimension H1 of the second subdivision B along the first direction Z is smaller than the dimension H2 of the first subdivision A along the first direction Z, the first subdivision A and the second subdivision B are alternately arranged along the second direction X, the first subdivision A and the second subdivision B are adjacent to each other, the second direction X is parallel to the surface of the substrate 200, and the first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0100] The ratio of the size of the first subsection A along the first direction Z to the size of the first subsection A along the third direction Y is in the range of 1.5 to 8. The third direction Y is perpendicular to the second direction X, and the third direction Y is parallel to the surface of the substrate 200. The size of the first subsection A along the first direction Z is in the range of 15 μm to 25 μm; the size of the first subsection A along the second direction X is in the range of 1 μm to 5 μm; the size of the first subsection A along the third direction Y is in the range of 8 μm to 15 μm. The size of the second subsection B along the first direction Z is in the range of 3 μm to 8 μm; the size of the second subsection B along the second direction X is in the range of 1 μm to 3 μm; the size of the second subsection B along the third direction Y is in the range of 8 μm to 15 μm.

[0101] The semiconductor structure further includes: a source 206 and a drain 207 . Along the third direction Y, the source 206 and the drain 207 are respectively located at two sides of the isolation structure 205 .

[0102] The semiconductor structure further includes a gate 208 . Along the third direction Y, the gate 208 is located at a side of the source 206 away from the isolation structure 205 .

[0103] Accordingly, the embodiment of the present invention also provides another semiconductor structure, please continue to refer to Figure 31 to Figure 33 , and combined with reference Fig.35 , Fig.32 yes Fig.31 Cross-sectional view at CC1 position, Fig.33 yes Fig.31 Cross-sectional view at DD1 position, Fig.35 It is a stereogram of an embodiment of the present invention.

[0104] The same points as the above-mentioned embodiments are not described in detail in the present disclosure. The difference from the above-mentioned embodiments is that the isolation structure 305 further includes: a third subdivision C, the third subdivision C is adjacent to the first subdivision A and the second subdivision B, and the projection of the third subdivision C on the surface of the substrate 200 is within the projection range of the second subdivision B on the surface of the substrate 200.

[0105] A size of the third section C in the third direction Y is smaller than a size of the first section A in the third direction Y. The third direction Y is perpendicular to the second direction X, and the third direction Y is parallel to the surface of the substrate 200 .

[0106] The sum of the size of the third subsection C along the first direction Z and the size of the second subsection B along the first direction Z is not greater than the size of the first subsection A along the first direction Z. Specifically, in some embodiments of the present invention, the sum of the size of the third subsection C along the first direction Z and the size of the second subsection B along the first direction Z is less than the size of the first subsection A along the first direction Z.

[0107] The size range of the first subsection A along the first direction Z is: 15μm to 25μm; the size range of the first subsection A along the second direction X is: 1μm to 5μm; the size range of the first subsection A along the third direction Y is: 8μm to 15μm. The size range of the second subsection B along the first direction Z is: 3μm to 8μm; the size range of the second subsection B along the second direction X is: 1μm to 3μm; the size range of the second subsection B along the third direction Y is: 8μm to 15μm. The size range of the third subsection C along the first direction Z is: 4μm to 7μm; the size range of the third subsection C along the second direction X is: 1μm to 3μm; the size range of the third subsection C along the third direction Y is: 3μm to 8μm.

[0108] Accordingly, the embodiment of the present invention also provides another semiconductor structure, please continue to refer to Figure 31 to Figure 33 , and combined with reference Fig.36 , Fig.32 yes Fig.31 Cross-sectional view at CC1 position, Fig.33 yes Fig.31 Cross-sectional view at DD1 position, Fig.36 It is a stereogram of an embodiment of the present invention.

[0109] The difference from the above embodiment is that the sum of the size of the third section C along the first direction Z and the size of the second section B along the first direction Z is equal to the size of the first section A along the first direction Z.

[0110] The size range of the first subsection A along the first direction Z is: 15μm to 25μm; the size range of the first subsection A along the second direction X is: 1μm to 5μm; the size range of the first subsection A along the third direction Y is: 8μm to 15μm. The size range of the second subsection B along the first direction Z is: 3μm to 9μm; the size range of the second subsection B along the second direction X is: 1μm to 3μm; the size range of the second subsection B along the third direction Y is: 8μm to 15μm. The size range of the third subsection C along the first direction Z is: 7μm to 16μm; the size range of the third subsection C along the second direction X is: 1μm to 3μm; the size range of the third subsection C along the third direction Y is: 3μm to 8μm.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: a substrate comprising a drift region; An isolation structure located in the drift region, the isolation structure includes at least one first section and at least one second section, the size of the second section along the first direction is smaller than the size of the first section along the first direction, the first section and the second section are alternately arranged along the second direction, the first section and the second section are adjacent to each other, the second direction is parallel to the surface of the substrate, and the first direction is the direction from the top surface of the substrate to the bottom surface of the substrate.

2. The semiconductor structure according to claim 1, It is characterized in that The isolation structure further includes a third section, the third section is adjacent to the first section and the second section, and a projection of the third section on the substrate surface is within a projection range of the second section on the substrate surface.

3. The semiconductor structure according to claim 2, It is characterized in that A dimension of the third section in a third direction is smaller than a dimension of the first section in the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to a surface of the substrate.

4. The semiconductor structure according to claim 2, It is characterized in that A sum of a size of the third section along the first direction and a size of the second section along the first direction is not greater than a size of the first section along the first direction.

5. The semiconductor structure according to claim 3, It is characterized in that The ratio of the size of the first subsection along the first direction to the size of the first subsection in the third direction is in the range of 1.5-8.

6. The semiconductor structure according to claim 3, It is characterized in that Also includes: A source and a drain, along the third direction, the source and the drain are respectively located on two sides of the isolation structure.

7. The semiconductor structure according to claim 6, It is characterized in that Also includes: A gate is located at a side of the source away from the isolation structure along the third direction.

8. The semiconductor structure according to claim 1, It is characterized in that The base includes a substrate, an insulating layer located on a surface of the substrate, and a semiconductor layer located on a surface of the insulating layer, wherein the semiconductor layer includes the drift region.

9. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate having a drift region; Etching a substrate of the drift region to form a first opening; After forming the first opening, forming a first mask layer on the substrate, wherein the first mask layer exposes the substrate of the drift region; Using the first mask layer as a mask, etching the substrate of the drift region to form an isolation trench; The isolation groove is filled to form an isolation structure, wherein the isolation structure includes at least one first section and at least one second section, wherein the size of the second section along the first direction is smaller than the size of the first section along the first direction, the first section and the second section are alternately arranged along the second direction, the first section and the second section are adjacent to each other, the second direction is parallel to the surface of the substrate, and the first direction is the direction from the top surface of the substrate to the bottom surface of the substrate.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that In the step of forming an isolation trench, the isolation trench includes a first region and a second region, the first region and the second region are alternately arranged along the second direction, the isolation trench of the first region corresponds to the first opening, and the isolation trench of the second region is connected to the isolation trench of the first region; In the step of filling the isolation trenches to form an isolation structure, the isolation trenches in the first region and the isolation trenches in the second region are filled to form the first sub-portion and the second sub-portion, respectively.

11. The method for forming a semiconductor structure according to claim 9, It is characterized in that A depth of the first opening is greater than a difference between a dimension of the first section along the first direction and a dimension of the second section along the first direction.

12. The method for forming a semiconductor structure according to claim 9, It is characterized in that After forming the first opening and before forming the first mask layer, it also includes: forming a second opening in the drift region, the second opening is arranged along a second direction with the first opening, the size of the second opening in the third direction is not greater than the size of the first opening in the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that A depth of the second opening is no greater than a depth of the first opening.

14. The method for forming a semiconductor structure according to claim 9, It is characterized in that The first mask layer is a hard mask.

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