A silicon carbide mosfet with improved reverse recovery capability and a method for manufacturing the same

Abstract

The application discloses a SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability and a preparation method thereof. The device comprises, from bottom to top, a silicon carbide substrate, an N-type drift layer and an N-type carrier storage layer. + region and a P + region, which are alternately distributed on the upper portion of the N-type carrier storage layer; a deep trench, which penetrates the N + region and the P + region and is located at the bottom of the N-type carrier storage layer; a P-type buried layer, which is formed in the N-type carrier storage layer at the bottom of the deep trench; a source, which fills the deep trench on both sides of the central N + region and realizes Schottky contact potential barrier with the N-type carrier storage layer on the sidewall; a gate oxide layer, which covers the sidewall and the bottom of the outermost deep trench; a gate, which covers the gate oxide layer and fills the outermost deep trench; a P-type base region, which is formed in the N + region and the P + region below the N-type carrier storage layer; a passivation layer, which covers the surface of the gate; and a source ohmic contact, which covers the surface of the device.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit device structure design, specifically relating to an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability and its fabrication method. Background Technology

[0002] SiC MOSFET devices are an excellent candidate for next-generation power semiconductor device architectures in many power conversion systems. Silicon carbide (SiC) is a compound semiconductor material composed of Si (silicon) and C (carbon). Its breakdown field strength is 10 times that of Si, and its bandgap is 3 times that of Si. At the same breakdown voltage level, SiC MOSFET devices have a much lower specific on-resistance than Si-based devices. Furthermore, SiC can achieve high breakdown voltages above 3KV through higher doping and thinner drift region thickness, thus being considered a power device material that surpasses the limits of Si. Simultaneously, SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), which is the same insulator as the oxide formed by the oxidation of Si. SiO2 has excellent performance as a passivation film in Si-based power devices, making it possible to fabricate entirely MOS-based devices using SiC.

[0003] The reverse conduction capability of silicon carbide (SiC) power transistors is crucial in practical switching processes. Since the body diode turn-on voltage of SiC is as high as approximately 2.7V, severely impacting switching performance, integrating a unipolar diode with a low reverse conduction voltage into the SiC MOSFET to deactivate the body pin diode is a reliable option. Examples include SiC MOSFETs with JBS diodes, SiC-MOSFETs with built-in SBDs, and SiC switch-MOS. On the other hand, due to p... + Heterojunction diodes composed of polycrystalline silicon and n-type SiC have been experimentally proven to have the unipolar effect of SBDs.

[0004] In current SiC integrated SBD solutions, using high work function metals is the main choice to reduce SBD leakage current, but this leads to a higher turn-on voltage of the SBD, thereby increasing switching losses. How to improve the third quadrant conduction capability of SBD integrated MOSFETs is the future development direction of SiC-MOS. Summary of the Invention

[0005] This invention discloses an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, which includes, from bottom to top, a silicon carbide substrate, an N-type drift layer and an N-type carrier storage layer.

[0006] N + Region and P +Regions, alternately distributed on the upper part of the N-type carrier storage layer; deep trenches, penetrating the N-type carrier storage layer. + Region and P + The region, located at the bottom, is situated within an N-type carrier storage layer; the P-type buried layer is formed within the N-type carrier storage layer at the bottom of the deep trench; the source is filled with the central N-type carrier storage layer. + The deep trenches on both sides of the region form a Schottky contact barrier with the N-type carrier storage layer on the sidewalls; the gate oxide layer covers the sidewalls and bottom of the outermost deep trench; the gate covers the gate oxide layer and fills the outermost deep trench; the P-type base region is formed between the gate and the source. + Region and P + In the N-type carrier storage layer below the region; a passivation layer covers the gate surface; a source ohmic contact covers the device surface, wherein the ohmic contact and the Schottky contact simultaneously serve as a reverse conduction mechanism. During reverse freewheeling, the source ohmic contact portion of the device conducts first at a low voltage, and then the Schottky diode turns on, achieving a lower reverse turn-on voltage for the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, resulting in a lower reverse leakage current for the device.

[0007] In the SBD integrated silicon carbide MOSFET of the present invention, which enhances reverse freewheeling capability, the source electrode is preferably a high work function metal, P + Polycrystalline silicon layer.

[0008] In the SBD integrated silicon carbide MOSFET of the present invention, which improves reverse freewheeling capability, preferably, the gate is N-type. + Polycrystalline silicon layer.

[0009] In the SBD integrated silicon carbide MOSFET of the present invention, which improves reverse freewheeling capability, the doping concentration of the P-type buried layer is preferably 1e18 / cm. 3 Magnitude.

[0010] This invention also discloses a method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, comprising the following steps: epitaxially forming an N-type drift layer and an N-type carrier storage layer on a silicon carbide substrate; subsequently forming alternating N-type carrier storage layers on the upper part of the N-type carrier storage layer by two photolithography processes and corresponding ion implantation. + Region, P + The region; finally, through a single photolithography step and corresponding ion implantation on both sides, N + Region and P +A P-type base region is formed in the N-type carrier storage layer below the region; spaced deep trenches are formed, with the bottom of the trenches located in the N-type carrier storage layer; a continuously distributed oxide layer is deposited, the oxide layer is etched back, the oxide layer at the bottom of the trenches is removed, forming sidewalls and source ion implantation barrier layers; ion implantation forms a P-type buried layer at the bottom of the trenches; all oxide layers are removed, and high-temperature annealing activates all implanted ions; in the central N... + The deep trenches on both sides of the region form the source; a gate oxide layer is formed on the sidewall and bottom of the outermost deep trench; a gate is formed to cover the gate oxide layer and completely fill the outermost deep trench, and a Schottky contact barrier with the N-type carrier storage layer is formed on the sidewall; a passivation layer is deposited, and photolithography is used to define the source metal contact region, retaining only the passivation layer on the surface of the gate on both sides; an ohmic contact is formed to cover the device surface, and then chemical mechanical polishing is performed. The ohmic contact and the Schottky contact serve as a reverse conduction mechanism. During reverse freewheeling, the source ohmic contact portion of the device conducts first at a low voltage, and then the Schottky diode turns on, achieving a lower reverse turn-on voltage for the device; in the blocking state, the ohmic contact source is pinched off by the Schottky barrier, resulting in a lower reverse leakage current for the device.

[0011] In the method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the source electrode is a high work function metal, P + Polycrystalline silicon layer.

[0012] In the method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the gate is N-type. + Polycrystalline silicon layer.

[0013] In the method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability of the present invention, preferably, the doping concentration of the P-type buried layer is 1e18 / cm. 3 Magnitude.

[0014] Beneficial effects:

[0015] SiC double-trench structure filled with nickel and other metals with high work function (work function around 5.1 eV) / p + Polycrystalline silicon achieves a high Schottky contact barrier with the N-type carrier storage layer on the SiC sidewall. During reverse breakdown, this structure utilizes the MESFET depletion principle to pinch off the barrier. During reverse turn-on, the sidewall Schottky barrier decreases, providing a channel for the conduction of electrons in the source region.

[0016] The top of the polysilicon-SiC heterojunction diode structure is designed as an ohmic contact, which has a stronger reverse turn-on capability and can effectively reduce the switching loss of the device. When the longitudinal withstand voltage is low, the high Schottky barrier of the heterojunction ensures the low leakage current of the device.

[0017] The heterojunction depletion region formed by the p+ polysilicon structure and SiC contact changes significantly with the bias voltage. Therefore, compared with the traditional SBD, this structure utilizes the combined effect of ohmic and Schottky contacts during reverse conduction to achieve a lower diode reverse turn-on voltage.

[0018] The device employs a dual-trench source structure, defining the gate and source trenches through a single photolithography and directional etching process, resulting in a relatively simple fabrication process. The polysilicon used as the source trench effectively alleviates electric field congestion in the gate trench, protects the gate oxide layer, and gives the device good breakdown voltage characteristics. Attached Figure Description

[0019] Figure 1 This is a flowchart of a method for fabricating SBD integrated silicon carbide MOSFETs to improve reverse freewheeling capability.

[0020] Figures 2 to 20 This is a schematic diagram of the various stages of the fabrication method for SBD integrated silicon carbide MOSFETs to improve reverse freewheeling capability. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0022] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0024] Figure 1 This is a flowchart illustrating the fabrication method of SBD integrated silicon carbide MOSFETs to improve reverse freewheeling capability. (Example) Figure 1 As shown, the fabrication method for SBD integrated silicon carbide MOSFETs with improved reverse freewheeling capability includes the following steps:

[0025] Step S1: Epitaxial doping concentration of 6e15 / cm on silicon carbide substrate 100. 3 The N-type drift layer 101 and the doping concentration of 2e16 / cm 3 The resulting structure of the N-type carrier storage layer (N-CSL) 102 is as follows: Figure 2 As shown. Subsequently, alternating heavily doped N₂ layers were formed on the upper part of the N-type carrier storage layer 102 through two photolithography processes and corresponding ion implantation. + Area 103, P + Region 104, the resulting structure is as follows Figure 3 As shown. Finally, through a single photolithography step and corresponding ion implantation on both sides, N... + Area 103 and P + A doping concentration of 2e17 / cm is formed in the N-type carrier storage layer 102 below region 104. 3 The resulting structure is as follows: P-base region 105. Figure 4 As shown. Where N + The depth of region 103 is controlled at around 0.2 μm to ensure sufficient ohmic contact area above the SBD.

[0026] Step S2: Define the trench region using photolithography, and etch to form deep trenches with a depth of 1.3 μm spaced apart, the trenches penetrating N. + Area 103, P + Region 104 and P-type base region 105, with the bottom located at N-type carrier storage layer 102, the resulting structure is as follows Figure 5 As shown in the diagram, two deep trenches in the central region serve as source trenches, while the deep trenches on either side of the periphery serve as gate trenches. The width of the source trenches is approximately 0.2 μm, slightly narrower than that of the gate trenches. A continuously distributed oxide layer 106 is then deposited, resulting in the structure shown below. Figure 6 As shown. The oxide layer 106 is etched back, removing the oxide layer 106 at the bottom of the trench to form sidewalls and a source ion implantation barrier layer. The resulting structure is shown below. Figure 7 As shown.

[0027] Step S3: Ion implantation is used to form a doping concentration of 1e18 / cm at the bottom of the trench. 3 The structure obtained from the P-well 107, a P-type buried layer of a certain magnitude, is as follows: Figure 8As shown. This concentration of buried layer implantation can effectively reduce the peak electric field of the device under breakdown voltage, protect the gate oxide and the subsequently filled polysilicon heterojunction, without affecting the reverse turn-on of the device. Afterwards, all oxide layers 106 were removed, and the implanted ions were activated by annealing at 1700℃ for 30 minutes. The resulting structure is shown in the figure. Figure 9 As shown.

[0028] Step S4, the deposition doping concentration is 1e19 / cm 3 P + The polysilicon layer 108 fills each deep trench, resulting in the structure shown below. Figure 10 As shown, in N located in the center + P is formed in the source trenches on both sides of region 103. + A polycrystalline silicon layer serves as the source electrode, forming a double-trench source electrode structure. + Polysilicon creates a high Schottky contact barrier with the N-type carrier storage layer on the SiC sidewalls. During reverse breakdown, this structure utilizes the MESFET depletion principle for pinch-off; during reverse turn-on, the sidewall Schottky barrier decreases, providing a channel for electron conduction in the source region. Alternatively, a high work function metal with a work function of around 5.1 eV, such as nickel or platinum, can be used as the source. Then, a silicon nitride layer 109 is deposited on the device surface as a mask for polysilicon etch-back and subsequent gate oxide oxidation. The resulting structure is shown below. Figure 11 As shown. Photolithography etching removes the silicon nitride layer 109 located at the top of the gate trenches on both sides of the periphery, resulting in the structure shown. Figure 12 As shown.

[0029] Step S5, wet etching back P gate trench region + Polycrystalline silicon layer 108, the resulting structure is as follows Figure 13 As shown. Then, dry oxidation of the gate oxide was performed at 1050℃ for 130 minutes to form a 50nm thick gate oxide layer 110 on the bottom and sidewalls of the gate trench. Simultaneously, the gate oxide layer 110 was deposited at the bottom of the trench. The resulting structure is shown. Figure 14 As shown. Subsequently, N-type metal as the gate is deposited over a large area. + A polycrystalline silicon layer 111 is applied to cover the device surface, resulting in the following structure: Figure 15 As shown.

[0030] Step S6, deposit N + Polysilicon layer 111 etched back N portion + The polysilicon layer 111 exposes the surface of the silicon nitride layer 109 and makes the N-type gate trenches on both sides visible. + The upper surface of polysilicon layer 111 and N + Area 103 and P + The upper surface of region 104 is flush with the ground to form a gate, resulting in the structure shown below. Figure 16As shown. Then, the silicon nitride barrier layer 109 is etched away, and the resulting structure is as follows. Figure 17 As shown.

[0031] Step S7, deposit an oxide layer as passivation layer 112, resulting in the structure shown below. Figure 18 As shown. Photolithography defines the source metal contact region, and the passivation layer 112 is etched, retaining only the passivation layers 112 on both sides of the gate surface. The resulting structure is as shown. Figure 19 As shown.

[0032] Step S8: Deposit metallic nickel to form the source ohmic contact 113, then perform chemical mechanical polishing on the top of the device to form a single-cell structure, as shown in the figure. Figure 20 As shown.

[0033] like Figure 20 As shown, the SBD integrated silicon carbide MOSFET for improving reverse freewheeling capability includes, from bottom to top, a silicon carbide substrate 100, an N-type drift layer 101, and an N-type carrier storage layer 102; N + Area 103 and P + Region 104 is alternately distributed on the upper part of the N-type carrier storage layer 102; deep trenches are spaced out and penetrate the N-type carrier storage layer. + Area 103 and P + Region 104, with its bottom located within the N-type carrier storage layer 102; P-type buried layer 107, formed within the N-type carrier storage layer 102 at the bottom of the deep trench; source 108, filled with the central N-type carrier storage layer 102. + The deep trenches on both sides of region 103 form a Schottky contact barrier with the N-type carrier storage layer on the sidewalls; the gate oxide layer 110 covers the sidewalls and bottom of the outermost deep trench; the gate 111 covers the gate oxide layer 110 and fills the outermost deep trench; the P-type base region 105 is formed between the gate 111 and the source 108. + Area 103 and P + In the N-type carrier storage layer 102 below region 104; passivation layer 112, covering the surface of the gate 111; source ohmic contact 113, covering the device surface.

[0034] The SiC dual-trench structure is filled with high work function metal / p+ polysilicon, which creates a high Schottky contact barrier with the N-type carrier storage layer on the SiC sidewall. During reverse breakdown, the structure is pinched off using the MESFET depletion principle; during reverse turn-on, the Schottky barrier on the sidewall is reduced, providing a channel for the conduction of electrons in the source region.

[0035] The top of the polysilicon-SiC heterojunction diode structure is designed as an ohmic contact, providing stronger reverse turn-on capability and effectively reducing switching losses. During longitudinal breakdown voltage testing, the high Schottky barrier of the heterojunction ensures low leakage current. The top of the device is sandwiched between P...+ The width W of the silicon carbide plateau between polysilicon trenches mesa The thickness needs to be optimized to around 0.35μm to ensure that the device has good switching characteristics while avoiding reverse voltage punch-through at high temperatures.

[0036] The entire device employs a dual-trench source structure, defining the gate and source trenches through a single photolithography and directional etching process, resulting in a relatively simple fabrication process. The polysilicon serving as the source trench effectively alleviates electric field congestion in the gate trench, protecting the gate oxide layer and giving the device good breakdown voltage characteristics. Simultaneously, the reverse transfer capacitance is reduced by approximately 70%, resulting in lower switching delay and further improving switching efficiency.

[0037] The device designed in this patent uses both ohmic and Schottky contacts as reverse conduction mechanisms: during reverse freewheeling, the ohmic contact portion of the device source conducts first at a low voltage, and then the Schottky diode turns on, achieving a lower reverse turn-on voltage. In the blocking state, the ohmic contact source is pinched off by the Schottky barrier, resulting in a lower reverse leakage current.

[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, characterized in that, From bottom to top, it includes a silicon carbide substrate, an N-type drift layer, and an N-type carrier storage layer; N + Region and P + The regions are alternately distributed in the upper part of the N-type carrier storage layer; Deep trenches, penetrating the N + Region and P + The region, at its bottom, is located within the N-type carrier storage layer; A P-type buried layer is formed in an N-type carrier storage layer at the bottom of a deep trench; Source, filled with central N + The deep trenches on both sides of the region create a Schottky contact barrier with the N-type carrier storage layer on the sidewalls; The gate oxide layer covers the sidewalls and bottom of the outermost deep trench; The gate electrode covers the gate oxide layer and fills the outermost deep trench; The P-type base region is formed between the gate and the source. + Region and P + In the N-type carrier storage layer below the region; A passivation layer covers the gate surface; Source ohmic contact, covering the device surface. In this device, both the ohmic contact and the Schottky contact serve as reverse conduction mechanisms. During reverse freewheeling, the ohmic contact portion of the device source conducts first at a low voltage, and then the Schottky diode turns on, resulting in a lower reverse turn-on voltage. In the blocking state, the ohmic contact source is pinched off by the Schottky barrier, giving the device a lower reverse leakage current.

2. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, characterized in that, The source metal is a high work function metal, P + Polycrystalline silicon layer.

3. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, characterized in that, The gate is N + Polycrystalline silicon layer.

4. The SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 1, characterized in that, The doping concentration of the P-type buried layer is 1e18 / cm. 3 Magnitude.

5. A method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability, characterized in that, Includes the following steps: An N-type drift layer and an N-type carrier storage layer are epitaxially grown on a silicon carbide substrate; Subsequently, alternating N-type carrier storage layers were formed on the upper part of the N-type carrier storage layer through two photolithography processes and corresponding ion implantation. + Region, P + area; Finally, through a single photolithography step and corresponding ion implantation on both sides, N... + Region and P + A P-type base region is formed in the N-type carrier storage layer below the region; Deep trenches are formed with spacing, and the bottom of the trenches is located in the N-type carrier storage layer; A continuously distributed oxide layer is deposited, the oxide layer is etched back, the oxide layer at the bottom of the trench is removed, and a sidewall and source ion implantation barrier layer are formed. Ion implantation forms a P-type buried layer at the bottom of the trench; Remove all oxide layers and activate all implanted ions with high-temperature annealing; On CCTV-9 + The deep trenches on both sides of the region form the source, and the Schottky contact barrier with the N-type carrier storage layer is realized on the sidewall; A gate oxide layer is formed on the sidewalls and bottom of the outermost deep trench; a gate is formed to cover the gate oxide layer and completely fill the outermost deep trench. A passivation layer is deposited, and photolithography is used to define the source metal contact area, leaving only the passivation layer on the two gate surfaces. A source ohmic contact is formed to cover the device surface, followed by chemical mechanical polishing. In this device, both the ohmic contact and the Schottky contact serve as reverse conduction mechanisms. During reverse freewheeling, the ohmic contact portion of the device source conducts first at a low voltage, and then the Schottky diode turns on, resulting in a lower reverse turn-on voltage. In the blocking state, the ohmic contact source is pinched off by the Schottky barrier, giving the device a lower reverse leakage current.

6. The method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, characterized in that, The source metal is a high work function metal, P + Polycrystalline silicon layer.

7. The method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, characterized in that, The gate is N + Polycrystalline silicon layer.

8. The method for fabricating an SBD integrated silicon carbide MOSFET with improved reverse freewheeling capability according to claim 5, characterized in that, The doping concentration of the P-type buried layer is 1e18 / cm. 3 Magnitude.

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