Semiconductor device and preparation method thereof
By setting up a stacked shield gate structure in the superjunction metal-oxide semiconductor field effect transistor, the bipolar conduction of electron-holes is transformed into a unipolar conduction, and the small breakdown voltage and reverse recovery characteristics are solved. The problem has improved the reliability and electrical performance of semiconductor devices.
Patent Information
- Application Number
- CN202411294478.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-20
AI Technical Summary
The presence of trench in superjunction metal-oxide semiconductor field effect transistors results in a small breakdown voltage and a reverse recovery characteristic in the reverse flow state, reducing the reliability and electrical properties of the semiconductor device.
By providing a stack on the basis of the first semiconductor layer and the second semiconductor layer, a secondary field effect tube is formed, and the gate conductive layer in the stack is arranged as a shield gate, connecting the first gate conductive layer and the gate electrode, The second gate conductive layer and the source electrode use the voltage drop of the source to conduct the secondary field effect tube in the reverse flow state, thereby transforming the bipolar conduction of electron-holes into the unipolar conduction of electrons. A hole injection is suppressed, and a depletion layer is formed between the first type semiconductor column and the second type semiconductor column.
It improves the breakdown voltage and reliability of semiconductor devices, improves the reverse recovery characteristics, reduces the internal resistance of the device, increases the saturation current and output capability, and reduces power consumption.
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Figure CN119170640A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJ MOSFET) can modulate the electric field inside the device by setting P-type and N-type columns, thereby breaking through the "silicon limit" relationship between the specific on-resistance and withstand voltage of traditional power devices. In addition, the parasitic capacitance of the super junction metal-oxide semiconductor field effect transistor is small, and the vertical channel does not need to set a drift region, so the specific on-resistance is low, making the super junction metal-oxide semiconductor field effect transistor widely used in power semiconductors.
[0003] However, due to the presence of trenches in the superjunction metal-oxide semiconductor field effect transistor, the breakdown voltage is small, and when the device is in a reverse current flow state, there is a reverse recovery characteristic, which reduces the reliability and electrical properties of the semiconductor device. Summary of the invention
[0004] The purpose of this application is to provide a semiconductor device and a method for preparing the same, which solves the problem of low breakdown voltage during semiconductor operation and reverse recovery characteristics when the device is in a reverse current state, thereby improving the reliability and electrical properties of the semiconductor device. To achieve the purpose of this application, this application provides the following technical solutions:
[0005] In a first aspect, the present application provides a semiconductor device, comprising:
[0006] substrate;
[0007] A first semiconductor layer, located on the substrate, comprises first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate;
[0008] A second semiconductor layer, located on a top surface of the first semiconductor layer;
[0009] A stack, penetrating the second semiconductor layer along a second direction perpendicular to the substrate and extending to the interior of the second-type semiconductor column; the stack comprises a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate;
[0010] The second-type semiconductor layer is buried in the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart and distributed along the second direction.
[0011] The semiconductor device of the present application includes a substrate, a first semiconductor layer, a second semiconductor layer and a stack, wherein the first semiconductor layer is located on the substrate and includes first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate, the stack penetrates the second semiconductor layer along a second direction perpendicular to the substrate and extends to the inside of the second-type semiconductor columns, the stack includes the first-type semiconductor layer, the second-type semiconductor layer and the gate dielectric layer sequentially distributed along a direction away from the substrate, wherein the second-type semiconductor layer is buried in the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart and distributed along the second direction. A secondary field effect transistor is formed by arranging a stack on the basis of a first semiconductor layer and a second semiconductor layer, and the gate conductive layer in the stack is arranged as a shielding gate. Since the first gate conductive layer in the stack is connected to the gate, and the top of the stack, the second gate conductive layer and the second type semiconductor layer in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source makes the secondary field effect transistor conduct, so that the reverse conduction process is transformed from bipolar conduction of electrons and holes to unipolar conduction of electrons, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first type semiconductor column and the second type semiconductor column to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0012] In one embodiment, the gate dielectric layer circumferentially covers the first gate conductive layer and covers the top surface and the bottom surface of the first gate conductive layer; and
[0013] The gate dielectric layer circumferentially wraps around the second gate conductive layer and covers the top surface and the bottom surface of the second gate conductive layer.
[0014] In one embodiment, the second-type semiconductor pillar circumferentially surrounds the stack and covers the bottom surface of the stack.
[0015] In one embodiment, the top surface of the second semiconductor layer is lower than the top surface of the stack; the semiconductor device further comprises:
[0016] a third semiconductor layer circumferentially surrounding the stack;
[0017] The third semiconductor layer includes a first-type doping region and a second-type doping region sequentially distributed along the first direction, and the second-type doping region is located between the first-type doping region and the stacked layer.
[0018] In one embodiment, the first type is P type, and the second type is N type; or
[0019] The first type is N type, and the second type is P type.
[0020] In a second aspect, the present application further provides an electronic device, including:
[0021] A semiconductor device as described in any of the above.
[0022] The electronic device of the present application includes any of the semiconductor devices described above, and a stack is provided on the basis of a first semiconductor layer and a second semiconductor layer to form a secondary field effect transistor, and the gate conductive layer in the stack is provided as a shielding gate. Since the first gate conductive layer in the stack is connected to the gate, and the top of the stack, the second gate conductive layer and the second type semiconductor layer in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source causes the secondary field effect transistor to be turned on, thereby converting the bipolar conduction of electrons and holes into unipolar conduction of electrons during the reverse conduction process, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first type semiconductor column and the second type semiconductor column to deplete each other, thereby increasing the breakdown voltage of the device, and improving the reliability and electrical properties of the semiconductor device.
[0023] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:
[0024] providing a substrate;
[0025] forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate;
[0026] A second semiconductor layer is formed on the top surface of the first semiconductor layer, and a stack is formed along a second direction perpendicular to the substrate, the stack penetrates the second semiconductor layer and extends to the inside of the second-type semiconductor column; the stack includes a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; wherein the second-type semiconductor layer is buried inside the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along the second direction.
[0027] The preparation method of the semiconductor device of the present application includes providing a substrate; then forming a first semiconductor layer on the substrate, the first semiconductor layer including first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate; finally forming a second semiconductor layer on the top surface of the first semiconductor layer, and forming a stack along a second direction perpendicular to the substrate, the stack penetrates the second semiconductor layer and extends to the inside of the second-type semiconductor column; the stack includes a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; wherein the second-type semiconductor layer is buried in the inside of the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart and distributed along the second direction. A secondary field effect transistor is formed by arranging a stack on the basis of a first semiconductor layer and a second semiconductor layer, and the gate conductive layer in the stack is arranged as a shielding gate. Since the first gate conductive layer in the stack is connected to the gate, and the top of the stack, the second gate conductive layer and the second type semiconductor layer in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source makes the secondary field effect transistor conduct, so that the reverse conduction process is transformed from bipolar conduction of electrons and holes to unipolar conduction of electrons, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first type semiconductor column and the second type semiconductor column to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0028] In one embodiment, forming a second semiconductor layer on the top surface of the first semiconductor layer and forming a stacked layer along a second direction perpendicular to the substrate includes:
[0029] forming a trench in the first semiconductor layer;
[0030] forming the first-type semiconductor layer in the trench, and forming a second semiconductor layer on a top surface of the first semiconductor layer;
[0031] forming the second-type semiconductor layer in the first-type semiconductor layer, wherein the second-type semiconductor layer is buried inside the first-type semiconductor layer;
[0032] A gate dielectric layer is formed on the top surface of the second-type semiconductor layer to form the stack, wherein the top surface of the second semiconductor layer is lower than the top surface of the stack, wherein the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along the second direction, the gate dielectric layer circumferentially coats the first gate conductive layer and covers the top and bottom surfaces of the first gate conductive layer; and the gate dielectric layer circumferentially coats the second gate conductive layer and covers the top and bottom surfaces of the second gate conductive layer.
[0033] In one embodiment, the second-type semiconductor pillar circumferentially surrounds the stack and covers the bottom surface of the stack.
[0034] In one embodiment, after forming the second semiconductor layer on the top surface of the first semiconductor layer, the method further includes:
[0035] A third semiconductor layer is formed on the top surface of the second semiconductor layer, and the third semiconductor layer circumferentially surrounds the stack; wherein the third semiconductor layer includes a first-type doping region and a second-type doping region sequentially distributed along the first direction, and the second-type doping region is located between the first-type doping region and the stack. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;
[0038] Figure 2 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;
[0039] Figure 3 is a schematic cross-sectional structural diagram of a structure obtained in step S11 in a method for preparing a semiconductor device provided in another embodiment;
[0040] Figure 4 is a schematic cross-sectional structural diagram of a structure obtained in step S12 in a method for preparing a semiconductor device provided in another embodiment;
[0041] Figure 5 is a flow chart of steps S121 to S126 in a method for preparing a semiconductor device provided in another embodiment;
[0042] Figure 6 is a schematic cross-sectional view of a structure obtained in step S121 in a method for preparing a semiconductor device provided in another embodiment;
[0043] Figure 7 is a schematic cross-sectional structural diagram of a structure obtained in step S122 in a method for preparing a semiconductor device provided in another embodiment;
[0044] Figure 8 is a schematic cross-sectional view of a structure obtained in step S123 in a method for preparing a semiconductor device provided in another embodiment;
[0045] Fig. 9 is a schematic cross-sectional structural diagram of a structure obtained in step S124 in a method for preparing a semiconductor device provided in another embodiment;
[0046] Fig.10 is a schematic cross-sectional structural diagram of a structure obtained in step S125 in a method for preparing a semiconductor device provided in another embodiment;
[0047] Fig.11 is a flow chart of steps S131 to S134 in a method for preparing a semiconductor device provided in another embodiment;
[0048] Fig.12 is a schematic cross-sectional structural diagram of a structure obtained in step S131 in a method for preparing a semiconductor device provided in another embodiment;
[0049] Fig.13 is a schematic cross-sectional structural diagram of a structure obtained in step S132 and step S133 in a method for preparing a semiconductor device provided in another embodiment;
[0050] Fig.14 is a schematic cross-sectional structural diagram of a structure obtained in step S134 in a method for preparing a semiconductor device provided in another embodiment;
[0051] Fig.15 is a schematic cross-sectional structural diagram of a structure obtained in step S1341 in a method for preparing a semiconductor device provided in another embodiment;
[0052] Fig.16 It is a schematic cross-sectional structural diagram of a structure obtained in step S1342 in a method for preparing a semiconductor device provided in another embodiment.
[0053] Description of Reference Numerals
[0054] 10. substrate; 101. heavily doped epitaxial layer; 20. first semiconductor layer; 201. first type semiconductor column; 2011. initial first type semiconductor column; 202. second type semiconductor column; 2021. first initial second type semiconductor column; 2022. second initial second type semiconductor column; 203. initial first semiconductor layer; 30. second semiconductor layer; 40. stack; 401. first type semiconductor layer; 402. second type semiconductor layer; 403. gate dielectric layer; 4031. first gate dielectric layer; 4032. second gate dielectric layer; 404. first gate conductive layer; 405. second gate conductive layer; 50. third semiconductor layer; 501. first type doped region; 502. second type doped region; 60. trench. DETAILED DESCRIPTION
[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0057] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0060] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0061] Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJ MOSFET) can modulate the electric field inside the device by setting P-type and N-type columns, thereby breaking through the "silicon limit" relationship between the specific on-resistance and withstand voltage of traditional power devices. In addition, the parasitic capacitance of the super junction metal-oxide semiconductor field effect transistor is small, and the vertical channel does not need to set a drift region, so the specific on-resistance is low, making the super junction metal-oxide semiconductor field effect transistor widely used in power semiconductors.
[0062] However, due to the presence of trenches in the superjunction metal-oxide semiconductor field effect transistor, the breakdown voltage is small, and when the device is in a reverse current flow state, there is a reverse recovery characteristic, which reduces the reliability and electrical properties of the semiconductor device.
[0063] The present application embodiment provides a semiconductor device. Figure 1 The semiconductor device may include: a substrate 10 , a first semiconductor layer 20 , a second semiconductor layer 30 and a stack 40 .
[0064] The first semiconductor layer 20 is located on the substrate 10, and includes a first-type semiconductor column 201 and a second-type semiconductor column 202 alternately distributed along a first direction parallel to the substrate 10; the second semiconductor layer 30 is located on the top surface of the first semiconductor layer 20; the stack 40 penetrates the second semiconductor layer 30 along a second direction perpendicular to the substrate 10 and extends to the inside of the second-type semiconductor column 202; the stack 40 includes a first-type semiconductor layer 401, a second-type semiconductor layer 402, and a gate dielectric layer 403 sequentially distributed along a direction away from the substrate 10; wherein the second-type semiconductor layer 402 is buried in the first-type semiconductor layer 401, and the gate dielectric layer 403 is coated with a first gate conductive layer 404 and a second gate conductive layer 405 spaced apart along the second direction.
[0065] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate, and the substrate 10 includes a heavily doped epitaxial layer 101 of the second conductivity type located on the substrate 10. Specifically, in the present embodiment, the substrate 10 is a silicon substrate, and the heavily doped epitaxial layer 101 of the second conductivity type is an N-type heavily doped epitaxial layer.
[0066] Exemplarily, the first direction is defined as the direction of the x-axis, and the second direction is defined as the direction of the y-axis.
[0067] Exemplarily, the first-type semiconductor pillar 201 is a P-type semiconductor pillar, and the second-type semiconductor pillar 202 is an N-type semiconductor pillar.
[0068] Exemplarily, the second semiconductor layer 30 is a P-type semiconductor layer. Specifically, in this embodiment, the doping concentration of the second semiconductor layer 30 is greater than the doping concentration of the first-type semiconductor pillar 201 .
[0069] Exemplarily, the first-type semiconductor layer 401 is a P-type semiconductor layer, the second-type semiconductor layer 402 is an N-type semiconductor layer, the gate dielectric layer 403 may include but is not limited to an oxide layer, the first gate conductive layer 404 may include but is not limited to a polysilicon layer, and the second gate conductive layer 405 may include but is not limited to a polysilicon layer.
[0070] The semiconductor device of the present application includes a substrate 10, a first semiconductor layer 20, a second semiconductor layer 30 and a stack 40. The first semiconductor layer 20 is located on the substrate 10, and includes first-type semiconductor pillars 201 and second-type semiconductor pillars 202 that are alternately distributed along a first direction parallel to the substrate 10. The stack 40 penetrates the second semiconductor layer 30 along a second direction perpendicular to the substrate 10 and extends to the inside of the second-type semiconductor pillars 202. The stack 40 includes a first-type semiconductor layer 401, a second-type semiconductor layer 402, and a gate dielectric layer 403 that are sequentially distributed along a direction away from the substrate 10, wherein the second-type semiconductor layer 402 is buried in the first-type semiconductor layer 401, and the gate dielectric layer 403 is coated with a first gate conductive layer 404 and a second gate conductive layer 405 that are spaced apart along the second direction. A secondary field effect transistor is formed by setting a stack 40 on the basis of the first semiconductor layer 20 and the second semiconductor layer 30, and the gate conductive layer in the stack 40 is set as a shielding gate. Since the first gate conductive layer 404 in the stack 40 is connected to the gate, and the top of the stack 40, the second gate conductive layer 405 and the second-type semiconductor layer 402 in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source makes the secondary field effect transistor turn on, so that the bipolar conduction of electrons and holes is transformed into unipolar conduction of electrons during the reverse conduction process, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first-type semiconductor column 201 and the second-type semiconductor column 202 to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0071] In some embodiments, please refer to Figure 1 , the gate dielectric layer 403 circumferentially covers the first gate conductive layer 404 and covers the top and bottom surfaces of the first gate conductive layer 404 ; and the gate dielectric layer circumferentially covers the second gate conductive layer 405 and covers the top and bottom surfaces of the second gate conductive layer 405 .
[0072] As an example, the gate dielectric layer 403 circumferentially covers the first gate conductive layer 404 and covers the top and bottom surfaces of the first gate conductive layer 404; and the gate dielectric layer 403 circumferentially covers the second gate conductive layer 405 and covers the top and bottom surfaces of the second gate conductive layer 405, thereby ensuring that the gate dielectric layer 403 isolates the first gate conductive layer 404 and the second gate conductive layer 405 to form a shielding gate, thereby reducing the internal resistance of the device, increasing the saturation current, enhancing the output capacity and reducing the power consumption of the device.
[0073] In the embodiment of the present application, the first gate conductive layer 404 and the second gate conductive layer 405 are isolated from each other by the gate dielectric layer 403 to form a shielding gate, thereby reducing the internal resistance of the device, increasing the saturation current, enhancing the output capacity and reducing the power consumption of the device.
[0074] In some embodiments, please refer to Figure 1 The second-type semiconductor pillar 202 circumferentially surrounds the stack 40 and covers the bottom surface of the stack 40 .
[0075] As an example, the second-type semiconductor pillar 202 circumferentially surrounds the stack 40 and covers the bottom surface of the stack 40 to ensure that the secondary field effect transistor formed by the first-type semiconductor layer 401 and the second-type semiconductor layer 402 in the stack 40 can be covered by the second-type semiconductor pillar 202 .
[0076] In this embodiment, by circumferentially surrounding the stack 40 and covering the bottom surface of the stack 40, the second-type semiconductor column 202 can ensure that the secondary field effect transistor formed by the first-type semiconductor layer 401 and the second-type semiconductor layer 402 in the stack 40 can be covered by the second-type semiconductor column 202, thereby ensuring that when the device is in a reverse flow state, the voltage drop acting on the source causes the secondary field effect transistor to be turned on, thereby converting the bipolar conduction of electrons and holes into the unipolar conduction of electrons during the reverse conduction process, thereby suppressing the injection of holes into the second-type semiconductor column 202, thereby improving the reverse recovery characteristics of the device.
[0077] In some embodiments, please refer to Figure 1 , the top surface of the second semiconductor layer 30 is lower than the top surface of the stack 40; the semiconductor device also includes: a third semiconductor layer 50, circumferentially surrounding the stack 40; wherein the third semiconductor layer 50 includes a first-type doping region 501 and a second-type doping region 502 distributed in sequence along the first direction, and the second-type doping region 502 is located between the first-type doping region 501 and the stack 40.
[0078] As an example, the first type doping region 501 is a P type doping region, and the second type doping region 502 is an N type doping region. Specifically, in this embodiment, the doping concentrations of the first type doping region 501 and the second type doping region 502 are both greater than the doping concentration of the second semiconductor layer. The second type doping region 502 can enable the device to flow between the second type doping regions 502 on both sides of the gate dielectric layer 403 of the stack 40 when the device is in the on state, thereby forming an on current.
[0079] In this embodiment, by setting the first type doping region 501 and the second type doping region 502, the second type doping region 502 can enable the device to flow between the second type doping regions 502 on both sides of the gate dielectric layer 403 of the stack 40 when the device is in the on state, thereby forming an on-current.
[0080] In some embodiments, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.
[0081] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.
[0082] The electronic device of the present application includes the semiconductor device in any of the above embodiments, and a stack is set on the basis of the first semiconductor layer and the second semiconductor layer to form a secondary field effect transistor, and the gate conductive layer in the stack is set as a shielding gate. Since the first gate conductive layer in the stack is connected to the gate, and the top of the stack, the second gate conductive layer and the second type semiconductor layer in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source makes the secondary field effect transistor turn on, so that the bipolar conduction of electrons and holes is transformed into unipolar conduction of electrons during the reverse conduction process, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first type semiconductor column and the second type semiconductor column to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0083] The present invention provides a method for preparing a semiconductor device. Figure 2 , the method for preparing the semiconductor device may include:
[0084] S11: providing a substrate.
[0085] As an example, see Figure 3The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate, and the substrate 10 includes a heavily doped epitaxial layer 101 of a second conductivity type located on the substrate 10. The heavily doped epitaxial layer 101 may be formed by but is not limited to an epitaxial process. Specifically, in this embodiment, the substrate 10 is a silicon substrate, and the heavily doped epitaxial layer 101 of the second conductivity type is an N-type heavily doped epitaxial layer.
[0086] S12: forming a first semiconductor layer on the substrate, wherein the first semiconductor layer includes first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate.
[0087] As an example, see Figure 4 The first direction is defined as the direction of the x-axis, and the second direction is defined as the direction of the y-axis. The first-type semiconductor pillar 201 is a P-type semiconductor pillar, and the second-type semiconductor pillar 202 is an N-type semiconductor pillar. A first semiconductor layer 20 is formed on the substrate 10. The first semiconductor layer 20 includes the first-type semiconductor pillars 201 and the second-type semiconductor pillars 202 that are alternately distributed along a first direction parallel to the substrate 10. Figure 5 , may include the following steps: S121~S126.
[0088] S121: forming an initial first semiconductor layer on a substrate.
[0089] For example, see Figure 6 , a lightly doped epitaxial layer as the initial first semiconductor layer 203 may be formed on the heavily doped epitaxial layer 101 in the substrate 10 by, but not limited to, an epitaxial process.
[0090] S122: forming an initial first-type semiconductor column on a surface of the initial first semiconductor layer facing away from the substrate, wherein the initial first-type semiconductor column circumferentially surrounds the initial first semiconductor layer.
[0091] For example, see Figure 7 The initial first-type semiconductor pillar 2011 may be formed on the surface of the initial first semiconductor layer 203 facing away from the substrate 10 by, but not limited to, an ion implantation process.
[0092] S123: forming a first initial second-type semiconductor column on a top surface of the initial first semiconductor layer and a top surface of the initial first-type semiconductor column.
[0093] For example, see Figure 8 The first initial second-type semiconductor column 2021 may be formed on the top surface of the initial first semiconductor layer 203 and the top surface of the initial first-type semiconductor column 2011 by, but not limited to, an epitaxial process.
[0094] S124: forming a first-type semiconductor column in the first initial second-type semiconductor column, wherein the first-type semiconductor column circumferentially surrounds the first initial second-type semiconductor column.
[0095] For example, see Fig. 9 , the first-type semiconductor column 201 may be formed in the first initial second-type semiconductor column 2021 by, but not limited to, ion implantation.
[0096] S125: forming a second initial second-type semiconductor column on the top surface of the first-type semiconductor column and the top surface of the first initial second-type semiconductor column.
[0097] For example, see Fig.10 The second initial second-type semiconductor column 2022 may be formed on the top surface of the first-type semiconductor column 201 and the top surface of the first initial second-type semiconductor column 2021 by using, but not limited to, an epitaxial process.
[0098] S126: etching the second initial second-type semiconductor column to form a second-type semiconductor column.
[0099] For example, please refer to Figure 4 The second initial second-type semiconductor pillar 2022 may be etched using, but not limited to, a wet etching process or a dry etching process to form a second-type semiconductor pillar 202 .
[0100] S13: A second semiconductor layer is formed on the top surface of the first semiconductor layer, and a stack is formed along a second direction perpendicular to the substrate, the stack penetrates the second semiconductor layer and extends to the interior of the second-type semiconductor column; the stack includes a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; wherein the second-type semiconductor layer is buried in the interior of the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along the second direction.
[0101] As an example, see Figure 1 , the second semiconductor layer 30 is a P-type semiconductor layer. Specifically, in this embodiment, the doping concentration of the second semiconductor layer 30 is greater than the doping concentration of the first-type semiconductor pillar 201. The first-type semiconductor layer 401 is a P-type semiconductor layer, the second-type semiconductor layer 402 is an N-type semiconductor layer, the gate dielectric layer 403 may include but is not limited to an oxide layer, the first gate conductive layer 404 may include but is not limited to a polysilicon layer, and the second gate conductive layer 405 may include but is not limited to a polysilicon layer.
[0102] The preparation method of the semiconductor device of the present application includes providing a substrate; then forming a first semiconductor layer on the substrate, the first semiconductor layer including first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate; finally forming a second semiconductor layer on the top surface of the first semiconductor layer, and forming a stack along a second direction perpendicular to the substrate, the stack penetrates the second semiconductor layer and extends to the inside of the second-type semiconductor column; the stack includes a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; wherein the second-type semiconductor layer is buried in the inside of the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart and distributed along the second direction. A secondary field effect transistor is formed by arranging a stack on the basis of a first semiconductor layer and a second semiconductor layer, and the gate conductive layer in the stack is arranged as a shielding gate. Since the first gate conductive layer in the stack is connected to the gate, and the top of the stack, the second gate conductive layer and the second type semiconductor layer in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source makes the secondary field effect transistor conduct, so that the reverse conduction process is transformed from bipolar conduction of electrons and holes to unipolar conduction of electrons, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first type semiconductor column and the second type semiconductor column to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0103] In some embodiments, see Fig.11 , forming a second semiconductor layer on the top surface of the first semiconductor layer, and forming a stacked layer along a second direction vertical to the substrate may include the following steps: step S131 to step S134.
[0104] S131: forming a trench in the first semiconductor layer.
[0105] As an example, see Fig.12 The trench 60 may be formed in the first semiconductor layer 20 by, but not limited to, a wet etching process or a dry etching process.
[0106] S132: forming a first type semiconductor layer in the trench, and forming a second semiconductor layer on a top surface of the first semiconductor layer.
[0107] As an example, see Fig.13 The first type semiconductor layer 401 may be formed in the trench 60 by, but is not limited to, an ion implantation process, and the second semiconductor layer 30 may be formed on the top surface of the first semiconductor layer 20 .
[0108] S133: forming a second type semiconductor layer in the first type semiconductor layer, wherein the second type semiconductor layer is buried inside the first type semiconductor layer.
[0109] As an example, see Fig.13 The second type semiconductor layer 402 may be formed in the first type semiconductor layer 401 by, but not limited to, ion implantation process, and the second type semiconductor layer 402 is buried inside the first type semiconductor layer.
[0110] S134: A gate dielectric layer is formed on the top surface of the second-type semiconductor layer to form a stack, wherein the top surface of the second semiconductor layer is lower than the top surface of the stack, wherein the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along a second direction, the gate dielectric layer circumferentially coats the first gate conductive layer and covers the top and bottom surfaces of the first gate conductive layer; and the gate dielectric layer circumferentially coats the second gate conductive layer and covers the top and bottom surfaces of the second gate conductive layer.
[0111] As an example, see Fig.14 , forming a gate dielectric layer on the top surface of the second type semiconductor layer to form a stack may include the following steps: S1341~S1342.
[0112] S1341: forming a first gate dielectric layer and a first gate conductive layer covered by the first gate dielectric layer on the top surface of the second type semiconductor layer.
[0113] For example, see Fig.15 A first gate dielectric layer 4031 and a first gate conductive layer 404 covered by the first gate dielectric layer may be formed on the top surface of the second semiconductor layer by, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).
[0114] S1342: forming a second gate dielectric layer on the top surface of the first gate dielectric layer, and a second gate conductive layer covered by the second gate dielectric layer to form a stack.
[0115] For example, see Fig.16 , a second gate dielectric layer 4032 can be formed on the top surface of the first gate dielectric layer 4031 by, but not limited to, physical vapor deposition, chemical vapor deposition or atomic layer deposition processes, and a second gate conductive layer 405 covered by the second gate dielectric layer 4032 to form a stack 40, and the first gate dielectric layer 4031 and the second gate dielectric layer 4032 together constitute the gate dielectric layer 403.
[0116] In the embodiment of the present application, by setting the gate conductive layer in the stack as a shielding gate, since the first gate conductive layer 404 in the stack 40 is connected to the gate, and the top of the stack 40, the second gate conductive layer 405 and the second-type semiconductor layer 402 in the stack are all connected to the source, when the device is in a reverse flow state, the voltage drop acting on the source causes the secondary field effect transistor to be turned on, thereby converting the bipolar conduction of electrons and holes into unipolar conduction of electrons during the reverse conduction process, thereby suppressing the injection of holes and improving the reverse recovery characteristics of the device. In addition, a depletion layer can be formed between the first-type semiconductor column 201 and the second-type semiconductor column 202 to deplete each other, thereby increasing the breakdown voltage of the device and improving the reliability and electrical properties of the semiconductor device.
[0117] In some embodiments, after forming the second semiconductor layer on the top surface of the first semiconductor layer, the following step is further included: S14.
[0118] S14: forming a third semiconductor layer on the top surface of the second semiconductor layer, wherein the third semiconductor layer circumferentially surrounds the stack; wherein the third semiconductor layer comprises a first-type doping region and a second-type doping region sequentially distributed along a first direction, and the second-type doping region is located between the first-type doping region and the stack.
[0119] As an example, see Figure 2 , the third semiconductor layer can be formed on the top surface of the second semiconductor layer by using, but not limited to, ion implantation. The first-type doping region 501 is a P-type doping region, and the second-type doping region 502 is an N-type doping region. Specifically, in this embodiment, the doping concentrations of the first-type doping region 501 and the second-type doping region 502 are both greater than the doping concentration of the second semiconductor layer. The second-type doping region 502 can enable the device to flow between the second-type doping regions 502 on both sides of the gate dielectric layer 403 of the stack 40 when the device is in the on state, thereby forming an on-current.
[0120] In this embodiment, by setting the first type doping region 501 and the second type doping region 502, the second type doping region 502 can enable the device to flow between the second type doping regions 502 on both sides of the gate dielectric layer 403 of the stack 40 when the device is in the on state, thereby forming an on-current.
[0121] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0122] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor device, characterized in that: include: substrate; A first semiconductor layer, located on the substrate, comprises first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate; A second semiconductor layer, located on a top surface of the first semiconductor layer; A stack, penetrating the second semiconductor layer along a second direction perpendicular to the substrate and extending to the interior of the second-type semiconductor column; the stack comprises a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; The second-type semiconductor layer is buried in the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart and distributed along the second direction.
2. The semiconductor device according to claim 1, wherein: The gate dielectric layer circumferentially covers the first gate conductive layer and covers the top surface and the bottom surface of the first gate conductive layer; and The gate dielectric layer circumferentially wraps around the second gate conductive layer and covers the top surface and the bottom surface of the second gate conductive layer.
3. The semiconductor device according to claim 1, wherein: The second-type semiconductor pillar circumferentially surrounds the stack and covers the bottom surface of the stack.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The top surface of the second semiconductor layer is lower than the top surface of the stack; the semiconductor device further comprises: a third semiconductor layer circumferentially surrounding the stack; The third semiconductor layer includes a first-type doping region and a second-type doping region sequentially distributed along the first direction, and the second-type doping region is located between the first-type doping region and the stacked layer.
5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The first type is P type, and the second type is N type; or The first type is N type, and the second type is P type.
6. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 5.
7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises first-type semiconductor columns and second-type semiconductor columns alternately distributed along a first direction parallel to the substrate; A second semiconductor layer is formed on the top surface of the first semiconductor layer, and a stack is formed along a second direction perpendicular to the substrate, the stack penetrates the second semiconductor layer and extends to the inside of the second-type semiconductor column; the stack includes a first-type semiconductor layer, a second-type semiconductor layer, and a gate dielectric layer sequentially distributed along a direction away from the substrate; wherein the second-type semiconductor layer is buried inside the first-type semiconductor layer, and the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along the second direction.
8. The method for preparing a semiconductor device according to claim 7, characterized in that: The second semiconductor layer is formed on the top surface of the first semiconductor layer, and a stack is formed along a second direction perpendicular to the substrate, comprising: forming a trench in the first semiconductor layer; forming the first-type semiconductor layer in the trench, and forming a second semiconductor layer on a top surface of the first semiconductor layer; forming the second-type semiconductor layer in the first-type semiconductor layer, wherein the second-type semiconductor layer is buried inside the first-type semiconductor layer; A gate dielectric layer is formed on the top surface of the second-type semiconductor layer to form the stack, wherein the top surface of the second semiconductor layer is lower than the top surface of the stack, wherein the gate dielectric layer is coated with a first gate conductive layer and a second gate conductive layer spaced apart along the second direction, the gate dielectric layer circumferentially coats the first gate conductive layer and covers the top and bottom surfaces of the first gate conductive layer; and the gate dielectric layer circumferentially coats the second gate conductive layer and covers the top and bottom surfaces of the second gate conductive layer.
9. The method for preparing a semiconductor device according to claim 7, characterized in that: The second-type semiconductor pillar circumferentially surrounds the stack and covers the bottom surface of the stack.
10. The method for preparing a semiconductor device according to any one of claims 7 to 9, characterized in that: After forming the second semiconductor layer on the top surface of the first semiconductor layer, the method further includes: A third semiconductor layer is formed on the top surface of the second semiconductor layer, and the third semiconductor layer circumferentially surrounds the stack; wherein the third semiconductor layer includes a first-type doping region and a second-type doping region sequentially distributed along the first direction, and the second-type doping region is located between the first-type doping region and the stack.