Silicon carbide MOSFET structure of heterogeneous integrated N well and preparation method of silicon carbide MOSFET structure

Abstract

The invention relates to a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure of a heterogeneous integrated N trap and a preparation method thereof, the structure comprises drain electrode metal, an N substrate, N-type silicon carbide and source electrode metal which are sequentially laminated from bottom to top, a polysilicon gate is arranged between the source electrode metal and the N-type silicon carbide, gate oxide is formed between the polysilicon gate and the N-type silicon carbide, N trap grooves are formed in two sides of the polysilicon gate, and the N trap grooves are formed in two sides of the polysilicon gate. The N well groove is formed in the surface of the N-type silicon carbide, the N well groove is filled with N-type polycrystalline silicon, the surface of the N-type polycrystalline silicon is in contact with gate oxide and source electrode metal, a P + region is formed on the surface of the N-type silicon carbide, the N well groove is embedded in the P + region, one side of the N well groove is in contact with the N-type silicon carbide, and the N-type polycrystalline silicon and the N-type silicon carbide form a heterojunction structure. According to the invention, the on and off of the MOSFET device are regulated and controlled by using a method of controlling the height of the heterojunction barrier through the grid electrode, a channel in a traditional plane grid structure can be greatly shortened or even completely removed, and the cell miniaturization of the silicon carbide MOSFET device is realized.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductors, and in particular to a heterogeneously integrated N-well silicon carbide MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon carbide (Si li con Carbide) high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more harsh environments. Therefore, they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace and other fields.

[0003] For silicon carbide MOSFET devices, the current main development direction is to continuously reduce the specific on-resistance by reducing the cell size and improving the process. However, due to the limitations of the characteristic process of power devices, the technical difficulty and cost of cell size miniaturization and advanced process development are relatively high. At present, there are two technical routes for silicon carbide MOSFET devices in the world: planar gate and trench gate. Planar gate silicon carbide MOSFET devices have prominent bottlenecks in cell miniaturization, but due to their high reliability, they are still the mainstream silicon carbide power switching devices on the market; trench gate silicon carbide MOSFET devices have great advantages in achieving cell size miniaturization, but due to the high gate oxide electric field strength at the bottom of the trench, it poses a serious threat to the reliability of the device, and its current market share is lower than that of planar gate silicon carbide MOSFET devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a heterogeneous integrated N-well silicon carbide MOSFET structure and a preparation method thereof in view of the above shortcomings, so as to solve the technical difficulties in miniaturization of existing planar gate silicon carbide MOSFET device cells.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A heterogeneous integrated N-well silicon carbide MOSFET structure includes a drain metal, an N substrate, an N-type silicon carbide and a source metal stacked sequentially from bottom to top.

[0007] A polysilicon gate is arranged between the source metal and the N-type silicon carbide, and a gate oxide is formed between the polysilicon gate and the N-type silicon carbide.

[0008] N-well grooves are arranged on both sides of the polysilicon gate. The N-well grooves are opened on the surface of N-type silicon carbide. The N-well grooves are filled with N-type polysilicon. The surface of the N-type polysilicon is in contact with the gate oxide and the source metal.

[0009] A P+ region is formed on the surface of the N-type silicon carbide, the N-well groove is embedded in the P+ region, one side of the N-well groove is in contact with the N-type silicon carbide, and the N-type polysilicon and the N-type silicon carbide form a heterojunction structure.

[0010] Furthermore, the N-type silicon carbide includes an N-type drift layer and a carrier storage layer arranged in sequence from bottom to top, and the N-well groove and the P+ region are both located in the carrier storage layer.

[0011] Furthermore, a P-well region is formed on the carrier storage layer, and the P-well region covers the outside of the N-well groove and the P+ region. A gap is provided between the surface of the P-well region and the surface of the carrier storage layer, and the gap forms a channel in which the N-type polysilicon contacts the carrier storage layer.

[0012] Furthermore, a gate dielectric is formed between the polysilicon gate and the gate oxide.

[0013] Furthermore, an interlayer dielectric is formed between the polysilicon gate and the source metal.

[0014] A method for preparing a heterogeneously integrated N-well silicon carbide MOSFET comprises the following steps:

[0015] Step S1, preparing an N substrate and N-type silicon carbide;

[0016] Step S2, implanting carrier storage region ions and P+ ions into the N-type silicon carbide, and performing high temperature annealing and activation to form a carrier storage layer and a P+ region on the N-type silicon carbide;

[0017] Step S3, etching the surface of the N-type silicon carbide to form an N-well groove, and filling the N-well groove with N-type polysilicon;

[0018] Step S4, thermally oxidizing the N-type silicon carbide to form a gate oxide;

[0019] Step S5, depositing a polysilicon gate and an interlayer dielectric on the gate oxide to form a MOS structure;

[0020] Step S6, depositing source metal in the region between adjacent polysilicon gates, and making the source metal contact with the N-type polysilicon;

[0021] Step S7, gate opening;

[0022] Step S8, depositing a thick source metal layer on the interlayer dielectric to form a source structure;

[0023] Step S9: forming a drain metal below the N substrate to form a drain structure.

[0024] Furthermore, in the step S2, before high temperature annealing and activation, P-well ions are implanted on the N-type silicon carbide to form a P-well region on the N-type silicon carbide after high temperature annealing and activation.

[0025] After adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0026] (1) The present invention uses N-type polysilicon to form a source electrode, and N-type polysilicon and N-type silicon carbide form a heterojunction. The heterojunction makes the device in a normally-off state when no gate voltage is applied. The structure uses a method of controlling the height of the heterojunction barrier by the gate to achieve the on and off control of the silicon carbide MOSFET device, which can shorten or omit the channel in the traditional planar gate structure, and realize the miniaturization of the silicon carbide MOSFET device cell;

[0027] (2) While retaining the channel, the inversion channel is replaced by an N-type accumulation channel, which greatly improves the channel mobility and significantly reduces the specific on-resistance of the silicon carbide MOSFET device;

[0028] (3) The present invention can omit the P-well as required. In the absence of the P-well region, the P+ region completely wraps the bottom of the N-well groove to achieve shielding protection. At the same time, the P+ region completely surrounds the N-well, which can greatly reduce the turn-on of the parasitic NPN transistor and improve the reliability of the device.

[0029] (4) The heterojunction formed by N-type polysilicon and N-type silicon carbide is reverse biased when the device is forward blocked, and can be combined with the shielding protection of P-well / P+ to reduce the leakage current of the device. When the device is reverse-conducting, the forward conduction voltage drop of the heterojunction is lower, which can greatly reduce the reverse conduction loss of the silicon carbide MOSFET device and inhibit the bipolar degradation caused by the conduction of the body diode. At the same time, the heterojunction stores less excess carriers, and the reverse recovery characteristics of the silicon carbide MOSFET device are better.

[0030] (5) The manufacturing process of the silicon carbide MOSFET device of the present invention is largely compatible with the manufacturing process of the conventional planar gate silicon carbide MOSFET device, and only the steps of N-well etching and polysilicon filling in the N-well need to be adjusted.

[0031] The present invention is described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a structural diagram of a silicon carbide MOSFET device according to an embodiment of the present invention.

[0033] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0034] 1. Drain metal; 2. N substrate; 3. N-type silicon carbide; 3a. N-type drift layer; 3b. Carrier storage layer; 31. N-well groove; 32. P+ region; 33. P-well region; 34. Channel; 4. Source metal; 5. Polysilicon gate; 51. Gate oxide; 52. Gate dielectric; 53. Interlayer dielectric; 6. N-type polysilicon; DETAILED DESCRIPTION

[0035] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0036] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", "clockwise" and "counterclockwise" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0037] Embodiment 1:

[0038] like Figure 1 As shown, a heterogeneous integrated N-well silicon carbide MOSFET structure includes a drain metal 1, an N substrate 2, an N-type silicon carbide 3 and a source metal 4 stacked from bottom to top.

[0039] A polysilicon gate 5 is formed between the N-type silicon carbide 3 and the source metal 4 , a gate oxide 51 is formed between the polysilicon gate 5 and the N-type silicon carbide 3 (a gate dielectric 52 may be deposited between the gate oxide 51 and the polysilicon gate 5 , or may be omitted), and an interlayer dielectric 53 is formed between the polysilicon gate 5 and the source metal 4 .

[0040] The N-type silicon carbide 3 includes an N-type drift layer 3a and a carrier storage layer 3b arranged sequentially from bottom to top. An N-well groove 31 is etched on the N-type silicon carbide 3. The N-well groove 31 is located below the left / right side of the polysilicon gate 5. The N-well groove 31 is filled with N-type polysilicon 6. The N-type polysilicon 6 is in contact with the N-type silicon carbide 3 to form a heterojunction structure.

[0041] A P+ region 32 and a P-well region 33 are also formed on the N-type silicon carbide 3 . The P+ region 32 and the P-well region 33 are sequentially coated on the outside of the N-well groove 31 to form a shielding protection for the N-type polysilicon 6 .

[0042] In order to solve the technical difficulties in cell miniaturization of existing planar gate silicon carbide MOSFET devices, in this embodiment, an N-well groove 31 is etched on the N-type silicon carbide 3, and N-type polysilicon 6 is filled in the N-well groove 31 as a source. A P+ region 32 and a P-well region 33 can also be set to surround the N-type polysilicon 6 to form a shielding protection. The upper surface of the P-well region 33 is spaced a certain distance from the upper surface of the N-type silicon carbide 3 to form a channel of the silicon carbide MOSFET device. The N-type polysilicon 6 and the N-type silicon carbide 3 form a heterojunction, so that the device is in a normally-off state when no gate voltage is applied. The rest of the structure is consistent with the traditional planar gate.

[0043] The above structure utilizes the method of controlling the height of the heterojunction barrier by the gate to realize the on and off control of the MOSFET device, which can significantly shorten or eliminate the channel in the traditional planar gate structure, and can use an accumulation channel to replace the inversion channel in the traditional structure, thereby improving the mobility of the channel and reducing the device's specific on-resistance.

[0044] The heterojunction formed by the N-type polysilicon 6 and the N-type silicon carbide 3 has a certain barrier height, so that the device is in a normally-off state when no gate voltage is applied;

[0045] When a positive voltage exceeding the threshold voltage is applied to the gate, the barrier height of the heterojunction decreases, the silicon carbide MOSFET device is turned on, and the electrons in the N-type polysilicon 6 pass through the channel 34, the carrier storage layer 3b, the N-type drift layer 3a and the N substrate 2 and enter the drain metal 1;

[0046] When the gate voltage is lower than the device threshold voltage, the SiC MOSFET device is turned off;

[0047] When a high voltage is applied to the drain of the device, the PN junction composed of the P-well region 33, the P+ region 32 and the N-type drift layer 3a is reverse biased to withstand the blocking voltage, and the reverse biased heterojunction can also reduce the leakage current of the device;

[0048] When the drain and source of the device are subjected to reverse voltage, the heterojunction formed by the N-type polysilicon 6 and the N-type silicon carbide 3 is forward-conducted, and the device conducts reverse current. Since the forward conduction voltage drop of the heterojunction is low, the reverse conduction voltage drop of the silicon carbide MOSFET device is low, which can simultaneously suppress the bipolar degradation caused by the conduction of the body diode; since the heterojunction formed by the N-type polysilicon 6 and the N-type silicon carbide 3 is unipolar (only electrons work as carriers), the reverse recovery characteristics of the device are better.

[0049] Specifically, the P+ region 32 , the P-well region 33 and the N-well groove 31 are all located in the carrier storage layer 3 b .

[0050] A method for preparing a heterogeneously integrated N-well silicon carbide MOSFET comprises the following steps:

[0051] 1. Silicon carbide wafer preparation, that is, forming N-type silicon carbide 3 on the surface of N substrate 2;

[0052] 2. P-well ions, P+ ions and carrier storage layer ions are implanted on the N-type silicon carbide 3, and then high-temperature annealing and activation are performed to form a carrier storage layer 3b, a P-well region 33 and a P+ region 32 on the N-type silicon carbide;

[0053] 3. Etching an N-well groove 31 on the N-type silicon carbide 3, and filling the N-well groove 31 with N-type polysilicon 6;

[0054] 4. Forming a thin gate oxide layer 51 on the N-type silicon carbide 3 by thermal oxidation;

[0055] 5. Deposit a high-k dielectric such as Al2O3 on the gate oxide 51 to form a second gate dielectric 52 (this layer and this step can be omitted);

[0056] 6. Depositing a polysilicon gate 5 and an interlayer dielectric 53 on the gate oxide 51 or the gate dielectric 52 to form a MOS structure;

[0057] 7. Deposit source metal between adjacent polysilicon gates 5, and make the source metal 4 contact with the N-type polysilicon 6;

[0058] 8. Gate opening;

[0059] 9. Deposit a thick source metal 4 on the polysilicon gate 5 to form a source structure;

[0060] 10. Form surface protection structures such as TEOS and PI;

[0061] 11. Thinning the back side of N substrate 2;

[0062] 12. A drain metal 1 is formed on the back side of the N substrate 2 to form a drain structure.

[0063] Embodiment 2:

[0064] In this embodiment, based on the first embodiment, the P-well region 33 is omitted.

[0065] In this embodiment, the process step of implanting P-well ions on the N-type silicon carbide 3 is omitted, so that the P-well region 33 is omitted.

[0066] In the case where the channel does not need to be retained, the P-well region 33 can be removed at the same time to reduce the mask and one ion implantation process. In this case, the P+ region 32 is directly used to form a shielding protection for the N-type polysilicon 6 in the N-well groove 31. Since the P+ region 32 forms a full surrounding protection for the bottom of the N-type polysilicon 6, the ion concentration of the P+ region 32 is very high, and the parasitic NPN transistor inside the silicon carbide MOSFET device will be greatly suppressed, thereby improving the reliability of the device.

[0067] The above is an example of the best implementation of the present invention, and the parts not described in detail are common knowledge of ordinary technicians in the field. The protection scope of the present invention shall be based on the content of the claims, and any equivalent transformation based on the technical enlightenment of the present invention is also within the protection scope of the present invention.

Claims

1. A heterogeneous integrated N-well silicon carbide MOSFET structure, characterized in that: The invention comprises a drain metal (1), an N substrate (2), an N-type silicon carbide (3) and a source metal (4) which are stacked in sequence from bottom to top. A polysilicon gate (5) is arranged between the source metal (4) and the N-type silicon carbide (3), and a gate oxide (51) is formed between the polysilicon gate (5) and the N-type silicon carbide (3). N-well grooves (31) are arranged on both sides of the polysilicon gate (5), the N-well grooves (31) are opened on the surface of the N-type silicon carbide (3), the N-well grooves (31) are filled with N-type polysilicon (6), and the surface of the N-type polysilicon (6) is in contact with the gate oxide (51) and the source metal (4). A P+ region (32) is formed on the surface of the N-type silicon carbide (3), the N-well groove (31) is embedded in the P+ region (32), one side of the N-well groove (31) is in contact with the N-type silicon carbide (3), and the N-type polycrystalline silicon (6) and the N-type silicon carbide (3) form a heterojunction structure.

2. The heterogeneous integrated N-well silicon carbide MOSFET structure according to claim 1, characterized in that: The N-type silicon carbide (3) comprises an N-type drift layer (3a) and a carrier storage layer (3b) arranged in sequence from bottom to top, and the N-well groove (31) and the P+ region (32) are both located in the carrier storage layer (3b).

3. The heterogeneous integrated N-well silicon carbide MOSFET structure according to claim 1 or 2, characterized in that: A P-well region (33) is formed on the carrier storage layer (3b), the P-well region (33) covers the outside of the N-well groove (31) and the P+ region (32), a gap is provided between the surface of the P-well region (33) and the surface of the carrier storage layer (3b), and the gap forms a channel (34) in which the N-type polysilicon (6) contacts the carrier storage layer (3b).

4. The heterogeneous integrated N-well silicon carbide MOSFET structure according to claim 1, characterized in that: A gate dielectric (52) is formed between the polysilicon gate (5) and the gate oxide (51).

5. The heterogeneous integrated N-well silicon carbide MOSFET structure according to claim 1, characterized in that: An interlayer dielectric (53) is formed between the polysilicon gate (5) and the source metal (4).

6. A method for preparing a heterogeneously integrated N-well silicon carbide MOSFET, characterized in that: The following steps are involved: Step S1, preparing an N substrate (2) and N-type silicon carbide (3); Step S2, implanting carrier storage region ions and P+ ions into the N-type silicon carbide (3), and performing high temperature annealing and activation to form a carrier storage layer (3b) and a P+ region (32) on the N-type silicon carbide; Step S3, etching the surface of the N-type silicon carbide (3) to form an N-well groove (31), and filling the N-type polysilicon (6) in the N-well groove (31); Step S4, forming a gate oxide (51) by thermal oxidation on the N-type silicon carbide (3); Step S5, depositing a polysilicon gate (5) and an interlayer dielectric (53) on the gate oxide (51) to form a MOS structure; Step S6, depositing a source metal (4) in a region between adjacent polysilicon gates (5), and making the source metal (4) contact the N-type polysilicon (6); Step S7, gate opening; Step S8, depositing a thick source metal layer (4) on the interlayer dielectric (53) to form a source structure; Step S9: forming a drain metal (1) below the N substrate (2) to form a drain structure.

7. The method for preparing a heterogeneously integrated N-well silicon carbide MOSFET according to claim 6, characterized in that: In the step S2, before high temperature annealing and activation, P well ions are implanted on the N type silicon carbide (3), so as to form a P well region (33) on the N type silicon carbide (3) after high temperature annealing and activation.

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