Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a drift region which extends into a semiconductor layer from a first surface of the semiconductor layer; the well regions extend into the drift region from the first surface of the semiconductor layer and are positioned on two sides of the gate structure; the drift region between the adjacent well regions is a JEFT region; the source region extends into the well region from the upper surface of the well region; the first insulation structure is located in the well region, the first insulation structure at least comprises a first part, and the first part is located between the source region and the lower surface of the well region and extends into the JEFT region; the first insulation structure is insulated from the drift region; the second insulation structure is located in the JFET region, the second insulation structure and the first insulation structures on the two sides are arranged at intervals, the second insulation structure comprises a second pseudo grid electrode and a second pseudo grid dielectric layer, and the second pseudo grid dielectric layer surrounds the second pseudo grid electrode, so that starting of a parasitic transistor is restrained, and the avalanche tolerance capacity of the device is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Planar power MOSFET devices are a widely used power semiconductor device. Their most common application is as a power switch to control power conversion, usually to control and drive inductive loads, so they experience high-frequency switching actions during operation. When the device is in the off state, the energy stored in the unclamped load inductor driven by the device will be released instantly, causing an avalanche phenomenon inside the device, generating instantaneous high voltage and high current. Generally speaking, the device itself has a certain inductive energy tolerance, but when the inductive energy exceeds the range that the device can withstand, it will cause the device to fail and eventually burn out. The avalanche tolerance of a power device is a measure of the maximum energy that the device can withstand when it is subjected to overshoot voltage or current and works in an avalanche state. In order to increase the working reliability level of the device, the avalanche tolerance of the device needs to be optimized.

[0003] like Figure 1 As shown in FIG. 1 , a parasitic bipolar NPN transistor exists in a conventional planar power MOSFET. The parasitic transistor is the main factor affecting the avalanche tolerance of the device. When the device undergoes avalanche breakdown and generates a large instantaneous current, the hole current will flow along the N+ source region 105 to the well region 103. Rb refers to the resistor existing in the N+ source region 105. When the current flowing through the resistor is large enough, the forward voltage drop generated is greater than the positive bias voltage between the base region and the emitter region of the parasitic transistor, and the parasitic transistor is turned on, causing current concentration and secondary breakdown, and ultimately leading to device failure.

[0004] In order to reduce the impact of turning on the parasitic transistor, the method usually adopted is to minimize the resistance of the parasitic resistor Rb. The typical approach is to increase the diffusion concentration of the P+ region 104, so that the resistance of Rb can be reduced by lateral diffusion of the P+ region 104, or by adjusting the direction of the N+ source region 105 to change to longitudinal diffusion, which can also reduce the length of the Rb resistance area, thereby reducing the resistance.

[0005] Currently known methods for improving the avalanche tolerance of devices, whether it is the improvement of the above-mentioned design structure or through process optimization, most of them are centered on reducing the resistance of the parasitic resistor Rb to optimize the avalanche tolerance characteristics of the device. This method can optimize the avalanche tolerance of the device to a certain extent, but because the resistance of the resistance area Rb always exists, it is impossible to completely eliminate the impact of the existence of this area on the avalanche tolerance reliability of the device. Therefore, when the device is turned off under harsh conditions, excessive current will still cause the parasitic resistor Rb to produce a positive bias greater than 0.7V, causing the parasitic transistor to turn on. Therefore, the avalanche tolerance reliability of the device will inevitably be limited, and it can only be said that the avalanche tolerance of the device has been improved to a certain extent. It can be seen that this traditional optimization method always has certain limitations. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can suppress the turn-on of a parasitic transistor and achieve the effect of enhancing the avalanche withstand capability of the device.

[0007] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor layer having a first surface and a second surface opposite to each other, a drift region being provided in the semiconductor layer, the drift region extending from the first surface of the semiconductor layer into the semiconductor layer, the semiconductor layer and the drift region being of a first doping type; A gate structure located on the first surface of the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate; extending from the first surface of the semiconductor layer to a well region in the drift region, the well region being located on both sides of the gate structure; a drift region located between adjacent well regions being a JFET region; the well region being of a second doping type, the second doping type being opposite to the first doping type; extending from the upper surface of the well region to a source region in the well region, the source region being of a first doping type; a first insulating structure located in the well region, the first insulating structure comprising at least a first portion, the first portion being located between the source region and a lower surface of the well region and extending into the JFET region; the first insulating structure being insulated from the drift region; a second insulating structure located in the JFET region, the second insulating structure being spaced apart from the first insulating structure on both sides, the second insulating structure comprising a second dummy gate and a second dummy gate dielectric layer, the second dummy gate dielectric layer surrounding the second dummy gate.

[0008] Preferably, the first insulating structure also includes a second part, wherein: one side of the first part extends into the JFET region in the direction of the gate structure; the second part is located on a side of the source region away from the gate structure, extends from the upper surface of the well region into the well region and is connected to the first part.

[0009] Preferably, it also includes: an ohmic contact region extending from the upper surface of the well region to the well region, the ohmic contact region is located on a side of the source region away from the gate structure, and the ohmic contact region is of the second doping type; a source metal layer located on the first surface of the semiconductor layer, the source metal layer is in contact with the ohmic contact region and the source region respectively.

[0010] Preferably, the second portion of the first insulating structure is located between the ohmic contact region and the source region; the other side of the first portion extends in a direction away from the gate structure to between the ohmic contact region and a lower surface of the well region.

[0011] Preferably, the first insulating structure is made of an insulating material; or, the first insulating structure includes a first dummy gate and a first dummy gate dielectric layer, and the first dummy gate dielectric layer surrounds the first dummy gate.

[0012] Preferably, along the direction of the thickness of the semiconductor layer, the distance between the lower surface of the first insulating structure and the lower surface of the well region is greater than or equal to 0.5 micrometers.

[0013] Preferably, the second insulating structure includes a first part and a second part, wherein: the first part of the second insulating structure extends toward the first insulating structures on both sides and is spaced apart from the first insulating structure; the second part of the second insulating structure extends from the upper surface of the JFET region to the JFET region and is connected to the first part of the second insulating structure.

[0014] Preferably, the first portion of the first insulating structure is aligned with the first portion of the second insulating structure in a thickness direction of the semiconductor layer.

[0015] Preferably, a distance between the first portion of the first insulating structure and the first portion of the second insulating structure in their extension directions is no more than 50 nanometers.

[0016] Preferably, it also includes a drain metal layer located on the second surface of the semiconductor layer.

[0017] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: A well region is formed in a drift region of a semiconductor layer, the drift region extends from a first surface of the semiconductor layer into the semiconductor layer, the well region extends from the first surface of the semiconductor layer into the drift region, and the drift region between adjacent well regions is a JFET region; a source region is formed extending from an upper surface of the well region into the well region; a first insulating structure is formed in the well region, the first insulating structure at least includes a first portion, the first portion is located between the source region and a lower surface of the well region and extends into the JFET region; the first insulating structure is insulated from the drift region; a second insulating structure is formed in the JFET region, the second insulating structure is spaced from the first insulating structure, the second insulating structure includes a second dummy gate and a second dummy gate dielectric layer, the second dummy gate dielectric layer surrounds the second dummy gate; a gate structure is formed on the first surface of the semiconductor, the gate structure includes a stacked gate dielectric layer and a gate, and the gate structure covers the JFET region; wherein the semiconductor layer, the drift region and the source region are of a first doping type, the well region is of a second doping type, and the second doping type is opposite to the first doping type.

[0018] Preferably, the process of forming the first insulating structure includes: etching the well region to form a first groove, the first groove extending from the upper surface of the well region to the well region; forming a barrier layer on the inner side wall of the first groove; etching the bottom of the first groove by an isotropic etching process to form a second groove at the bottom of the first groove, the second groove is located between the source region and the lower surface of the well region, and one side of the second groove extends toward the gate structure to the JFET region; removing the barrier layer in the first groove, forming a first dielectric layer on the inner walls of the first groove and the second groove, and filling the first groove and the second groove to form a first pseudo gate, the upper surface of the first pseudo gate is lower than the top of the first groove; filling the second dielectric layer in the first groove, the second dielectric layer is connected to the first dielectric layer to form a first pseudo gate dielectric layer.

[0019] Preferably, the process of forming the first insulating structure includes: etching the well region to form a first trench, the first trench extending from the upper surface of the well region into the well region; forming a barrier layer on the inner side wall of the first trench; etching the bottom of the first trench using an isotropic etching process to form a second trench at the bottom of the first trench, the second trench being located between the source region and the lower surface of the well region, and one side of the second trench extending toward the gate structure into the JFET region; removing the barrier layer in the first trench, and filling the first trench and the second trench with insulating material to form the first insulating structure.

[0020] Preferably, the process of forming the second insulating structure includes: etching the JFET region to form a third trench; forming a barrier layer on the inner side wall of the third trench; etching the bottom of the third trench using an isotropic etching process to form a fourth trench at the bottom of the third trench, with both sides of the fourth trench extending toward the first insulating structure and beyond the third trench; removing the barrier layer in the third trench, forming a third dielectric layer on the inner walls of the third trench and the fourth trench, and filling the third trench and the fourth trench to form a second pseudo gate, with the upper surface of the second pseudo gate being lower than the top of the third trench; filling the third trench with a fourth dielectric layer, with the fourth dielectric layer connected to the third dielectric layer to form a second pseudo gate dielectric layer.

[0021] The semiconductor device provided by the present invention adopts a first insulating structure to occupy the P-well area under the N+ source area of ​​the traditional device structure, eliminating the most important area of ​​the parasitic resistance Rb in the traditional structure, thereby being able to effectively suppress the turning-on of the parasitic transistor, and thus improving the avalanche tolerance of the device; further, a second insulating structure is arranged in the JFET area, the second insulating structure is spaced apart from the first insulating structure and the second insulating structure adopts a pseudo-gate structure, when an avalanche occurs, it is difficult for holes to flow upward in the spaced area between the second insulating structure and the first insulating structure, which can generally suppress the possibility of holes flowing under the source area and retain the current conduction capability, thereby ensuring the normal conduction of the semiconductor device.

[0022] In a preferred embodiment, the first insulating structure also adopts a pseudo gate structure, so that the interval region between the second insulating structure and the first insulating structure forms an inversion layer, which can completely block the upward flow of holes. At the same time, when the device is in the on state, the interval region is actually the inversion layer channel region, which does not affect the normal downward flow of electrons.

[0023] The manufacturing method of the semiconductor device provided by the present invention involves processes that are all commonly used in semiconductor manufacturing processes, has a relatively low process difficulty, and is conducive to promotion and application in actual production. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram showing the structure of a conventional planar power MOSFET device is shown;

[0026] Figure 2 A schematic structural diagram of a semiconductor device provided according to a first embodiment of the present invention is shown;

[0027] Figure 3A schematic structural diagram of a semiconductor device provided according to a second embodiment of the present invention is shown;

[0028] Figures 4 to 11 sectional views showing various stages of the method for manufacturing a semiconductor device according to the first embodiment and the second embodiment of the present invention;

[0029] Fig.12 An equivalent circuit diagram of a semiconductor device provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same structure or region is represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and technology of the device, so as to more clearly understand the technical concept of the present invention. However, as those skilled in the art can understand, the present invention can be implemented without following these specific details.

[0031] In addition, it should be noted that in this article, relational terms such as "first", "second", "third", "fourth" and the like are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship, order or quantity between these entities or operations.

[0032] Figure 2 FIG. 2 shows a schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention. Figure 2 As shown, the semiconductor device provided by the first embodiment of the present invention includes: a semiconductor layer, a well region 103, a source region 104, an ohmic contact region 105, a source metal layer 106, a gate structure, a first insulating structure 108, a second insulating structure 114, a JET region 109, and a drain metal layer 110.

[0033] The semiconductor layer includes a stacked substrate 101 and a drift region 102, the lower surface of the drift region 102 faces the substrate 101, the upper surface of the drift region 102 serves as the first surface of the semiconductor layer, the upper surface of the substrate 101, i.e., the front side, faces the drift region 102, and the back side, i.e., the lower surface, of the substrate 101 serves as the second surface of the semiconductor layer. For the convenience of description, the structures included in the semiconductor device, such as the well region 103, the JEF region 109, the first insulating structure 108, and the second insulating structure 114, are referred to as the lower surface facing the substrate 101, and the upper surface away from the substrate 101.

[0034] The drift region 102 extends from the first surface of the semiconductor layer into the semiconductor layer. In a specific implementation process, the drift region 102 can be formed on the substrate 101 by an epitaxial process. The substrate 101 can be a silicon substrate, a silicon carbide substrate, or the like, especially a semiconductor substrate that can be used in a power semiconductor device; the substrate 101 and the drift region 102 have the same doping type, and generally the doping concentration of the substrate 101 is greater than the doping concentration of the drift region 102.

[0035] The gate structure includes a stacked gate dielectric layer and a gate 107, wherein the gate dielectric layer is located on the upper surface of the drift region 102, and can specifically adopt a gate dielectric material commonly used in existing semiconductor devices, such as silicon dioxide, or a stack of silicon dioxide and silicon nitride. The gate 107 can specifically be a polysilicon gate. In addition, an insulating dielectric layer is also covered above and on the sides of the gate 107 to play an isolation role.

[0036] The well region 103 is located on both sides of the gate structure and extends from the first surface of the semiconductor layer to the drift region 102. The well region 103 is of the second doping type, which is opposite to the first doping type. For example, for an N-type drift region 102, the well region 103 is a P-well. The drift region 102 located between the two well regions 103 is the JEFT region 109; it is not difficult to understand that the JEFT region 109 is located below the gate structure.

[0037] The source region 104 is located in the well region 103, extending from the first surface of the semiconductor layer to the well region 103, the source region 104 is of the first doping type, and the source region 104 is connected to the source electrode. Figure 2 The source metal layer 106 shown in FIG. 1 covers the upper surface of the well region 103 , but the present invention is not limited thereto.

[0038] The ohmic contact region 105 extends from the first surface of the semiconductor layer to the well region 103. The ohmic contact region 105 is of the second doping type. The ohmic contact region 105 forms an ohmic contact with the source. In this embodiment, the source region 104 and the ohmic contact region 105 located in the same well region 103 are arranged at intervals, and the ohmic contact region 105 is relatively farther away from the gate structure.

[0039] The substrate 101 is electrically connected to the drain. In a specific implementation, the drain can be Figure 2 Shown is a drain metal layer 110 covering the back side of the substrate 101 .

[0040] The first insulating structure 108 is located in the well region 103, and at least a portion of the first insulating structure 108 is located between the lower surface of the source region 104 and the lower surface of the well region 103. The first insulating structure 108 is insulated from the drift region 102, that is, at least the peripheral area of ​​the first insulating structure 108 is made of insulating material. In this embodiment, the entire first insulating structure 108 is made of insulating material, such as insulating material such as silicon oxide, silicon nitride, or a stack of insulating materials.

[0041] refer to Figure 1 and Figure 2 Compared with the conventional planar power MOSFET device, in the semiconductor device provided in the first embodiment of the present invention, part of the well region 103 located below the source region 104 is occupied by the first insulating structure 108, which eliminates the Rb parasitic resistance region corresponding to the position in the conventional planar power MOSFET device, breaking the existence of the parasitic transistor, such as Fig.12 As shown in the equivalent circuit diagram, the probability of the parasitic transistor being turned on is zero, which greatly improves the avalanche tolerance and reliability level of the device.

[0042] And it should be noted that in Figure 2 In the illustrated embodiment, there is a gap between the first insulating structure 108 and the lower surface of the source region 104 , but the present application is not limited thereto. In a preferred embodiment, the first insulating structure 108 is in contact with the lower surface of the source region 104 , which can better suppress the parasitic resistance under the source region 104 .

[0043] To ensure the flow of holes, there should be sufficient passage between the ohmic contact region 105 and the well region 103. In one embodiment, Figure 2 As shown, in the first direction, the distance H between the lower surface of the first insulating structure 108 and the lower surface of the well region 103 is preferably controlled to be above 0.5 μm, that is, H ≥ 0.5 μm, so as to ensure that there is sufficient doping area in the bottom area of ​​the well region 103 to ensure the flow of holes and realize the original voltage resistance of the device.

[0044] Further references Figure 2 The first insulating structure 108 may specifically include a first part and a second part, wherein the first part is located between the lower surface of the source region 104 and the lower surface of the well region 103, and the second part is located between the source region 104 and the ohmic contact region 105. The second part can be regarded as extending from the upper surface of the well region 103 toward the substrate 101, that is, the second part extends along the first direction to be flush with the lower surface of the source region 104 or beyond the lower surface of the source region 104; the first part is connected to the bottom of the second part, the first part is located below the source region 105, and one side of the first part extends along the second direction toward the gate structure to exceed the well region 103 and enter the JEFT region 109.

[0045] The first direction is the direction from the first surface to the second surface of the semiconductor layer, that is, Figure 2 The second direction is parallel to the surface of the substrate 101, and the second direction is perpendicular to the first direction.

[0046] In some embodiments of the present invention, the first insulating structure 108 is in an "L" shape; in other embodiments of the present invention, such as Figure 2 As shown, the other side of the first portion of the first insulating structure 108 extends to below the ohmic contact region 105 in a direction away from the gate structure, so that the first portion and the second portion of the first insulating structure 108 are combined into an inverted "T" shape.

[0047] The second insulating structure 114 is located in the JFET region 109 and is spaced apart from the first insulating structure 108. Specifically, the first portions of the first insulating structure 108 located on both sides of the gate structure extend toward each other into the JFET region 109, and the two are separated by the second insulating structure 114, and both have a certain distance from the second insulating structure 114.

[0048] In the embodiment of the present invention, the second insulating structure 114 includes at least a first portion, and there is a distance between the upper surface of the first portion and the upper surface of the drift region 102, and there is also a distance between the lower surface of the first portion and the lower surface of the drift region 102, that is, the first portion is "suspended" in the JFET region 109; the first portion of the second insulating structure 114 is spaced apart from the first portion of the first insulating structure 108. Further, the second insulating structure 114 may also include a second portion, the second portion extends from the upper surface of the JFET region 109 along the first direction to the inside of the JFET region 109, and the bottom of the second portion is connected to the top of the first portion, and the two are combined into an inverted "T" shape.

[0049] Specifically, the second insulating structure 114 includes a second dummy gate 1141 and a second dummy gate dielectric layer 1142, wherein the second dummy gate dielectric layer 1142 surrounds the second dummy gate 1141. The second dummy gate 1141 can be a material that can be used for a gate, such as doped polysilicon and metal, and the second dummy gate dielectric layer 1142 can be a dielectric material commonly used in existing semiconductor devices, such as silicon dioxide, or a stack of silicon dioxide and silicon nitride.

[0050] In the first embodiment, if Figure 2As shown, the first part of the second insulating structure 114 includes a second dummy gate 1141 and a dielectric layer covering a portion of the surface of the second dummy gate 1141, and the second part of the second insulating structure 114 includes a dielectric layer covering the remaining portion of the surface of the second dummy gate 1141. In other embodiments, the second insulating structure 114 may also be other structures, such as the second dummy gate 1141 includes a portion of the structure located in the first portion and another portion of the structure located in the second portion, the two portions of the structure are inverted "T" shape, and the second dummy gate dielectric layer 1142 covers the second dummy gate 1141. In addition, although not shown in the figure, in fact, the second dummy gate 1141 is electrically connected to the gate 107, and specifically, the second dummy gate 1141 can be led out by forming a contact hole penetrating the second dummy gate dielectric layer 1142, and electrically connected to the gate 107 through metal wiring.

[0051] The first portion of the first insulating structure 108 and the first portion of the second insulating structure 114 are aligned in a direction perpendicular to their extension direction, that is, the upper surfaces and lower surfaces of the two are aligned respectively, further limiting the spacing area between the first insulating structure 108 and the second insulating structure 114. Preferably, as Figure 2 As shown, the distance L between the first portion of the first insulating structure 108 and the first portion of the second insulating structure 114 in their extending direction, ie, the second direction, is not greater than 50 nanometers to ensure the current conduction capability of the semiconductor device.

[0052] In the first embodiment described above, the first insulating structure 108 occupies the P-well region under the N+ source region of the traditional structure, eliminating the most important region of the parasitic resistance Rb in the traditional structure, thereby effectively suppressing the opening of the parasitic transistor, and thus improving the avalanche tolerance of the device. Furthermore, the first insulating structure 108 extends into the JFET region 109, and a second insulating structure 114 is provided in the JFET region 109, the second insulating structure 114 adopts a pseudo-gate structure, and the second insulating structure 114 is spaced apart from the first insulating structure 108. When an avalanche occurs, the above-mentioned spacing area is small, so that it is difficult for the holes to flow upward in the spacing area between the second insulating structure 114 and the first insulating structure 108, which can generally suppress the possibility of holes flowing under the source region, thereby greatly improving the device's anti-avalanche capability, and retaining a portion of the current conduction capability, ensuring the normal conduction of the semiconductor device.

[0053] Figure 3 Schematic diagram of the structure of the semiconductor device provided by the second embodiment of the present application. Figure 3As shown, different from the first embodiment, in the semiconductor device provided in the second embodiment of the present application, the first insulating structure 108 also adopts a pseudo gate structure, including a first pseudo gate 1081 and a first pseudo gate dielectric layer 1082 wrapping the first pseudo gate 1081. Among them, the material of the first pseudo gate 1081 can be a gate material commonly used in semiconductor devices such as doped polysilicon and metal; the first pseudo gate dielectric layer 1082 can adopt a dielectric material commonly used in existing semiconductor devices, such as silicon dioxide, or a stack of silicon dioxide and silicon nitride. In addition, although not shown in the figure, in fact, the first pseudo gate 1081 is electrically connected to the gate 107, and the first pseudo gate 1081 can be led out by forming a contact hole extending along the first direction, and electrically connected to the gate 107 through metal wiring.

[0054] The first insulating structure 108 adopts a pseudo gate structure, so that the interval region between the second insulating structure 114 and the first insulating structure 108 forms an inversion layer, which can completely block the upward flow of holes. At the same time, when the device is in the on state, the interval region is actually the inversion layer channel region, which will not affect the normal downward flow of electrons, thereby further inhibiting the flow of holes under the source region and further ensuring the current conduction capability of the device.

[0055] Figure 3 In the illustrated embodiment, the first portion of the first insulating structure 108 includes a first dummy gate 1081 and an insulating dielectric layer that wraps a portion of the surface of the first dummy gate 1081, and the second portion is made entirely of insulating material. The two portions of insulating dielectrics constitute a first dummy gate dielectric layer 1082 that together wrap the first dummy gate 1081. In other embodiments, the first dummy gate 1081 is in an inverted "T" or "L" shape as a whole, with a portion belonging to the first portion of the first insulating structure 108 and another portion belonging to the second portion of the first insulating structure 108; the first dummy gate dielectric layer 1082 wraps around the first dummy gate 1081.

[0056] Figures 4 to 11 The cross-sectional views of various stages of the semiconductor device manufacturing method according to the first and second embodiments of the present invention are shown. Figures 4 to 11 , a method for manufacturing a semiconductor device in the first embodiment and the second embodiment of the present invention is described.

[0057] like Figure 4As shown, a drift region 102 is formed on a substrate 101 to obtain a semiconductor layer. The obtained semiconductor layer includes a stacked substrate 101 and a drift region 102, the lower surface of the drift region 102 faces the substrate 101, the upper surface of the drift region 102 serves as the first surface of the semiconductor layer, the front surface of the substrate 101 faces the drift region 102, and the back surface of the substrate 101 serves as the second surface of the semiconductor layer. In this step, the material of the substrate 101 can be a semiconductor material such as silicon, the doping type can be N-type doping, and the resistivity can be 0.005 to 0.015 ohm·cm. The drift region 102 can be formed, for example, by a deposition process or an epitaxial process. The thickness of the drift region 102 is, for example, about 9 μm, the doping type is N-type doping, and the doping concentration is less than the doping concentration of the substrate 101.

[0058] It should be additionally noted that the above steps are performed as optional steps. In another embodiment, epitaxial wafers that meet the requirements can be directly purchased from the market as semiconductor layers, that is, subsequent steps can be directly implemented on the existing semiconductor layer without performing the above steps.

[0059] Further references Figure 4 , a well region 103 is formed in the drift region 102. In this step, the drift region 102 can be doped with P-type by photolithography, ion implantation and high temperature well driving process to form a well region 103 extending from the upper surface of the drift region 102 to the substrate 101, and the two well regions 103 are arranged at intervals. The drift region 102 located between the two well regions 103 is the JEFT region 109.

[0060] like Figure 5 As shown, a mask layer is formed above the drift region 102 by a photolithography process, and then the drift region 102 is etched to form a first trench 111 and a third trench 115 in the well region 103 and the JFET region 109, respectively. In this step, for example, an anisotropic etching process is used to form the first trench 111 and the third trench 115 extending in the first direction, that is, the depth directions of the first trench 111 and the third trench 115 are parallel to the first direction.

[0061] like Figure 6 As shown, a barrier layer 112 is formed on the inner sidewalls of the first trench 111 and the third trench 115. Specifically, a deposition layer may be formed first, so that the deposition layer at least covers the entire inner wall (including the sidewall and the bottom wall) of the first trench 111 and the third trench 115, and then the deposition layer on the bottom wall of the first trench 111 and the bottom wall of the third trench 115 is removed by an etching process, and the remaining deposition layer on the sidewalls of the first trench 111 and the third trench 115 is the barrier layer 112. For example, a silicon oxide layer may be deposited by a chemical vapor deposition process, and then a dry etching process may be used to form the barrier layer; or a silicon oxide layer may be formed first, and then a silicon nitride layer may be formed, and then a dry etching process may be used to form the barrier layer.

[0062] like Figure 6 As shown, a portion of the well region 103 at the bottom of the first trench 111 is etched along the first trench 111, and a portion of the JFT region 109 at the bottom of the third trench 115 is etched along the third trench 115 to obtain a second trench 113 and a fourth trench 116, respectively. In this step, for example, an isotropic etching process is used to form a second trench 113 at the bottom of the first trench 111, and along the second direction, the size of the second trench 113 is larger than the size of the first trench 111; the method of forming the fourth trench 116 at the bottom of the third trench 115 is similar and will not be repeated. The isotropic etching can be wet etching or vapor etching. The barrier layer 112 in the first trench 111 and the third trench 115 is then removed.

[0063] It is not difficult to understand that the trenches finally formed in the well region 103 include a first trench 111 and a second trench 113 which are interconnected, and the trenches located in the JEFT region 109 include a third trench 115 and a fourth trench 116 which are interconnected, wherein the first trench 111 and the third trench 115 extend along the first direction; the second trench 113 is located at the bottom of the first trench 111 and extends along the second direction, and along the second direction, the size of the second trench 113 is significantly larger than the first trench 111, and the two roughly form an inverted "T" shape; the fourth trench 116 and the third trench 115 also roughly form an inverted "T" shape.

[0064] like Figure 8 and 9 As shown, a method for manufacturing a semiconductor device according to a first embodiment of the present invention includes filling insulating material in a first trench 111 and a second trench 113 located in a well region 103 to form a first insulating structure 108, wherein the insulating material includes but is not limited to silicon oxide, and an optional step also includes planarization treatment to remove the insulating material located on the surface of the semiconductor layer.

[0065] In the third trench 115 and the fourth trench 116 located in the JEFT region 109, an oxide layer or other dielectric layer is grown inside the third trench 115 and the fourth trench 116, and gate materials such as doped polysilicon are deposited to form a second pseudo gate 1141. Of course, etching or other processes can be used to make the top of the second pseudo gate 1141 lower than the top of the third trench 115; then a dielectric layer such as an oxide layer is grown or deposited again to fill the entire trench, so that the dielectric layers formed twice together wrap the entire second pseudo gate 1141, and then the excess dielectric material outside the trench is etched away to form a second gate dielectric layer 1142.

[0066] like Fig.10As shown, the method for manufacturing a semiconductor device according to the second embodiment of the present invention includes simultaneously forming a first insulating structure 108 and a second insulating structure 114. The specific steps may be:

[0067] A first trench 111 and a second trench 113 are formed in the well region 103, and a third trench 115 and a fourth trench 116 are formed in the JEFT region 109; then, a dielectric material layer such as a silicon oxide layer is formed on the inner wall of the trench by the same process, and then gate materials such as doped polysilicon and metal materials are deposited or deposited in the trench to form a second pseudo gate 1141 and a first pseudo gate 1081, respectively; a dielectric material layer is grown or deposited again, and excess dielectric material outside the trench is etched away to form a second pseudo gate dielectric layer 1142 and a first pseudo gate dielectric layer 1082, respectively.

[0068] like Fig.11 As shown, the well region 103 is doped and annealed respectively to form a heavily doped ohmic contact region 105 and a source region 104 , wherein the ohmic contact region 105 is, for example, heavily doped with P type, and the source region 104 is, for example, heavily doped with N type.

[0069] like Fig.11 As shown, an oxide layer is grown on the upper surface of the semiconductor layer, polysilicon is deposited, and etching is performed to produce a gate dielectric layer and a gate 107; a metal layer is deposited on the upper surface of the semiconductor layer and patterned to form a source metal layer 106; the back side of the substrate 101 is thinned, and metal is deposited on the back side of the thinned substrate 101 to form a drain metal layer 110.

[0070] It should be noted that, in addition to the above steps, the present invention also includes: forming through holes penetrating the first dummy gate dielectric layer 1082 and the second dummy gate dielectric layer 1142 to expose the first dummy gate 1081 and the second dummy gate 1141 respectively, and filling the through holes with metal materials such as tungsten to lead out the first dummy gate 1081 and the second dummy gate 1141; leading out the gate 107; and electrically connecting the first dummy gate 1081 and the second dummy gate 1141 to the gate 107 by forming a patterned metal wiring layer. The above steps can be implemented by conventional processes in the art, and will not be repeated here.

[0071] The semiconductor device provided by the embodiment of the present invention is provided with a first insulating structure below the source region 104 to occupy part of the well region below the source region 104, and this region is the most important region of the parasitic resistance Rb in the traditional structure. By eliminating this region, the opening of the parasitic transistor is suppressed, and the effect of enhancing the avalanche tolerance of the device is achieved. At the same time, a second insulating structure is provided in the JFET region, and the second insulating structure adopts a pseudo-gate structure, and the second insulating structure and the first insulating structure are arranged at intervals in the JFET region. When an avalanche occurs, it is difficult for the holes to flow upward in the interval area between the second insulating structure and the first insulating structure, which can generally suppress the possibility of holes flowing under the source region. The typical parameters of the semiconductor device implemented by this structure are basically unaffected, but at the same time the reliability level of the device is effectively improved, and it can be used for the implementation of high-performance and high-reliability power device structures.

[0072] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A semiconductor device, It is characterized in that include: A semiconductor layer having a first surface and a second surface opposite to each other, wherein a drift region is provided in the semiconductor layer, wherein the drift region extends from the first surface of the semiconductor layer into the semiconductor layer, and the semiconductor layer and the drift region are of a first doping type; A gate structure located on the first surface of the semiconductor layer, the gate structure comprising a gate dielectric layer and a gate which are stacked; Extending from the first surface of the semiconductor layer to a well region in the drift region, the well region being located on both sides of the gate structure; The drift region between adjacent well regions is a JEFT region; the well region is of a second doping type, and the second doping type is opposite to the first doping type; Extending from the upper surface of the well region to the source region in the well region, the source region being of a first doping type; a first insulating structure located in the well region, the first insulating structure comprising at least a first portion, the first portion being located between the source region and a lower surface of the well region and extending into the JEFT region; the first insulating structure being insulated from the drift region; A second insulating structure is located in the JFET region, the second insulating structure is spaced apart from the first insulating structure on both sides, the second insulating structure comprises a second dummy gate and a second dummy gate dielectric layer, and the second dummy gate dielectric layer surrounds the second dummy gate.

2. The semiconductor device according to claim 1, It is characterized in that The first insulating structure further comprises a second portion, wherein: One side of the first portion extends into the JFET region in a direction toward the gate structure; The second portion is located at a side of the source region away from the gate structure, extends from the upper surface of the well region into the well region and is connected to the first portion.

3. The semiconductor device according to claim 2, It is characterized in that Also includes: An ohmic contact region extending from the upper surface of the well region to the well region, the ohmic contact region being located on a side of the source region away from the gate structure, and the ohmic contact region being of a second doping type; A source metal layer is located on the first surface of the semiconductor layer, and the source metal layer is in contact with the ohmic contact region and the source region respectively.

4. The semiconductor device according to claim 3, It is characterized in that The second portion of the first insulating structure is located between the ohmic contact region and the source region; the other side of the first portion extends in a direction away from the gate structure to between the ohmic contact region and the lower surface of the well region.

5. The semiconductor device according to any one of claims 1 to 4, It is characterized in that The material of the first insulating structure is insulating material; Alternatively, the first insulating structure includes a first dummy gate and a first dummy gate dielectric layer, and the first dummy gate dielectric layer surrounds the first dummy gate.

6. The semiconductor device according to any one of claims 1 to 5, It is characterized in that Along the direction of the thickness of the semiconductor layer, a distance between a lower surface of the first insulating structure and a lower surface of the well region is greater than or equal to 0.5 micrometers.

7. The semiconductor device according to any one of claims 1 to 5, It is characterized in that The second insulating structure comprises a first portion and a second portion, wherein: The first part of the second insulating structure extends toward the first insulating structures on both sides and is spaced apart from the first insulating structures; The second portion of the second insulating structure extends from the upper surface of the JFET region into the JFET region and is connected to the first portion of the second insulating structure.

8. The semiconductor device according to claim 7, It is characterized in that The first portion of the first insulating structure is aligned with the first portion of the second insulating structure in a thickness direction of the semiconductor layer.

9. The semiconductor device according to claim 8, It is characterized in that A distance between the first portion of the first insulating structure and the first portion of the second insulating structure in their extending directions is no greater than 50 nanometers.

10. The semiconductor device according to any one of claims 1 to 5, It is characterized in that Also included is a drain metal layer located on the second surface of the semiconductor layer.

11. A method for manufacturing a semiconductor device, It is characterized in that include: Forming well regions arranged at intervals in the drift region of the semiconductor layer, wherein the drift region extends from the first surface of the semiconductor layer to the inside of the semiconductor layer, and the well region extends from the first surface of the semiconductor layer to the drift region, and the drift region between adjacent well regions is a JEFT region; forming a source region extending from the upper surface of the well region into the well region; forming a first insulating structure in the well region, the first insulating structure comprising at least a first portion, the first portion being located between the source region and the lower surface of the well region and extending into the JEFT region; the first insulating structure being insulated from the drift region; forming a second insulating structure in the JFET region, the second insulating structure being spaced apart from the first insulating structure, the second insulating structure comprising a second dummy gate and a second dummy gate dielectric layer, the second dummy gate dielectric layer surrounding the second dummy gate; forming a gate structure on the first surface of the semiconductor, the gate structure comprising a gate dielectric layer and a gate which are stacked, and the gate structure covers the JEFT region; The semiconductor layer, the drift region and the source region are of a first doping type, the well region is of a second doping type, and the second doping type is opposite to the first doping type.

12. The manufacturing method according to claim 11, It is characterized in that The process of forming the first insulating structure includes: Etching the well region to form a first trench, wherein the first trench extends from the upper surface of the well region into the well region; forming a barrier layer on the inner sidewall of the first trench; Etching the bottom of the first trench by an isotropic etching process to form a second trench at the bottom of the first trench, wherein the second trench is located between the source region and the lower surface of the well region, and one side of the second trench extends toward the gate structure into the JFET region; The barrier layer in the first trench is removed, a first dielectric layer is formed on the inner walls of the first trench and the second trench, and the first trench and the second trench are filled to form a first pseudo gate, wherein the upper surface of the first pseudo gate is lower than the top of the first trench; a second dielectric layer is filled in the first trench, and the second dielectric layer is connected to the first dielectric layer to form a first pseudo gate dielectric layer.

13. The manufacturing method according to claim 11, It is characterized in that The process of forming the first insulating structure includes: Etching the well region to form a first trench, wherein the first trench extends from the upper surface of the well region into the well region; forming a barrier layer on the inner sidewall of the first trench; Etching the bottom of the first trench by an isotropic etching process to form a second trench at the bottom of the first trench, wherein the second trench is located between the source region and the lower surface of the well region, and one side of the second trench extends toward the gate structure into the JFET region; The barrier layer in the first trench is removed, and an insulating material is filled in the first trench and the second trench to form the first insulating structure.

14. The manufacturing method according to any one of claims 11 to 13, It is characterized in that The process of forming the second insulating structure includes: Etching the JFET region to form a third trench; forming a barrier layer on an inner sidewall of the third trench; Etching the bottom of the third trench using an isotropic etching process to form a fourth trench at the bottom of the third trench, with two sides of the fourth trench extending toward the first insulating structure and beyond the third trench; The barrier layer in the third trench is removed, a third dielectric layer is formed on the inner walls of the third trench and the fourth trench, and the third trench and the fourth trench are filled to form a second pseudo gate, wherein the upper surface of the second pseudo gate is lower than the top of the third trench; a fourth dielectric layer is filled in the third trench, and the fourth dielectric layer is connected to the third dielectric layer to form a second pseudo gate dielectric layer.

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