Silicon carbide diode and manufacturing method thereof

Abstract

The invention discloses a silicon carbide diode and a manufacturing method thereof. The silicon carbide diode comprises a substrate, and a buffer layer, an n-type drift region, a contact metal layer and an outer side metal layer are sequentially arranged on the substrate in the vertical direction. Wherein a plurality of p-type doped regions are embedded in the drift region of the n-type drift region at intervals. The contact metal layer is in contact with the n-type drift region and the p-type doped region, and the width of the contact region of the p-type doped region and the contact metal layer is gradually increased from the edge to the center. According to the invention, the non-uniform distribution rule that the width of the contact region of the p-type doped region is gradually increased from the edge to the center of the region is utilized, so that the higher junction temperature of the central region of the device is reduced, the temperature distribution of the device is more uniform, and the reliability of the SiC diode is improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and in particular to a silicon carbide diode and a manufacturing method thereof. Background Art

[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limits of the material, while devices made of third-generation semiconductor materials represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance.

[0003] As a representative of SiC devices, SiC MOSFET has many excellent characteristics such as low conduction loss, fast switching speed, and high operating frequency. It has gradually been promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC transmission. Since silicon carbide devices need to challenge some extreme environments in different working scenarios, such as being used in high temperature and high pulse current environments, the reliability of silicon carbide devices also needs to be improved.

[0004] In the design of reliability improvement, a common method is to improve the surge current resistance of Schottky diodes. Ordinary Schottky diodes are arranged in an array in a PN alternating manner. The forward direction reduces the turn-on voltage through the Schottky in the n region, reduces the forward voltage drop, and thus reduces the on-resistance at normal high temperatures; on the other hand, a PN junction is formed through the p region, and the reverse blocking characteristics of the PN junction are used to reduce the reverse leakage current and increase the breakdown voltage. However, since the p region of the ordinary Schottky diode does not form an ohmic contact in the forward direction, the potential barrier is high, and the PN junction does not conduct in the forward state; therefore, the high surge current resistance characteristics of the ordinary Schottky diode cannot be displayed; on the other hand, when the SiC diode chip is in the working state, due to the different heat dissipation efficiencies in different regions of the chip, a temperature gradient will appear between different regions of the chip, and the central region of the chip often shows a higher junction temperature, which makes the SiC diode chip still have the risk of high-temperature failure when the junction temperature in some regions does not reach the limit, which has an adverse effect on the reliability of the SiC diode chip.

[0005] In summary, the design needs to be optimized to utilize the pn junction to improve the surge current capability, improve the temperature distribution, reduce the occurrence of heat accumulation, and improve the overall reliability. Summary of the invention

[0006] The present invention provides a silicon carbide diode with an improved structure to solve the above problems.

[0007] The present invention adopts the following technical solutions to solve the above technical problems:

[0008] In one aspect, the present invention provides a silicon carbide diode, comprising a substrate;

[0009] The substrate is provided with a buffer layer, an n-type drift region, a contact metal layer, and an outer metal layer in sequence along a vertical direction;

[0010] The n-type drift region is provided on the upper surface of the buffer layer; a plurality of p-type doped regions are embedded in the drift region of the n-type drift region;

[0011] The contact metal layer is provided on the upper surface of the n-type drift region; the contact metal layer contacts the n-type drift region and the p-type doping region respectively; the contact region width between the p-type doping region and the contact metal layer increases in sequence from the outer edge to the center of the n-type drift region;

[0012] The outer metal layer is disposed on the upper surface of the contact metal layer.

[0013] Optionally, the p-type doped region includes a p-type low-doped region and a p-type high-doped region;

[0014] The p-type highly doped region and the contact metal layer form a quasi-ohmic contact region;

[0015] The adjacent p-type doped region and the contact metal layer form a Schottky contact region.

[0016] Optionally, the doping width of the p-type low-doping region ranges from 0.1 μm to 10 μm;

[0017] The depth of the p-type low-doping region ranges from 0.5 μm to 10 μm;

[0018] The doping concentration of the p-type low-doping region is in the range of 1×10 15 cm -3 -1×10 19 cm -3 .

[0019] Optionally, the doping width of the p-type high-doping region ranges from 0.1 μm to 10 μm;

[0020] The depth of the p-type high-doping region ranges from 0.5 μm to 10 μm;

[0021] The doping concentration range of the p-type high doping region is 1×10 19 cm -3 -1×10 20 cm -3 .

[0022] Optionally, the width of the contact region between the p-type doped region at the outer edge of the n-type drift region and the contact metal layer is in the range of 0.1 μm-3 μm;

[0023] The width of the contact region between the p-type doping region at the center of the n-type drift region and the contact metal layer is in the range of 1 μm-10 μm.

[0024] Optionally, the width of the contact region between the p-type doping region and the contact metal layer increases in a gradient range of 1 μm-10 μm per micron.

[0025] Optionally, a distance between an upper surface of the p-type doping region and an upper surface of the n-type drift region is in a range of 0-100 μm.

[0026] Optionally, the surface profile of the p-type doping region is at least one of a stripe, an alternate stripe, a regular quadrilateral, and a regular hexagon;

[0027] The contact area width between the p-type doping region and the contact metal layer is the maximum width of the surface profile of the p-type doping region.

[0028] Optionally, the contact metal layer is a titanium metal layer or a nickel metal layer, or a titanium-nickel alloy layer.

[0029] Optionally, a back metal layer is also provided on the lower surface of the substrate.

[0030] On the other hand, the present invention also provides a method for manufacturing a silicon carbide diode, which mainly comprises the following steps:

[0031] Pre-treating the substrate;

[0032] Preparing an epitaxial layer on the substrate, wherein the epitaxial layer at least includes a buffer layer and an n-type drift region;

[0033] preparing a silicon dioxide mask on the epitaxial layer by using a mask plate;

[0034] Processing a mask structure of a p-type doping region based on photolithography and dry etching, and doping the p-type doping region by ion implantation;

[0035] A contact metal layer and an outer metal layer are sequentially processed on the epitaxial layer by a deposition method.

[0036] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0037] The present invention utilizes the non-uniform distribution law that the width of the contact area of ​​the p-type doped area increases from the edge to the center of the area, thereby reducing the higher junction temperature in the central area of ​​the device, making the temperature distribution of the device more uniform, and improving the reliability of the silicon carbide diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 is a schematic structural diagram of a silicon carbide diode in a specific embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of a mask in a specific embodiment of the present invention;

[0041] Figure 3 It is a flow chart of a method for manufacturing a silicon carbide diode in a specific embodiment of the present invention.

[0042] In the figure, 1, substrate, 2, buffer layer, 3, n-type drift region, 4, p-type low-doped region, 5, p-type high-doped region, 6, contact metal layer, 7, outer metal layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present invention, it is necessary to understand that the relative relationships indicated by the terms "upper" and "lower" are based on the order of contact with the material in the rotation direction in actual applications. They are for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position. Therefore, they cannot be understood as limitations on the present invention.

[0046] In the description of the present invention, “plurality” means two or more than two, unless otherwise clearly and specifically defined.

[0047] It should be noted that the methods used in the present invention are all conventional methods unless otherwise specified; the raw materials and devices used are all conventional commercially available products unless otherwise specified.

[0048] This embodiment provides a silicon carbide diode, such as Figure 1 As shown, it includes a substrate 1. The substrate 1 is a 4H-SiC substrate, on which a buffer layer 2, an n-type drift region 3, a contact metal layer 6 and an outer metal layer 7 are sequentially arranged along a vertical direction.

[0049] An n-type drift region 3 is provided on the upper surface of the buffer layer 2. A plurality of p-type doped regions are interspersed in the upper drift region of the n-type drift region 3. A contact metal layer 6 is provided on the upper surface of the n-type drift region 3. There are multiple choices of materials for the contact metal layer 6, specifically a titanium metal layer or a nickel metal layer, or a titanium-nickel alloy layer. The lower surface of the contact metal layer 6 is in contact with the n-type drift region and the p-type doped region respectively; wherein the p-type doped region is provided with a p-type low doped region 4 and a p-type high doped region 5. The p-type high doped region 5 forms a quasi-ohmic contact region with the contact region of the contact metal layer 6 provided in the upper layer. A quasi-ohmic contact region refers to: a region exhibiting characteristics similar to an ohmic contact. Ohmic contact is an ideal contact state, which is characterized by very small resistance at the contact interface and a linear relationship between current and voltage. Although the quasi-ohmic contact region cannot completely achieve the ideal state of ohmic contact, it has a lower contact resistance and a more linear current-voltage characteristic to a certain extent. A Schottky contact region is formed between adjacent p-type doped regions and the contact metal layer 6. This embodiment increases the implantation concentration of the doping region to form a quasi-ohmic contact between the p-type region and the contact metal, so that when the forward voltage is large, the PN junction in the Schottky diode is turned on, showing a high surge current resistance characteristic.

[0050] Furthermore, the doping width of the p-type low-doping region 4 is in the range of 0.1 μm-10 μm, and the depth of the p-type low-doping region 4 is in the range of 0.5 μm-10 μm; the doping concentration of the p-type low-doping region 4 is in the range of 1×10 15 cm -3 -1×10 19 cm -3 .

[0051] Furthermore, the doping width of the p-type high-doping region 5 is in the range of 0.1 μm-10 μm, and the depth of the p-type high-doping region is in the range of 0.5 μm-10 μm; the doping concentration of the p-type high-doping region is in the range of 1×10 19 cm -3 -1×10 20 cm -3 .

[0052] The surface profile of each p-type doping region is a combination of one or more shapes such as strips, spaced strips, regular quadrilaterals, and regular hexagons. In this embodiment, a regular quadrilateral is used as an example for explanation, and the width of the contact area between the p-type doping region and the contact metal layer 6 is the maximum width of the surface profile of the p-type doping region. Therefore, in this embodiment, its width is the side length of the p-type doping region; it should not be understood here as the diagonal length, although the diagonal is the maximum point, but the width should be understood as at least a direction parallel to the length of one side.

[0053] The contact area widths between the multiple p-type doped regions on the n-type drift region 3 and the contact metal layer 6 increase in sequence from the edge of the n-type drift region 3 to the center of the n-type drift region 3. Figure 2 As shown in the mask, the side length of the regular quadrilateral contact area at the edge is smaller, and the side length gradually increases as it approaches the center area; specifically, the contact area width of the p-type doped area and the contact metal layer 6 increases by 1μm-10μm per micron; for example: the distance (gradient direction distance) between the center of the second circle regular quadrilateral contact area on the center side and the center of the regular quadrilateral contact area of ​​the adjacent outer circle (third circle) is n microns, then the side length of the second circle regular quadrilateral contact area is n-10n longer than the side length of the third circle regular quadrilateral contact area, in microns. On this basis, the present embodiment also designs the contact area width range of the p-type doped area at the edge to be 0.1μm-3μm; and the contact area width range of the p-type doped area at the center is 1μm-10μm. This design can reduce the higher junction temperature in the central area of ​​the chip, make the temperature distribution of the chip more uniform, and improve the reliability of the SiC diode.

[0054] Optionally, the distance between the upper surface of the p-type doping region and the upper surface of the n-type drift region is in the range of 0-100 μm, that is, they may be aligned, or the p-type doping region may have a small amount of sinking structure.

[0055] An outer metal layer 7 is provided on the upper surface of the contact metal layer 6, and a back metal layer (not shown) is also processed on the lower surface of the substrate 1.

[0056] Based on the above embodiments, the present invention also provides a method for manufacturing a silicon carbide diode. Figure 3 As shown, for ease of understanding, a relatively clear process sequence (S1-S6) is used for explanation, which should not be understood as a restriction. In specific scenarios, technicians can adjust the sequence of process steps according to actual needs.

[0057] Therefore, the main steps of the method in this embodiment include:

[0058] S1. Pre-treat the substrate; select a 6-inch SiC substrate material with a processing thickness of 350 μm, and perform surface cleaning and other surface treatment work;

[0059] S2. preparing an epitaxial layer on the substrate, the epitaxial layer including a buffer layer and an n-type drift region; specifically, sequentially growing an N+ buffer layer and an N-drift layer (region) on the Si surface of a 6-inch SiC substrate;

[0060] S3, preparing a silicon dioxide mask on the epitaxial layer through a mask plate;

[0061] S4, based on photolithography and dry etching to process the mask structure of the p-type doping region, such as Figure 2 As shown, the p-type doping region is doped twice by a high temperature ion implantation method, thereby forming a p-type low-doping region and a p-type high-doping region;

[0062] S5, sequentially processing the contact metal layer 6 and the outer metal layer 7 on the epitaxial layer by a deposition method;

[0063] Furthermore, it also includes:

[0064] S6. Perform a thinning process below the substrate 1 and process a back metal layer on the processed lower surface by a deposition method.

[0065] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A silicon carbide diode, characterized in that: It comprises a substrate; a buffer layer, an n-type drift region, a contact metal layer, and an outer metal layer are sequentially arranged on the substrate along a vertical direction; The n-type drift region is provided on the upper surface of the buffer layer; a plurality of p-type doped regions are embedded in the drift region of the n-type drift region; The contact metal layer is provided on the upper surface of the n-type drift region; the contact metal layer contacts the n-type drift region and the p-type doping region respectively; the contact region width between the p-type doping region and the contact metal layer increases in sequence from the outer edge to the center of the n-type drift region; The outer metal layer is disposed on the upper surface of the contact metal layer.

2. The silicon carbide diode according to claim 1, characterized in that: The p-type doping region includes a p-type low-doping region and a p-type high-doping region; The p-type highly doped region and the contact metal layer form a quasi-ohmic contact region; The adjacent p-type doped region and the contact metal layer form a Schottky contact region.

3. The silicon carbide diode according to claim 2, characterized in that: The doping width of the p-type low-doping region ranges from 0.1 μm to 10 μm; The depth of the p-type low-doping region ranges from 0.5 μm to 10 μm; The doping concentration of the p-type low-doping region is in the range of 1×10 15 cm -3 -1×10 19 cm -3 .

4. The silicon carbide diode according to claim 2, characterized in that: The doping width of the p-type high-doping region ranges from 0.1 μm to 10 μm; The depth of the p-type high-doping region ranges from 0.5 μm to 10 μm; The doping concentration range of the p-type high doping region is 1×10 19 cm -3 -1×10 20 cm -3 .

5. The silicon carbide diode according to claim 3 or 4, characterized in that: The width of the contact region between the p-type doped region at the outer edge of the n-type drift region and the contact metal layer is in the range of 0.1 μm to 3 μm; The width of the contact region between the p-type doping region at the center of the n-type drift region and the contact metal layer is in the range of 1 μm-10 μm.

6. The silicon carbide diode according to claim 5, characterized in that: The width of the contact area between the p-type doping area and the contact metal layer increases gradually in a range of 1 μm to 10 μm per micron.

7. The silicon carbide diode according to claim 1, characterized in that: The distance between the upper surface of the p-type doping region and the upper surface of the n-type drift region is in the range of 0-100 μm.

8. The silicon carbide diode according to claim 1, characterized in that: The surface profile of the p-type doping region is at least one of a stripe, an alternate stripe, a regular quadrilateral, and a regular hexagon; The width of the contact region between the p-type doping region and the contact metal layer is the maximum width of the surface profile of the p-type doping region.

9. The silicon carbide diode according to claim 1, characterized in that: The contact metal layer is a titanium metal layer or a nickel metal layer, or a titanium-nickel alloy layer.

10. The silicon carbide diode according to claim 1, characterized in that: The lower surface of the substrate is also provided with a back metal layer.

11. A method for manufacturing a silicon carbide diode, characterized in that: The steps include: Pre-treating the substrate; Preparing an epitaxial layer on the substrate, wherein the epitaxial layer at least includes a buffer layer and an n-type drift region; preparing a silicon dioxide mask on the epitaxial layer by using a mask plate; Processing a mask structure of a p-type doping region based on photolithography and dry etching, and doping the p-type doping region by ion implantation; A contact metal layer and an outer metal layer are sequentially processed on the epitaxial layer by a deposition method.

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