Novel groove silicon carbide chip structure and preparation method thereof

Abstract

The invention discloses a novel groove silicon carbide chip structure and a preparation method, and particularly relates to the technical field of semiconductors, and the novel groove silicon carbide chip structure comprises back thickening metal, ohmic contact metal, a silicon carbide substrate and a silicon carbide epitaxial layer which are sequentially arranged from bottom to top. According to the groove type field limiting ring structure with the gradually-changed depth, under the condition that the area of a terminal is not increased, the inhibition effect of the terminal on a surface electric field is improved by changing the depth of the field limiting ring and changing electric field distribution, the reverse breakdown voltage of a chip is improved, and the method does not increase manufacturing procedures and is suitable for large-scale production. And the increase of the manufacturing cost of the device is small.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a novel grooved silicon carbide chip structure and a preparation method thereof. Background Art

[0002] Silicon carbide material has become the preferred material for manufacturing high-temperature, high-frequency, high-power and high-voltage devices due to its unique physical properties. Its characteristics include large bandgap, excellent thermal conductivity, high electron saturation migration rate and super strong breakdown electric field. Due to these outstanding properties, SiC devices have demonstrated unparalleled superiority in multiple extreme environments in the field of electronic devices, such as high temperature, high pressure, high frequency and high power environments, as well as aerospace, military industry, nuclear energy and other applications. It effectively makes up for the shortcomings of traditional semiconductor materials in practical applications and has been established as the future development direction of power semiconductors.

[0003] After searching, a Chinese patent with announcement number CN116314340A discloses a trench-type silicon carbide MOSFET device and a preparation method thereof. The P-type shielding region in the scheme has a good shielding effect on the gate of the device when the device is reversely withstand voltage, thereby improving the gate oxide reliability and improving the breakdown voltage of the device. At the same time, the P-type buried layer region in the device structure is formed by ion implantation, arranged below the P-type shielding region and below the longitudinal trench, extending into the N-type epitaxial layer, increasing the lateral depletion of the N-type epitaxial layer, so that a higher concentration of N-type epitaxial layer can be selected when designing the device, significantly reducing the on-resistance of the device.

[0004] In addition, the Chinese patent with announcement number CN116110935A discloses a trench-type silicon carbide device and a preparation method thereof. The technical solution is to set a partially surrounding P-type shielding layer at the bottom of part or all of the gate trenches, and the P-type shielding layer is not connected to the P-well layer, so that when the trench-type silicon carbide device is in an open state, the channels on both sides of the gate trench can be turned on, so it has a smaller on-resistance; and when the trench-type silicon carbide device is in a short-circuit state, the area between the P-type shielding layer and the P-well layer that is closer is depleted, so that part of the channel is turned off, the saturation current is reduced, and the short-circuit capability is improved; in addition, when the trench-type silicon carbide device is in a reverse blocking state, the adjacent P-type shielding layer and the P-well layer are depleted and pinched off from each other, thereby reducing the electric field strength on the oxide layer at the bottom of the gate trench, thereby protecting the gate oxide layer.

[0005] However, at present, the methods for improving the reverse breakdown voltage of the device include increasing the thickness of the epitaxial layer and increasing the area of ​​the terminal region, but these methods have obvious disadvantages: Increasing the thickness of the epitaxial layer will increase the number of defects in the epitaxial layer, reduce the yield and performance of the chip, and increase the cost of the chip; Increasing the area of ​​the terminal region will increase the chip area and increase the cost of the chip, all of which limit the further improvement and promotion of the performance of silicon carbide devices.

[0006] At present, the terminals of power device products on the market mainly adopt a field limiting ring + field plate structure. In order to solve the above problems, the present invention proposes a silicon carbide chip with a novel groove field limiting ring structure with varying depth on the basis of the field limiting ring + field plate structure. The reverse breakdown voltage of the device is increased by changing the injection depth of the field limiting ring without increasing the process, chip area and epitaxial layer thickness and with little cost increase. Summary of the invention

[0007] In order to overcome the above-mentioned defects of the prior art, the present invention provides a novel grooved silicon carbide chip structure and a preparation method thereof to solve the problems raised in the above-mentioned background technology.

[0008] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a novel grooved silicon carbide chip structure, the novel grooved silicon carbide chip structure comprises a back-side thickened metal, an ohmic contact metal, a silicon carbide substrate and a silicon carbide epitaxial layer arranged in sequence from bottom to top, the top of the silicon carbide epitaxial layer is provided with a P-type injection region extending into the silicon carbide epitaxial layer, a P-type main junction and a groove, and a P-type field limiting ring under the groove, wherein the depth of the P-type field limiting ring is variable, the spacing between the P-type field limiting rings is variable, and the silicon carbide epitaxial layer A field oxide layer covering part of the P-type main junction and all the P-type field limiting rings is provided, and the field oxide layer is filled in the groove of the silicon carbide epitaxial layer, a Schottky contact metal covering all the P-type injection areas and extending to part of the field oxide layer is provided on the silicon carbide epitaxial layer, a front thickening metal is provided on the Schottky contact metal, an inorganic passivation layer extending to part of the front thickening metal is provided on the field oxide layer, an organic passivation layer is provided on the inorganic passivation layer, and the conductivity type of the silicon carbide substrate and the silicon carbide epitaxial layer are both N-type.

[0009] Preferably, the heights and doping concentrations of the P-type injection region, the P-type main junction and the P-type field limiting ring are the same, the widths of the multiple P-type injection regions are the same, the spacings between the multiple P-type injection regions are the same, the depths of the P-type injection region and the P-type main junction are set to be the same, and the widths of the groove and the P-type field limiting ring are the same.

[0010] Preferably, the right ends of the Schottky contact metal and the front thickening metal are laid on the field oxide layer, and the left front ends of the inorganic passivation layer and the organic passivation layer are laid above the front thickening metal.

[0011] The present invention also provides a preparation method for preparing the novel grooved silicon carbide chip structure, the preparation method comprising the following steps: S1. Depositing a silicon oxide film on the surface of the silicon carbide epitaxial layer using plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition technology, coating a photoresist on the surface of the silicon oxide film, and patterning the film surface using grayscale photolithography technology so that the photoresist presents grooves with varying depths; S2. Using photoresist as a mask, and using inductively coupled plasma enhanced etching or reactive ion etching technology to etch the silicon oxide film and the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer has a groove with varying depth in the field limiting ring area; S3, using the silicon oxide layer as a masking layer, Al ion implantation is performed on the device, followed by high temperature activation annealing, to form a P-type implantation region, a P-type main junction and a P-type field limiting ring with varying depth in the active region and the terminal region; S4, removing the silicon oxide layer using a wet etching technique; S5, forming silicon oxide in the terminal area of ​​the silicon carbide chip by high temperature oxidation or PECVD, LPCVD deposition to form a field oxide layer; S6. Forming a Schottky contact metal on the active area and part of the main junction of the silicon carbide chip by sputtering or evaporation, and then forming a Schottky contact metal between the metal and the silicon carbide by alloying, rapid annealing or laser annealing; S7, depositing a front thickening metal on the Schottky contact metal by sputtering or evaporation; S8, depositing an inorganic passivation layer on the field oxide layer, and then coating an organic passivation layer on the inorganic passivation layer and curing it; S9, forming an ohmic contact metal on the back of the silicon carbide chip by sputtering or evaporation, and forming an ohmic contact metal between the metal and the silicon carbide by laser annealing; S10, forming a back thickening metal on the ohmic contact metal by sputtering or evaporation.

[0012] Preferably, the preparation method further comprises the steps of: In S7, a microstructure layer is formed on the thickened metal on the front side to increase the surface area of ​​the device and improve the heat dissipation performance and current carrying capacity. The microstructure layer is implemented using a microstructure in the shape of nanoparticles, nanowires or nanopillars.

[0013] Technical effects and advantages of the present invention: The depth-gradient groove field limiting ring structure proposed in the present invention can change the electric field distribution by changing the depth of the field limiting ring without increasing the terminal area, thereby improving the terminal's suppression of the surface electric field and improving the reverse breakdown voltage of the chip. In addition, the method proposed in the present invention does not increase the manufacturing process and has a small increase in the device manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1It is a schematic diagram of the structure of the grooved silicon carbide chip of the present invention.

[0015] Figure 2 This is one of the flow charts for preparing the silicon carbide chip structure of the present invention.

[0016] Figure 3 This is the second flow chart for preparing the silicon carbide chip structure of the present invention.

[0017] Figure 4 The third flowchart of the silicon carbide chip structure preparation of the present invention.

[0018] Figure 5 The fourth is the flow chart for preparing the silicon carbide chip structure of the present invention.

[0019] The accompanying drawings are marked as follows: 1. back-side thickened metal; 2. ohmic contact metal; 3. silicon carbide substrate; 4. silicon carbide epitaxial layer; 5. P-type injection region; 6. P-type main junction; 7. trench; 8. P-type field limiting ring; 9. field oxide layer; 10. Schottky contact metal; 11. front-side thickened metal; 12. inorganic passivation layer; 13. organic passivation layer. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example 1

[0021] This embodiment provides a novel grooved silicon carbide chip structure, as shown in the attached Figure 1 As shown, the novel trench silicon carbide chip structure includes a back-side thickened metal 1, an ohmic contact metal 2, a silicon carbide substrate 3 and a silicon carbide epitaxial layer 4 which are arranged in sequence from bottom to top.

[0022] Specifically, the back thickened metal 1 serves as the back electrode of the device, and is used to provide a conduction path for the current. The thickened metal can increase the conductivity, reduce the resistance, and improve the current carrying capacity. The ohmic contact metal 2 forms an ohmic contact with the silicon carbide substrate 3, that is, to achieve low-resistance contact between the metal and the semiconductor. The function of the ohmic contact metal 2 is to provide an input and output channel for the current, and to ensure that the current can flow smoothly into and out of the device. The silicon carbide substrate 3, as the basic supporting material of the device, has excellent physical and chemical stability and can withstand harsh environments such as high temperature and high pressure. The silicon carbide substrate 3 also has good thermal conductivity, which helps to dissipate heat and maintain stable operation of the device. The silicon carbide epitaxial layer 4 is a single crystal thin film grown on the silicon carbide substrate 3, and is used to make the active area and terminal area of ​​the device. The silicon carbide epitaxial layer 4 has a high-quality crystal structure, which can improve the performance and reliability of the device. In summary, the device structure realizes key functions such as current input and output, ohmic contact between metal and semiconductor, high-quality crystal structure and good heat dissipation performance by setting it up in sequence from bottom to top. The reasonable combination of these functions enables the device structure to operate stably in harsh environments such as high temperature and high pressure, and have high performance and reliability.

[0023] Further as attached Figure 1 As shown, a P-type implantation region 5 extending into the silicon carbide epitaxial layer 4 , a P-type main junction 6 and a trench 7 , and a P-type field limiting ring 8 below the trench 7 are arranged on the top of the silicon carbide epitaxial layer 4 .

[0024] Specifically, the P-type implantation region 5, the P-type main junction 6 and the trench 7 on the top of the silicon carbide epitaxial layer 4, and the P-type field limiting ring 8 below the trench 7 constitute the key structure of the device, which is used to control the current and increase the blocking voltage; The P-type implantation region 5 is a region formed by ion implantation, which is used to adjust the conductivity of the semiconductor and form a PN junction. In the power device, the P-type implantation region 5 has the function of controlling the current channel and affecting the switching characteristics of the device. The P-type main junction 6 is the interface formed by the contact between the P-type and N-type semiconductor materials, and is the basis for realizing the functions of semiconductor devices. In silicon carbide devices, the P-type main junction 6 is usually used to withstand high voltage and control the flow of current; The groove 7 can increase the surface area of ​​the device, which helps to improve the current distribution and reduce the surface electric field, thereby improving the breakdown voltage and reliability of the device; The P-type field limiting ring 8 is located below the trench 7 and is used to limit the flow of carriers, reduce electric field concentration, avoid local overheating, and improve the stability and short-circuit resistance of the device; Due to the special properties of silicon carbide materials, such as wide bandgap, high thermal conductivity and high electron saturation drift velocity, it performs well in high temperature, high voltage and high frequency applications. The quality of the epitaxial layer directly affects the performance and yield of the device. Therefore, epitaxial technology is one of the core technologies for preparing high-performance silicon carbide power devices. In summary, these structures on top of the silicon carbide epitaxial layer 4 are crucial to achieving high performance and high reliability of the device, and they work together to control the current, block the voltage, and improve the overall performance of the device.

[0025] Further as attached Figure 1 As shown, a field oxide layer 9 covering a portion of the P-type main junction 6 and the entire P-type field limiting ring 8 is disposed on the silicon carbide epitaxial layer 4 , and the field oxide layer 9 is filled into the trench 7 of the silicon carbide epitaxial layer 4 .

[0026] Specifically, the field oxide layer 9 on the silicon carbide epitaxial layer 4 mainly plays an insulating and protective role, and also helps to improve the breakdown voltage of the device. In addition, the silicon carbide epitaxial layer 4 is a single crystal film grown on the silicon carbide substrate 3, and it has the same crystal structure as the substrate. Fabricating devices on the silicon carbide epitaxial layer 4 can ensure a high-quality crystal structure, thereby improving the overall performance of the device. Moreover, the resistivity of the silicon carbide epitaxial layer 4 is usually high, which helps to improve the breakdown voltage of the device. At the same time, the silicon carbide substrate 3 itself has a low resistivity, which helps to reduce the resistance of the substrate, thereby reducing the saturation voltage drop and optimizing the performance of the device.

[0027] Further as attached Figure 1 As shown, a Schottky contact metal 10 is provided on the silicon carbide epitaxial layer 4 , covering the entire P-type implantation region 5 and extending to a portion of the field oxide layer 9 , and a front thickening metal 11 is provided on the Schottky contact metal 10 .

[0028] Specifically, the Schottky contact metal 10 and the front thickened metal 11 constitute the anode of the device, which is the key part for realizing current conduction. When the Schottky contact metal 10 contacts the N-type silicon carbide epitaxial layer 4, a Schottky barrier is formed, which can control the current to flow in one direction, thereby realizing the rectification function, and the front thickened metal 11 can increase the conductivity of the anode, reduce resistance, and improve current carrying capacity. Therefore, the Schottky contact metal 10 and the front thickened metal 11 play an important role in forming a Schottky barrier, optimizing contact resistance, improving voltage resistance and enhancing conductivity in the device, and are the key structures for realizing high-performance silicon carbide devices.

[0029] Further as attached Figure 1 As shown, an inorganic passivation layer 12 extending onto a portion of the front thickened metal 11 is disposed on the field oxide layer 9 , and an organic passivation layer 13 is disposed on the inorganic passivation layer 12 .

[0030] Specifically, the inorganic passivation layer 12 and the organic passivation layer 13 work together to protect the device from environmental influences and improve its stability and reliability. Specifically, the inorganic passivation layer 12 is usually composed of inorganic materials such as SiO2 and Si3N4. These materials can form a very thin, dense film with good coverage performance. This film is used to protect the chip surface and improve the reverse breakdown voltage of the chip. At the same time, this film has the properties of high temperature resistance, dense structure, high hardness, good hydrophobicity, difficulty in gas and water permeability, and blocking foreign ion pollution, which can improve the reliability and stability of the chip in extreme environments of high temperature and high humidity; Organic passivation layers 13, such as PI polyimide and BCB benzocyclobutene, provide additional protection. They can serve as a supplementary protective layer to enhance the overall passivation effect, especially in terms of resisting mechanical stress and environmental factors such as humidity and temperature changes. Organic passivation materials usually have good flexibility and ductility, can adapt to small changes in the metal surface, and reduce cracks and defects caused by thermal expansion or mechanical stress; In summary, the combined use of the inorganic passivation layer 12 and the organic passivation layer 13 can not only protect the chip surface through chemical reactions, but also enhance the overall stability and durability of the chip by physical means, which is crucial to improving the performance and reliability of electronic devices.

[0031] Further as attached Figure 1 As shown, the conductivity type of the silicon carbide substrate 3 and the silicon carbide epitaxial layer 4 are both N-type.

[0032] Further as attached Figure 1 As shown, the heights and doping concentrations of the P-type injection region 5, the P-type main junction 6 and the P-type field limiting ring 8 are the same, the widths of the multiple P-type injection regions 5 and the spacings therebetween are the same, the depths of the P-type injection region 5 and the P-type main junction 6 are set to be the same, the widths of the grooves 7 and the P-type field limiting rings 8 are the same, the depths of the P-type field limiting rings 8 are variable, and the spacings between the P-type field limiting rings 8 are variable.

[0033] Specifically, the structure achieves precise control of the device electric field and current distribution through a specific design to improve the performance and reliability of the device. Specifically, the P-type injection region 5 has the same height and doping concentration as the P-type main junction 6, and the depth is set the same, which helps to form a uniform PN junction and ensures that the current is evenly distributed when the device is working. This design can reduce hot spots caused by local high current density, thereby improving the stability of the device. The depth change and spacing change design of the P-type field limiting ring 8 can further optimize the electric field distribution, so that the electric field smoothly transitions between the active area and the terminal area of ​​the device, reduces electric field concentration, and increases the breakdown voltage. The field oxide layer 9 covering the P-type main junction 6 and the field limiting ring, in addition to playing an insulating role, also helps to protect the underlying semiconductor material from external environmental influences, such as moisture and ion contamination.

[0034] Further as attached Figure 1 As shown, the right ends of the Schottky contact metal 10 and the front thickening metal 11 are laid on the field oxide layer 9 , and the left front ends of the inorganic passivation layer 12 and the organic passivation layer 13 are laid above the front thickening metal 11 .

[0035] Specifically, the design of this structure helps to improve the stability and reliability of the device, while optimizing the electrical performance. Specifically, the right ends of the Schottky contact metal 10 and the front thickened metal 11 are built on the field oxide layer 9. Such a design can form a field plate structure, optimize the electric field distribution, reduce the electric field peak at the main junction, and increase the reverse breakdown voltage of the device. The Schottky barrier formed by the Schottky contact metal 10 and the N-type silicon carbide epitaxial layer 4 is the key to achieving the rectification function, while the front thickened metal 11 helps to improve the conductivity. The left front ends of the two passivation layers, the inorganic passivation layer 12 and the organic passivation layer 13, are built above the front thickened metal 11. Such a layout can protect the metal from corrosion and extend the service life of the device. Example 2

[0036] As attached Figure 2-5 As shown, this embodiment provides a preparation method for preparing the above-mentioned novel grooved silicon carbide chip structure, and the preparation method comprises: S1. Deposit a silicon oxide film on the surface of the silicon carbide epitaxial layer 4 using plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition technology, coat photoresist on the surface of the silicon oxide film, and pattern the film surface using grayscale photolithography technology to make the photoresist present grooves 7 with varying depths.

[0037] This step is combined with the Figure 2 As shown, specifically, a silicon oxide film is deposited on the silicon carbide epitaxial layer 4 using plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition technology, a photoresist is coated on the surface of the silicon oxide film and patterned using grayscale lithography technology, so that a complex three-dimensional structure can be achieved. Grayscale lithography technology allows grooves 7 with varying depths to be formed on the photoresist, which means that multi-level patterns can be achieved in the same step, reducing manufacturing steps and costs.

[0038] S2. Use photoresist as a mask and use inductively coupled plasma enhanced etching technology to etch the silicon oxide film and the silicon carbide epitaxial layer 4, so that the silicon carbide epitaxial layer 4 forms a groove 7 with varying depth in the field limiting ring region.

[0039] This step is combined with the Figure 3 As shown, specifically, the effect of this step is to accurately transfer the pattern on the photoresist to the silicon carbide epitaxial layer 4 through high-precision etching technology, forming a field limiting ring area with a depth-varying groove 7, which is very critical for improving the voltage resistance and reliability of the device.

[0040] S3. Using the silicon oxide layer as a masking layer, Al ion implantation is performed on the device, followed by high temperature activation annealing to form a P-type implantation region 5, a P-type main junction 6 and a P-type field limiting ring 8 with varying depth in the active region and the terminal region.

[0041] This step is combined with the Figure 3 As shown, specifically, this step forms a P-type region of the device through ion implantation and high-temperature annealing, which is crucial to improving the performance and reliability of the device.

[0042] S4. Remove the silicon oxide layer using wet etching technology.

[0043] This step is combined with the Figure 3 As shown, specifically, using wet etching technology, such as using BOE solution to remove the silicon oxide layer, can achieve precise removal of the oxide layer on the surface of the silicon carbide wafer, providing a clean working environment for subsequent semiconductor manufacturing steps.

[0044] S5. Depositing silicon oxide in the terminal region by high temperature oxidation and PECVD to form a field oxide layer 9.

[0045] This step is combined with the Figure 4 As shown, specifically, silicon oxide is deposited in the terminal region by high temperature oxidation and PECVD to form a field oxide layer 9, which can not only improve the electrical performance of the device, but also provide better process control and higher product quality during the manufacturing process.

[0046] S6. Forming a Schottky contact metal 10 on the active area and main junction of the silicon carbide chip by sputtering or evaporation, and then forming a Schottky contact metal 10 between the metal and the silicon carbide by alloying, rapid annealing or laser annealing.

[0047] This step is combined with the Figure 4 As shown, specifically, this step is crucial to ensuring the performance and reliability of electronic devices, especially in the manufacture of high-performance semiconductor devices, such as silicon carbide power devices, which have extremely strict requirements on material properties and processing technology. Through the above process steps, semiconductor devices with Schottky diodes having excellent electrical characteristics and high reliability can be manufactured.

[0048] S7. Depositing the front thickening metal 11 on the Schottky contact metal 10 by sputtering or evaporation.

[0049] S8 , depositing an inorganic passivation layer 12 on the field oxide layer 9 , and then coating an organic passivation layer 13 on the inorganic passivation layer 12 and curing it.

[0050] This step is combined with the Figure 4As shown, specifically, this step not only improves the current carrying capacity of the semiconductor device but also helps to improve the overall performance and long-term reliability of the device by introducing a microstructure layer with a specific shape on the front thickened metal 11.

[0051] S9. Form an ohmic contact metal 2 on the back side of the silicon carbide chip by sputtering or evaporation, and use laser annealing to form an ohmic contact metal 2 between the metal and the silicon carbide.

[0052] This step is combined with the Figure 5 As shown, specifically, by forming a high-quality ohmic contact metal 2 on the back of the silicon carbide chip, not only the performance of a single device can be improved, but it can also play an important role in system integration and has a significant effect on improving the efficiency and stability of the entire electronic system.

[0053] S10, forming a back thickened metal 1 on the ohmic contact metal 2 by sputtering or evaporation. At the same time, forming a microstructure layer on the front thickened metal 11 to increase the surface area of ​​the device, improve the heat dissipation performance and current carrying capacity, and the microstructure layer is realized by using a microstructure in the shape of nanoparticles, nanowires or nanocolumns.

[0054] In summary, the depth-gradient groove 7-type field limiting ring structure proposed in the present invention can change the electric field distribution by changing the depth of the field limiting ring without increasing the terminal area, thereby improving the terminal's suppression of the surface electric field and the reverse breakdown voltage of the chip. In addition, the method proposed in the present invention does not increase the manufacturing process and has a small increase in the device manufacturing cost.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A new type of trench silicon carbide chip structure, Features: A novel grooved silicon carbide chip structure comprises a back-side thickened metal (1), an ohmic contact metal (2), a silicon carbide substrate (3) and a silicon carbide epitaxial layer (4) arranged in sequence from bottom to top, wherein the top of the silicon carbide epitaxial layer (4) is provided with a P-type injection region (5) extending into the silicon carbide epitaxial layer (4), a P-type main junction (6) and a groove (7), and a P-type field limiting ring (8) below the groove (7), wherein the depth of the P-type field limiting ring (8) is variable, the spacing between the P-type field limiting rings (8) is variable, and the silicon carbide epitaxial layer (4) is provided with a field oxide layer covering part of the P-type main junction (6) and all of the P-type field limiting rings (8) (9), and the field oxide layer (9) is filled in the groove (7) of the silicon carbide epitaxial layer (4), the silicon carbide epitaxial layer (4) is provided with a Schottky contact metal (10) covering the entire P-type injection region (5) and extending to a portion of the field oxide layer (9), the Schottky contact metal (10) is provided with a front thickening metal (11), the field oxide layer (9) is provided with an inorganic passivation layer (12) extending to a portion of the front thickening metal (11), the inorganic passivation layer (12) is provided with an organic passivation layer (13), and the conductivity type of the silicon carbide substrate (3) and the silicon carbide epitaxial layer (4) are both N-type.

2. A novel grooved silicon carbide chip structure according to claim 1, Features: The heights and doping concentrations of the P-type injection region (5), the P-type main junction (6) and the P-type field limiting ring (8) are all the same, the widths of the plurality of P-type injection regions (5) are all the same, the spacings between the plurality of P-type injection regions (5) are all the same, the depths of the P-type injection region (5) and the P-type main junction (6) are set to be the same, and the widths of the groove (7) and the P-type field limiting ring (8) are the same.

3. A novel grooved silicon carbide chip structure according to claim 1, Features: The right ends of the Schottky contact metal (10) and the front thickening metal (11) are arranged on the field oxide layer (9), and the left front ends of the inorganic passivation layer (12) and the organic passivation layer (13) are arranged above the front thickening metal (11).

4. A preparation method for preparing the novel grooved silicon carbide chip structure according to claim 1, Features: The preparation method comprises the following steps: S1. Depositing a silicon oxide film on the surface of the silicon carbide epitaxial layer (4) using plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition technology, coating a photoresist on the surface of the silicon oxide film, and patterning the surface of the film using grayscale photolithography technology so that the photoresist forms grooves (7) with varying depths; S2, using a photoresist as a mask, and using inductively coupled plasma enhanced etching or reactive ion etching technology to etch the silicon oxide film and the silicon carbide epitaxial layer (4), so that the silicon carbide epitaxial layer (4) forms a groove (7) with varying depths in the field limiting ring region; S3, using the silicon oxide layer as a masking layer, performing Al ion implantation on the device, and then performing high temperature activation annealing to form a P-type implantation region (5), a P-type main junction (6) and a P-type field limiting ring (8) with varying depth in the active region and the terminal region; S4, removing the silicon oxide layer using a wet etching technique; S5, forming silicon oxide in the terminal area of ​​the silicon carbide chip by high temperature oxidation or PECVD, LPCVD deposition to form a field oxide layer (9); S6, forming a Schottky contact metal (10) on the active area and part of the main junction of the silicon carbide chip by sputtering or evaporation, and then forming a Schottky contact metal (10) between the metal and the silicon carbide by alloying, rapid annealing or laser annealing; S7, depositing a front thickening metal (11) on the Schottky contact metal (10) by sputtering or evaporation; S8, depositing an inorganic passivation layer (12) on the field oxide layer (9), and then coating an organic passivation layer (13) on the inorganic passivation layer (12) and curing the organic passivation layer (13); S9, forming an ohmic contact metal (2) on the back side of the silicon carbide chip by sputtering or evaporation, and forming an ohmic contact metal (2) between the metal and the silicon carbide by laser annealing; S10, forming a back thickened metal (1) on the ohmic contact metal (2) by sputtering or evaporation.

5. A preparation method according to claim 4, Features: The preparation method also includes the following steps: In S7, a microstructure layer is formed on the front thickened metal (11) to increase the surface area of ​​the device and improve the heat dissipation performance and current carrying capacity. The microstructure layer is implemented using a microstructure in the shape of nanoparticles, nanowires or nanocolumns.

Images