Semiconductor detector and method of manufacturing the same

Abstract

The embodiment of the invention relates to a semiconductor detector and a manufacturing method thereof. The present disclosure describes a detector for use in a critical dimension scanning electron microscope (CD-SEM) and for redetecting an SEM system. In one embodiment, a detector includes a semiconductor structure having a p-n junction and an aperture through which a scanning beam is delivered to a target. The detector also includes a top electrode (250) (e.g., an anode electrode or a cathode) for the p-n junction, the top electrode providing an effective region for detecting electrons or electromagnetic radiation (e.g., backscatter from a target). The top electrode has a doped layer (230) and a buried portion (260) underneath the doped layer to reduce the series resistance of the top electrode without changing the active area. In another embodiment, an isolation structure may be formed in the semiconductor structure near the sidewall of the hole to electrically isolate the active region from the sidewall. A method of forming a buried portion of a top electrode is also described.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the Chinese patent application with the application date of December 6, 2019, application number 201980087099.4, and name “Semiconductor detector and its manufacturing method”. Technical Field

[0003] The present disclosure relates generally to radiation detectors such as may be used in, for example, a scanning electron microscope (SEM) system. Background Art

[0004] Radiation detectors are used in a variety of applications. Here and elsewhere, the term "radiation" is used to refer to both electromagnetic waves and moving particles. For example, in a manufacturing process for making integrated circuit (IC) components, unfinished or completed circuit components are inspected to ensure that they are manufactured according to a specified design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes (such as SEMs) can be employed. As the physical dimensions of various features of IC components continue to shrink, the accuracy and yield achieved by these detection systems become more important. Currently, these systems are often limited, at least in part, by the sensitivity and speed of semiconductor radiation detectors, or simple semiconductor detectors, which are used to detect backscattered electrons or secondary electrons from the target being inspected. Therefore, there is a great need to improve the performance of semiconductor detectors. Summary of the invention

[0005] A simplified summary of one or more aspects of various embodiments of the present disclosure is presented below to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or important elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0006] Aspects of one embodiment describe a detector having a semiconductor structure with an aperture through which a scanning light beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active area for detecting electrons or electromagnetic radiation, wherein the top electrode includes a doped layer and a buried portion below the doped layer, wherein the buried portion is configured to reduce a series resistance of the top electrode without changing the active area provided for detection.

[0007] Aspects of another embodiment describe a detector having a semiconductor structure with an aperture through which a scanning light beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active area for detecting electrons or electromagnetic radiation, and wherein the top electrode includes a doped layer. The detector also has an isolation structure formed in the semiconductor structure near a sidewall of the aperture, wherein the isolation structure is configured to electrically isolate the active area from the sidewall of the aperture.

[0008] Aspects of yet another embodiment describe a detector having a semiconductor structure with an aperture through which a scanning light beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active area for detecting electrons or electromagnetic radiation, wherein the top electrode includes a doped layer and a buried portion below the doped layer, wherein the buried portion is configured to reduce a series resistance of the top electrode without changing the active area provided for detection. The detector also has an isolation structure formed in the semiconductor structure near a sidewall of the aperture, wherein the isolation structure is configured to electrically isolate the active area from the sidewall of the aperture.

[0009] Aspects of yet another embodiment describe a method for forming a buried portion of a top electrode in a semiconductor detector, the method comprising depositing a dopant layer on a surface of a semiconductor structure having an active area of ​​a top electrode, and then applying a heat treatment to drive dopants from the dopant layer into the semiconductor structure and beneath a detection layer of the top electrode to form the buried portion of the top electrode.

[0010] According to another aspect of another embodiment, a method of manufacturing a semiconductor detector is disclosed, the semiconductor detector including an element for generating an electrical signal in response to receiving radiation and a circuit system electrically connected to the element, the circuit system including at least one structure that cannot withstand a processing temperature exceeding a temperature T, the method comprising the following steps: manufacturing a first portion of the circuit system, the first portion being able to withstand the temperature T; performing a processing step at the temperature T; and manufacturing a second portion of the circuit system, the second portion including a structure that cannot withstand the temperature T. Performing the processing step at the temperature T may include performing a high temperature chemical vapor deposition. Performing the high temperature chemical vapor deposition may include performing a high temperature chemical vapor deposition of boron. Performing the high temperature chemical vapor deposition of boron may include a high temperature chemical vapor deposition of pure boron. Manufacturing the first portion of the circuit system may include partial manufacturing of the CMOS circuit system. Manufacturing the second portion of the circuit system includes complete manufacturing of the CMOS circuit system. The temperature T may be above 700°C.

[0011] According to another aspect of another embodiment, a method for manufacturing a semiconductor detector is disclosed, which includes an element for generating a signal in response to receiving radiation and a CMOS circuit system electrically connected to the element, the CMOS circuit system including at least one structure that cannot withstand a processing temperature T exceeding 700°C, the method comprising the following steps: manufacturing a first portion of the CMOS circuit system, the first portion being able to withstand temperature T; performing an HT PureB CVD processing step at temperature T; and manufacturing a second portion of the CMOS circuit system, the second portion including a structure that cannot withstand temperature T.

[0012] According to another aspect of another embodiment, a process for manufacturing a single-die image semiconductor radiation detector is disclosed, the process comprising the following steps: providing a starting wafer; performing a first partial circuit forming step on a processed side of the starting wafer to form a first partial circuit layer, the first partial circuit forming step being limited to forming a circuit system that can withstand a processing temperature T; bonding a first bonded wafer to the first partial circuit layer; etching away a portion of the starting wafer to expose the first partial circuit layer; depositing a boron layer on the first partial circuit layer; bonding a second bonded wafer to the boron layer; unbonding the first bonded wafer from the first partial circuit layer; performing a second partial circuit forming step on the first partial circuit layer to form a completed circuit layer, the second partial circuit forming step including forming a circuit structure that cannot withstand the processing temperature T; bonding a third bonding layer to the completed circuit layer; and unbonding the second bonded wafer from the boron layer. Performing the first partial circuit forming step may include performing a first partial CMOS circuit forming step. Performing the second partial circuit forming step on the first partial circuit layer to form a completed circuit layer may include performing the second partial CMOS circuit forming step on the first partial circuit layer to form a completed CMOS circuit layer. Depositing the boron layer on the first partial circuit layer includes using HT PureB CVD. The temperature T may be higher than 700°C.

[0013] According to another aspect of another embodiment, a single-die semiconductor detector is disclosed, which includes an element for generating a signal in response to receiving radiation and a CMOS circuit system electrically connected to the element, the CMOS circuit system including at least one structure that cannot withstand a processing temperature T exceeding 700°C, and the detector is manufactured by a method including the following steps: manufacturing a first part of the CMOS circuit system, the first part can withstand temperature T; performing an HT PureB CVD processing step at temperature T; and manufacturing a second part of the CMOS circuit system, the second part including a structure that cannot withstand temperature T.

[0014] To achieve the foregoing and related purposes, aspects of the embodiments include the features described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are merely indicative of several of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A is a diagram showing a semiconductor detector in a SEM system.

[0016] Figure 1B is a diagram showing a semiconductor detector in an off-axis SEM system.

[0017] Figure 2A is a diagram showing a partial cross-sectional view of a semiconductor detector with an external Al grid on a top electrode according to some aspects of the present disclosure.

[0018] Figure 2B is a diagram showing a partial cross-sectional view of a semiconductor detector with a buried portion of a top electrode according to some aspects of the present disclosure.

[0019] Figure 2C is a diagram showing a partial cross-sectional view of a semiconductor detector having a buried portion of a top electrode and a capping layer according to some aspects of the present disclosure.

[0020] Figure 3 is a diagram of simulated electron position distribution on a detector plane according to some aspects of the present disclosure.

[0021] Figure 4A is a diagram showing a partial cross-sectional view of a semiconductor detector having a large "dead zone" around its aperture, according to some aspects of the present disclosure.

[0022] Figure 4B and 4C is a diagram showing a partial cross-sectional view of semiconductor detectors having isolation structures to create small "dead zones" around their apertures according to some aspects of the present disclosure.

[0023] Figure 5A is a diagram illustrating an example of a top view of a buried portion of a top electrode in which a plurality of buried segments are arranged in a radial configuration according to some aspects of the present disclosure.

[0024] Figure 5B is a diagram illustrating an example of a top view of a buried portion of a top electrode in which a plurality of buried segments are arranged in a grid configuration according to some aspects of the present disclosure.

[0025] Figure 6is a flow chart illustrating an example of a method of forming a buried portion of a top electrode in a semiconductor detector according to some aspects of the present disclosure.

[0026] Figure 7 is a diagram illustrating an example of a method of forming a semiconductor detector according to some aspects of the present disclosure.

[0027] Figures 8A-8D is a diagram illustrating an example of a method of forming a semiconductor detector according to some aspects of the present disclosure.

[0028] Fig. 9 is a flow chart illustrating an example of a method of forming a semiconductor detector according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0029] As described above, inspection systems such as SEMs using optical microscopes or charged particle (e.g., electron) beam microscopes can be used to inspect completed or unfinished IC components (e.g., semiconductor wafer or die inspection). As the critical dimensions of IC components continue to shrink, resulting in an increasing number of transistors, and as the overall yield of the inspection system is also pushed up, the accuracy, yield, and speed achieved by these inspection systems become more important. One of the key components of these systems is a semiconductor detector, which is used to analyze any errors or inconsistencies generated in the manufacturing process by detecting backscattered or secondary electrons from the inspected target. With higher yields, more sensitive or faster semiconductor detectors can help ensure that enough information is detected at a higher speed. Semiconductor detectors with improved sensitivity or higher bandwidth or other features described herein can enable the accuracy, yield, or speed of the inspection system to be improved. The present disclosure describes various techniques, such as techniques for improving the sensitivity of semiconductor detectors, for example, by increasing their effective area, or techniques for improving the bandwidth of semiconductor detectors, for example, by reducing their series resistance to shorten their time constants.

[0030] Reference will now be made in detail to example aspects of the embodiments, examples of which are illustrated in the accompanying drawings. The following descriptions all refer to the accompanying drawings, and unless otherwise specified, the same reference numerals in different drawings represent the same or similar elements. The implementations set forth in the following description of example aspects of the embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of structures and processes consistent with various aspects of the embodiments related to the disclosure recorded in the claims. For example, although some aspects of the present disclosure are described in the context of an inspection system using electronic scanning and detection, these aspects may also be applicable to other types of inspection systems.

[0031] Figure 1AFIG. 100a is shown illustrating a general representation of an SEM system (e.g., an inspection system). An SEM system may also be referred to as an electron beam (e-beam) system. FIG. 100 includes a source 110 that provides a scanning beam 115 (e.g., an electron beam) that passes through an aperture 125 of a detector 120 (e.g., a semiconductor detector) and is aimed at a target 130 (e.g., a wafer or die being inspected). The aperture 125 may be located at the center of the detector 120, or at some other location of the detector 120. Because the detector 120 is aligned between the source 110 and the target 130, the detector 120 may be referred to as an in-lens detector. The axis formed by the source 110 and the detector 120 being positioned in a vertical direction may be referred to as the optical axis of the SEM system.

[0032] The scanning beam 150 is used to characterize one or more features on the top surface of the target 130, thereby causing backscattered or secondary electrons 135, which reach the downward facing surface of the detector 120 for detection. Based on the electrons 135 received by the detector 120, the detector 120 can then generate and provide a signal (not shown) that conveys information associated with the inspected features of the target 130, where the information is then used to generate a SEM image of the scanned target. In some implementations, more than one scanning beam 150 can be generated and provided by the source 110 to allow inspection of multiple targets.

[0033] Figure 1B A diagram 100b illustrating a general representation of an off-axis SEM system is shown. In this example, the detector 120 may be placed in a secondary axis 170 that is different from the primary axis 140 of the scanning beam 115. In this case, the detector 120 may be referred to as an off-axis detector and need not have an aperture 125 through which the scanning beam 115 passes.

[0034] The SEM system shown in FIG100b also includes a source 110 (or a similar electron or radiation source), a gun hole plate 145, a condenser lens 150, a source conversion unit 155, a main projection system 160, and a target 130, all of which are aligned with the main axis 140. A beam splitter 175 and a deflection scanning unit 180 can be placed inside the main projection system 160. The main projection system 160 can also include an objective lens 185. The SEM system in FIG100b also includes an auxiliary imaging system 165 aligned with the auxiliary axis 170 together with the detector 120.

[0035] The beam splitter 175 can be configured to deflect the secondary electrons 135 (e.g., or a beam having the secondary electrons 135) at an angle α in the direction of the auxiliary imaging system 165. The angle α can be determined as the angle between the primary axis 140 and the secondary axis 170, and thus, the angle α can represent the separation angle between the on-axis scanning beam 115 and the secondary electrons 135 directed by the beam splitter 175 in the direction of the auxiliary imaging system 165 and the off-axis detector 120. In some implementations, the angle α can be set in the range of 5 to 25 degrees.

[0036] The current in-lens or off-axis detector 120 can be a secondary electron (SE) detector that includes a single silicon PIN photodiode having a diameter of about 20 millimeters (mm) and having an aperture 125 having a diameter of about 0.5 mm for the primary electron beam to pass through (e.g., scanning beam 115). In the present disclosure, the terms "about" or "approximately" when used may refer to a value relative to a nominal value, wherein the difference between the two values ​​may be less than 1%, between 1% and 5%, between 1% and 10%, or between 1% and 20%.

[0037] There is typically about 50 nanometers (nm) of aluminum (Al) coating over the surface of the PIN photodiode to increase the series resistance as well as to reflect any stray light (eg, light from the laser and scattered inside the column of the SEM system).

[0038] The use of semiconductor detectors for detector 120 (e.g., a single silicon PIN photodiode) has been primarily used as in-lens detectors for electron beam (e-beam) wafer inspection systems. On the other hand, Everhart-Thornley detectors (ET detectors), which consist of a scintillator and a photomultiplier tube (PMT) cell, have been used in critical dimension SEM (CD-SEM) and re-detection SEM systems. By using semiconductor detectors instead of ET detectors, wafer inspection systems can typically image at 10 to 100 times higher beam currents and high detection bandwidths, thereby operating with high detection throughput. Therefore, although semiconductor detectors may have a relatively higher noise floor than ET detectors, they become a natural choice due to their superior bandwidth and robustness against radiation damage.

[0039] With the continued miniaturization of semiconductor wafer designs (e.g., reduction in critical dimension or CD), even electron beam wafer inspection systems now often operate at very low beam currents to ensure the necessary resolution of SEM images. As this trend continues, the noise floor of semiconductor detectors used for SEM scanning must be reduced to prevent the SNR from exceeding the small output currents produced by the semiconductor detectors.

[0040] In a typical wafer inspection system, a delayed objective SEM column configuration is used, where the wafer being inspected (e.g., target 130) is biased to a negative high voltage at Vw to achieve a landing energy (Vle) of V volts to comply with the following expression:

[0041] Vle=Vc-Vw,

[0042] Where Vc is the accelerating voltage of the electron beam cathode. Secondary electrons (eg, electrons 135) emitted from the wafer surface in response to the scanning beam 115 are accelerated to (Vc-Vw) eV and strike the surface of the detector 120 with such kinetic energy.

[0043] In one example, the cathode voltage Vc can be -10 kilovolts (KV) or greater so that the kinetic energy of electrons (e.g., electrons 135) entering the detector 120 is kept above 8KeV at a minimum. Electrons arriving at the surface of the detector 120 must reach the depletion region that passes through the p++ layer and the np junction thickness as well as the top aluminum coating used to reflect scattered photons. If the electron kinetic energy drops below 8KeV, the quantum efficiency drops sharply because the signal current change per electron is reduced, thereby deteriorating the SNR of the SEM image. However, in some cases, it is desirable to keep the cathode voltage below 6KV for specific requirements of constructing the SEM system as well as system reliability and cost. In these cases, the detector 120 may need to allow most of the incoming electrons to reach the depletion region with minimal energy loss, thereby minimizing the SEM image SNR degradation.

[0044] Although off-axis detectors (e.g. Figure 1B The detector 120 in the secondary axis of the schematic diagram 100b of FIG. 100b) need not have a hole, but an in-lens or on-axis detector (e.g., in FIG. 100b) may be used. Figure 1A The in-lens detector 120 in schematic 100a requires an aperture (e.g., aperture 125) for the primary electron beam (e.g., scanning beam 115) to pass through, where the distance between the aperture inner diameter (ID) surface and the effective detection surface must be properly designed to minimize additional dark current.

[0045] As described above, the detectors of electron beam inspection systems need to support high bandwidth for high inspection throughput, where relatively large beam currents are employed. The bandwidth of the detector depends at least in part on the junction capacitance and the series resistance. Therefore, if a delayed objective SEM column is to be used with a cathode voltage fixed at a low value (such as 6KV), the series resistance needs to be reduced or lowered to provide a shorter time constant (e.g., faster response, higher bandwidth) for the in-lens detector without reducing the likelihood that electrons reaching the detector surface also reach the depletion region to maintain high quantum efficiency.

[0046] For CD-SEM applications, there are several challenges related to detector design that need to be addressed. For CD-SEM applications, low beam or probe currents are required to maintain good resolution, resulting in very low total beam dose. In this case, it is necessary to have very low circuit noise levels to maintain acceptable SNR and therefore good image quality. The noise performance of existing PIN photodiode detectors combined with preamplifier circuits cannot meet these requirements. In current preamplifier designs, the detector capacitance is an important factor that affects not only the bandwidth but also the noise.

[0047] To address at least some of these issues, a thin layer can be added to the detector to improve the collection efficiency. In some implementations, the thin layer includes boron (B), and the detector with the boron layer can be referred to as a pure B detector. The boron layer is typically a few nanometers of pure or nearly pure amorphous boron. Layers that use other elements in pure or nearly pure form and provide similar functions to the pure boron layer can also be used. However, such a detector must still meet the requirements of low capacitance and fast response time. Due to the low beam or detection current, low landing energy, and high bandwidth requirements, the corresponding signal generated by the detector 120 (e.g., secondary electrons or SE electrons) is much lower than existing platforms. Therefore, it is desirable to keep the collection efficiency of the detector as high as possible - due to the unique design characteristics of the boron layer, the boron layer proposed in the pure B detector meets this problem - and maximize the fill factor (e.g., the detection area or active area of ​​the detector) by reducing any unused or dead area, which can include any "safety margin" from the active area to the edge of the hole 125 and any isolation area between different segments of the detector.

[0048] In some cases, secondary or backscattered electrons from the top surface of target 130 will be accelerated back by a field of about 5 KeV along the optical axis. The spatial distribution of secondary electrons on the surface of detector 120 is approximately Gaussian in shape (see, e.g. Figure 3 ), although the spread of the curve depends on the operating conditions, the distribution is centered on the optical axis. In order to increase the signal power, and thus improve the SNR, it is preferred to make the dead zone as small as possible while still maintaining a low leakage current.

[0049] One aspect of using a pure boron layer as applied to electron detection is the high sheet resistance of the nano-thin boron layer (e.g., on the order of 10 kΩ x cm). For fast response electron detectors, a low series resistance on the top electrode (e.g., the anode electrode) is generally preferred so that together with a low capacitance per unit area, a faster response time can be achieved. A current solution to reduce the series resistance of a pure B layer on the top electrode is to form an aluminum (Al) grid on top of the boron layer (see, e.g., Figure 2A), which results in loss of the active area, as electrons falling on the aluminum grid do not reach the depletion region and are not detected. The aluminum grid also creates topography on the active area, which can interfere with the detection of incoming electrons.

[0050] Figure 2A FIG. 200a shows a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having an external aluminum (Al) grid 240 on a top electrode 250. The semiconductor detector may be an in-lens / on-axis semiconductor detector (see, e.g., Figure 1A ) or off-axis semiconductor detectors (see e.g. Figure 1B ). In diagram 200a, the detector 120 includes a semiconductor structure 210 (e.g., a silicon-based photodiode) and a top electrode 250. The semiconductor structure 210 may be a high resistivity (HR) semiconductor layer and include a pn junction (not shown) that creates a depletion region (not shown). The pn junction may be a pin junction for forming a PIN photodiode in the semiconductor structure 210. Figure 2A The isolation layer 220 is between the top electrode 250 and the semiconductor structure 210 .

[0051] The top electrode 250 provides an active area 245 for detecting electrons (or electromagnetic radiation). That is, the top electrode 250 is placed on the surface of the detector 120 that faces the target 130 and receives secondary or backscattered electrons 135 from the target 130. The top electrode 250 includes a doped layer 230, which can be referred to as a detection layer, which can then be doped with pure boron to provide the above-mentioned boron layer for improving the collection efficiency of the detector 120.

[0052] As described above, by using the aluminum grid 240, a loss of active area 245 is caused because the aluminum grid 240 prevents electrons that fall on the aluminum grid 240 from reaching the depletion region of the pn junction and are not detected. In addition, the aluminum grid 240 also creates topography (e.g., height variations on the surface of the detector 120) on the active area, which may interfere with the detection of incoming electrons.

[0053] An alternative is to form a "buried grid" or "buried portion" of the top electrode 250 (see, e.g. Figure 2B ). The buried grid is expected to be a better solution than the aluminum grid 240 to reduce the series resistance of a photodiode having a boron layer (e.g., doped layer 230) because it will not cause losses in the active or detection area 245, there will be no topography on the active area 245, and no soft material such as aluminum will be used on the active area 245.

[0054] Figure 2BFIG. 200 b is shown illustrating a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having a buried portion 260 of a top electrode 250. In this example, the aluminum grid 240 shown in FIG. 200 a is not present. Instead, the top electrode 250 includes a doped layer 230 (e.g., a boron layer or other layer having a similar function) and a buried portion 260 below the doped layer 230, wherein the buried portion 260 is configured to reduce the series resistance of the top electrode 250 without changing the active area 245 provided for detection.

[0055] In various aspects of one embodiment, for Figure 2B The semiconductor detector in the embodiment of the present invention, the semiconductor structure 210 is a silicon-based semiconductor structure, the top electrode 250 is an anode electrode, and the doping layer 230 is doped with a p-type dopant. The buried portion 260 of the top electrode 250 is formed by heat treatment of the same type of dopant as the doping layer 230 (see, for example, Figure 6 ). Thus, in this case, the buried portion 260 of the top electrode 250 is a low resistivity (LR) p-type region, while the semiconductor structure 210 is a high resistivity (HR) n-type layer. The dopant used to form the buried portion 260 of the top electrode 250 can be deposited onto the semiconductor structure 210 by various types of implantation processes, one of which can be a chemical vapor deposition (CVD) process. In addition, as described above, the p-type dopant of the doping layer 230 includes boron. In some implementations, the p-type dopant of the doping layer 230 can be a different element (or a composite element or alloy), which can be at least partially selected from, for example, the same periodic table column as boron.

[0056] In aspects of another embodiment, for Figure 2B In the semiconductor detector of FIG. 2 , the semiconductor structure 210 is again a silicon-based semiconductor structure, the top electrode 250 is now a cathode electrode, and the doped layer 230 is doped with an n-type dopant. In this embodiment, the doped layer 230 is not a boron layer because it is doped n-type, but when the top electrode 250 is an anode electrode, it plays the same or similar role as the boron layer. The buried portion 260 of the top electrode 250 is again formed by contacting the doped layer 230 (see, for example, FIG. 2 ). Figure 6 ) is formed by heat treatment of the same type of dopant as that of the top electrode 250, and the dopant for forming the buried portion 260 of the top electrode 250 can also be deposited on the semiconductor structure 210 by a CVD process. Therefore, in this case, the buried portion 260 of the top electrode 250 is an LR n-type region, and the semiconductor structure 210 is an HR p-type layer. The same type of dopant for the buried portion 260 of the top electrode 250 and the doping layer 230 can be different n-type dopants. In addition, the n-type dopant of the doping layer 230 can include one or more of arsenic, phosphorus, or antimony.

[0057] from Figure 2A and 2B As can be understood from the corresponding Figures 200a and 200b in the top electrode 250, the top electrode 250 may also include a top electrode metal contact 270, which is arranged above the periphery of the semiconductor structure 210 and partially overlaps the doping layer 230 of the top electrode, wherein the buried portion 260 of the top electrode 250 makes the current generated by the pn junction through the detection of electrons (or electromagnetic radiation) available at the top electrode metal contact 270.

[0058] Alternatively or additionally, the goal of reducing the series resistance of the top electrode 250 can be achieved by covering the pure boron layer (e.g., doped layer 230) of the top electrode 250 with a thin low resistivity (LR) layer and / or with a controlled top electrode (e.g., anode electrode) doping drive-in (e.g., when the top electrode 250 is an anode electrode). For the electron energies of interest, the corresponding reduction in electron relative gain is expected to be negligible, so this approach should not affect the collection efficiency in any significant way. These three alternative options, namely: using a buried grid or buried portion, a thin LR capping layer, and a top electrode drive-in, can be used individually or in some combination to reduce the series resistance of the detector 120.

[0059] Figure 2C FIG. 200c is shown illustrating a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having a buried portion 260 of a top electrode 250 and a capping layer 280. As shown in FIG. 200c, the capping layer 280, which may include one or more LR layers, is disposed over the doped layer 230. Furthermore, the capping layer 280 may be made of a conductive material.

[0060] It should be understood that Figures 2A-2C Each of the semiconductor detectors shown may be a secondary electron (SE) detector configured to detect secondary electrons and / or backscattered electrons from a target (e.g., target 130), or may be a radiation detector configured to detect electromagnetic radiation generated by or backscattered from a target (e.g., target 130).

[0061] Another relevant aspect of the present disclosure that has a direct impact on the performance of a particular electron detector is the extent of the "dead zone" around the aperture (e.g., aperture 125 in diagram 100 in FIG. 1) through which the primary beam (e.g., scanning beam 115) passes. Ideally, this dead zone should be as small as possible because the secondary electron (SE) position distribution is heavily concentrated around the aperture. Figure 3A diagram 300 of a simulated electron position distribution on the detector plane is shown, where it is apparent that most electrons arrive at the center of the detector and the larger the "dead zone" around the aperture, the fewer electrons will be detected. Therefore, another aspect of the present disclosure is to minimize any "dead zone" in the detector 120 to improve its overall efficiency and / or sensitivity.

[0062] In existing semiconductor detector designs, the limitation on reducing this "dead zone" is the lateral extent of the deep depletion region required for fast response (e.g., reduced junction capacitance). In fact, it is preferred that the depletion layer does not reach the surface of the hole 125 to prevent a significant increase in leakage current (e.g., in the segment of the detector 120 closest to the hole 125).

[0063] Figure 4A Figure 400a illustrates a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having a large "dead zone" 410a around the hole 125. The "dead zone" 410a of this example covers the area between the top electrode metal contact 270 of the top electrode 250, where the area includes the hole 125 and the adjacent area. In this example, the first layer 420 and the second layer 425 form a pn junction that produces a depletion region 427 with a certain depletion length (e.g., the depth or thickness of the depletion region 420) that extends into the second layer 425 based on the applied reverse bias, where the depletion length is large enough to reduce the junction capacitance of the pn junction in the semiconductor structure 210. This increases the response time and bandwidth of the semiconductor detector. In some implementations, the first layer 420 is a p-type doped layer and the second layer 425 is an n-type doped layer (e.g., a high resistivity n-type device layer), while in other implementations, the first layer 420 is an n-type doped layer and the second layer 425 is a p-type doped layer. However, large depletion region 427 also extends laterally. To prevent it from reaching sidewalls 430 of hole 125 and causing increased leakage current, top electrode 250 is configured so that its active area begins away from hole 125, creating the large "dead zone" 410a found in prior semiconductor detector designs.

[0064] The present disclosure proposes a different approach than that described in Figure 400a. Figure 4B and 4C Figures 400b and 400c are partial cross-sectional views of semiconductor detectors (e.g., detector 120) having isolation structures to create small or smaller "dead zones" around their apertures 125. For example, the "dead zones" 410b in Figure 400b and the "dead zones" 410c in Figure 400c are smaller than the "dead zones" 410a in Figure 400a.

[0065] For example, in Figure 400b, an isolation structure 440 is included in the semiconductor structure 210 to isolate the depletion region 427 from the sidewalls 430 of the hole 125. The isolation structure 440 is formed near the sidewalls 430 of the hole 125 and includes a deep trench 445 with doped sidewalls 450 to provide a defect-free stopping plane that limits the lateral extension of the depletion region 420 in the direction of the hole 125. The deep trench 445 can be filled with, for example, an insulating material, such as a dielectric material (e.g., an oxide). The doping of the doped sidewalls 450 can be, for example, a doping or doping type opposite to the doping or doping type of the second layer 425. This allows the "dead zone" 410 between the hole 125 and the active area provided by the top electrode 250 to be reduced to tens of microns, and therefore, it is expected that having a smaller "dead zone" 410 will provide significant improvements in the detection of secondary electrons and / or backscattered electrons (e.g., electrons 135). In this example, the distance between the isolation structure 440 and the sidewall 430 of the hole 125 may be less than 60 micrometers. Thus, the isolation structure 440 having the deep trench 440 and the sidewall 450 may be substantially parallel to the sidewall 430 of the hole 125 but not contacting it.

[0066] In diagram 400c, an isolation structure 460 is included in the semiconductor structure 210 to isolate the depletion region 420 from the sidewalls 430 of the hole 125. The isolation structure 460 is formed very close to the sidewalls 430 of the hole 125 and includes a doped layer that is substantially parallel to and adjacent to the sidewalls 430 of the hole 125 and limits the lateral extension of the depletion region 427 in the direction of the hole 125. That is, the material, doping and / or structural characteristics of the isolation structure 460 are configured to limit the lateral extension of the depletion region 427 to be as close as possible to the sidewalls 430 of the hole 125. This allows for a reduction in the "dead zone" 410c between the hole 125 and the active area provided by the top electrode 250, and improves the detection of secondary electrons and / or backscattered electrons (e.g., electrons 135). In this example, the distance between the isolation structure 460 and the sidewalls 430 of the hole 125 can be less than 1 micron. However, in some cases, isolation structure 460 may be in direct contact with sidewall 430 of hole 125 .

[0067] Combined with the above Figure 2B As in the described embodiment, Figure 4B and 4CThe semiconductor detector (e.g., detector 120) in FIG. 1 may have a semiconductor structure 210 that is a silicon-based semiconductor structure, a top electrode 250 that is an anode electrode, and a doping layer 230 doped with a p-type dopant (e.g., boron), or alternatively, have a semiconductor structure 210 that is a silicon-based semiconductor structure, a top electrode 250 that is a cathode electrode, and a doping layer 230 doped with an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony). In each of these cases, the buried portion ( Figure 4B and 4C ) may be formed by heat treating the same type of dopant as that of the doping layer 230.

[0068] In addition to the various features described above, a semiconductor detector (e.g., detector 120) can have multiple segments. In each segment, a new anode electrode (or cathode electrode) with position sensing function is introduced, which will allow the resolution of electrons collected by the same segment. Different resolution profiles can be used, as described below.

[0069] For example, Figure 5A Figure 500a shows a top view of an example of a buried portion 260 of a top electrode 250, wherein a plurality of buried segments are arranged in a radial configuration. That is, the buried portion 260 of the top electrode 250 includes a plurality of buried segments in the active area 245 provided by the top electrode 250, and the segments are arranged to form a radial configuration as shown in Figure 500a.

[0070] In another example, Figure 5B FIG500b is a top view of an example of a buried portion 260 of a top electrode 250, wherein a plurality of buried segments are arranged in a grid configuration. That is, the buried portion 260 of the top electrode 250 includes a plurality of buried segments in the active area 245 provided by the top electrode 250, and the segments are arranged to form a grid configuration as shown in FIG500b.

[0071] In other examples, the individual segments forming the buried portion 260 of the top electrode 250 need not be as shown in FIG. 500a ( Figure 5A ) and 500b( Figure 5B ) cross each other as in the example in FIG. ). For example, each segment may include a plurality of lines (e.g., straight lines, curves) that do not overlap, cross each other, and / or touch each other. In addition, each segment forming the buried portion 260 of the top electrode 250 may include a similar structure to FIG. 500a ( Figure 5A ) of the radial configuration shown in these curved segments, similar to FIG. 500b ( Figure 5B )'s grid configuration, or a combination of both curved and straight segments.

[0072] The buried portion 260 of the top electrode 250, whether configured in a radial configuration, a grid configuration, or some other configuration, is formed by thermally treating the same type of dopant as the doped layer 230, where in some cases the dopant is the same, but not always (see, e.g., Figure 2B description).

[0073] Figure 6 is a flow chart illustrating an example of a method 600 of forming a buried portion 260 of a top electrode 250 in a semiconductor detector (eg, the detector 120 ).

[0074] Method 600 includes depositing a dopant layer on a surface of a semiconductor structure (eg, semiconductor structure 210) having an active region (eg, active region 245) of top electrode 250 at 610. The dopant layer is different from doping layers such as doping layer 230.

[0075] The method 600 optionally includes depositing a capping layer (eg, capping layer 280) over the dopant layer at 620, wherein the capping layer is deposited before applying the thermal treatment. Typically, the capping layer is a dielectric layer.

[0076] The method 600 includes, at 630 , applying a thermal treatment (eg, heat treatment) to drive dopants from the dopant layer into the semiconductor structure and below the detection layer (eg, doping layer 230 ) of the top electrode 250 to form a buried portion 260 of the top electrode 250 .

[0077] In one aspect of method 600 , depositing the dopant layer includes depositing the dopant layer by a CVD process.

[0078] In another aspect of method 600, top electrode 250 may be an anode electrode and the dopant in the dopant layer may include a p-type dopant (eg, boron). Additionally, the dopant of the detection layer may be the same dopant type as the dopant layer.

[0079] In another aspect of method 600, top electrode 250 may be a cathode electrode and the dopant in the dopant layer may include an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony). In addition, the dopant of the detection layer may be the same dopant type as the dopant layer.

[0080] In another aspect of method 600 , the semiconductor detector may be a SE detector or a radiation detector.

[0081] According to the description provided above in conjunction with Figures 1-6, an implementation supported by the present disclosure includes a detector having: a first layer of a first conductivity type on a first side of a substrate (e.g., a p-type doped layer), which is used to form an anode electrode to receive secondary electrons of a scanning electron microscope (SEM) inspection system; a buried portion of the first conductivity type on the first side of the substrate (e.g., buried portion 260), which is used to reduce the series resistance of the anode electrode; and a second layer of a second conductivity type (e.g., an n-type doped layer), which is used to enable the formation of a pn diode including the first layer and the second layer. In another aspect of this implementation, the formation of the buried portion may include implanting a dopant into the substrate, wherein the dopant may be, for example, boron. In addition, the buried portion may form a grid (see, for example, Figure 5A ) or other configurations.

[0082] In another implementation supported by the present disclosure, a substrate includes: a semiconductor structure (e.g., semiconductor structure 210) having a hole (e.g., hole 125), wherein the semiconductor structure also has a deep trench isolation (e.g., isolation structure 440) surrounding the hole; a first layer of a first conductivity type (e.g., a p-type or n-type doped layer) on a first side of the semiconductor structure, which is used to receive secondary electrons of a SEM system; and a second layer of a second conductivity type (e.g., an n-type or p-type doped layer) which is used to enable a pn diode including the first layer and the second layer to be formed in the semiconductor structure, wherein the second layer is adjacent to the deep trench isolation.

[0083] As described above, in an imaging system that detects backscattered electrons, it is highly desirable to have a detector that can detect electrons reliably and quickly. Such a detector ideally combines on a single die a detector that detects the electrons, i.e., a detector that generates a signal in response to receiving the electrons, and a circuit system that receives the signal. However, there is a problem. In order to make the detector fast, it is desirable to use a step in the manufacturing process called HT PureB CVD, which stands for High Temperature Pure Boron Chemical Vapor Deposition. As the name implies, this step involves exposing the wafer on which the circuit system is formed to very high temperatures. It is also desirable to use a circuit system called CMOS circuit system. Unfortunately, these high temperatures exceed the temperatures that CMOS circuit systems can withstand. This has represented a fundamental incompatibility in the past. According to one of the disclosures herein, this fundamental incompatibility is addressed by dividing the formation of the circuit system into two parts: (1) a first part that involves creating only structures that can tolerate the subsequent high temperature step; and (2) a second part performed after the high temperature step, in which structures that could not survive the earlier high temperature step can be safely manufactured. Thus, according to one aspect, the HT PureB CVD process steps are integrated into a standard BSI CMOS process to allow the production of highly sensitive, robust, radiation-hardened, very fast and energy-efficient detectors / imagers and readout electronics. In other words, the resulting detectors will have higher sensitivity, faster response times and higher signal-to-noise ratios for optimal image quality. The process also allows for more functionality within the detector.

[0084] In other words, as described above, according to one aspect of the embodiment, the in-lens SE detector can be configured as a single silicon PIN detector with a central hole to allow the original electron beam to pass through. There is an aluminum coating on top of the diode surface to increase the series resistance and reflect stray light from the laser beam scattered in the column. The SE detector is the first stage of the entire image channel, and its signal-to-noise ratio (SNR) determines the upper limit of the SNR of the rest of the channel.

[0085] There is technology to produce single-die imagers for low penetration depth radiation (such as EUV / DUV photons and low energy electrons) using a low temperature (LT) PureB process and a standard CMOS process, see U.S. Patent No. 9,331,117, entitled "Sensor and Lithographic Apparatus," issued on May 3, 2016, the disclosure of which is incorporated herein by reference in its entirety. The integration of the LT PureB process with a standard CMOS process allows the creation of multi-pixel detectors (imagers) on a single die for imaging low penetration depth radiation. However, the LT PureB process is characterized by a very high sheet resistance, which makes high speed imaging impossible.

[0086] There is a technical need for extremely fast pixelated radiation detectors capable of detecting low energy (low penetration depth) electrons. One solution to create such a detector is to combine the HT PureB process with a standard CMOS process on a single silicon die. The HT PureB process provides a shallow pn junction for detecting any low penetration depth particles: charged and uncharged photons, such as DUV and EUV photons, or low energy electrons, for which the PureB technology (CVD boron deposition on crystalline silicon) facilitates high readout speeds, and a thin and dense protective and passivating amorphous boron layer on top of the silicon. Placing the CMOS readout electronics on the same silicon die with the radiation response elements shortens the signal path, reduces parasitic resistance and capacitance, and enables energy efficient and very fast signal processing.

[0087] However, one technical challenge in achieving these benefits is that the temperatures used for chemical vapor deposition (CVD) of boron on silicon in the HT PureB process are typically above 700° C. Such temperatures could damage CMOS components if processed first.

[0088] According to one aspect of the embodiment, the technical challenges are overcome by dividing the CMOS processing of the die into two parts: (1) a first part to be performed before the HT CVD of pure boron, and (2) a second part to be performed after the HT CVD of pure boron. The CMOS structure created before the HT CVD boron is selected to be a structure that can tolerate further die processing at temperatures up to 800°C. Next, the HT PureB CVD process is implemented (e.g., at approximately 750°C), followed by the remaining, non-temperature-resistant steps of the CMOS process. In this way, the sequence of wafer processing steps with respect to temperature can be arranged so that each step uses a lower temperature than the previous step.

[0089] One way to implement this processing sequence uses temporary wafer bonding-debonding. Figure 7An example of the overall processing sequence of a single-die CMOS image sensor (CIS) with integrated HT CVD of boron using temporary wafer bonding-debonding is shown in FIG. The process starts with an initial structure 700, which is a starting wafer W1. Next, an initial CMOS process 702 is performed on one surface of the starting wafer W1 to achieve an intermediate structure 710. The initial CMOS process can include steps to form a CMOS circuit system that will tolerate high temperature CVD steps performed later in the process. For example, the initial CMOS process can reach and include the formation of a polysilicon grid. Next, a first bonded wafer BW1 is bonded to the portion of the starting wafer W1 having the initial CMOS structure 702 to achieve an intermediate structure 720. Next, the portion of the initial wafer W1 other than the CMOS structure 702 is etched away to form an intermediate structure 730. Next, a boron layer 742 is deposited on the CMOS layer 702 using HT PureB CVD to form an intermediate structure 740. Next, a second bonded wafer BW2 is bonded to the boron layer 742 to achieve an intermediate structure 750. Next, the first bonded wafer BW1 is debonded from the CMOS layer 702 to form the intermediate structure 760. The second part of the CMOS process is then performed to create the CMOS structure layer 772 and thus achieve the intermediate structure 770. The third bonded wafer BW3 is then bonded to the CMOS structure layer 772 to achieve the intermediate structure 780. Finally, the bonding layer BW2 is debonded from the boron layer 742 to achieve the final structure 790. It should be understood that the final structure may undergo additional processing steps. For each bonding / debonding step, an appropriate bonding / debonding technique must be selected based on an appropriate thermal treatment sequence before and after the bonding / debonding step.

[0090] Figures 8A-8D Shown in more detail Figure 7 the overall process. Fig. 8A The topmost portion of shows an initial CMOS process 702 applied to one surface of a starting wafer W1 to achieve an intermediate structure 710. The initial CMOS process may include steps to form CMOS circuitry that will tolerate high temperature CVD steps performed later in the process. For example, the initial CMOS process may be up to and including the formation of a polysilicon grid. Fig. 8A The next part downwards in the figure shows that a first bonding wafer BW1 is bonded to a portion of the starting wafer W1 having an initial CMOS structure 702 to realize an intermediate structure 720 . Fig. 8A The next portion downward of shows the portion of the initial wafer W1 except that the CMOS layer 702 has been etched away to form an intermediate structure 730 .

[0091] Steering Figure 8B , Figure 8B The topmost portion of FIG. 7 shows the deposition of a boron layer 742 on the CMOS layer 702 using HTPureB CVD to form an intermediate structure 740 . Figure 8B The next part downward in the figure shows that a second bonding wafer BW2 is bonded to the boron layer 742 to realize an intermediate structure 750 .

[0092] Steering Figure 8C , Figure 8C The topmost portion of shows debonding the first bonded wafer BW1 from the CMOS layer 702 to form an intermediate structure 760 . Figure 8C The next portion downward shows performing a second portion of CMOS processing to create a CMOS structure layer 772 and thereby realize an intermediate structure 770 .

[0093] Fig.8D The topmost portion of illustrative embodiment shows the bonding of the third bonded wafer BW3 to the CMOS structure layer 772 to achieve the intermediate structure 780. Finally, the second bonded wafer BW2 is debonded from the boron layer 742 to achieve the final structure 790.

[0094] Fig. 9 is a flow chart showing the process steps for manufacturing a single-die CMOS detector using temporary wafer bonding-debonding according to one aspect of an embodiment. In step S10, an initial CMOS processing is performed on a starting wafer. This processing is performed in order to form only structures that can tolerate the high heat of subsequent steps, especially high temperature CVD deposition steps. In step S20, a first bonded wafer is bonded to the processed side of the starting wafer. In step S30, the starting wafer is etched to expose a portion of the CMOS processed surface. In step S40, a layer of material such as pure boron is deposited on the CMOS processed surface using, for example, HT PureB CVD. In step S50, a second bonded wafer is bonded to the boron layer. In step S60, the first bonded wafer is debonded from the combination of the second bonded wafer and its layers. In step S70, additional CMOS processing is performed on the CMOS processed layers. In this step, structures that cannot tolerate high temperature steps such as HT PureB CVD can be formed because such steps have been performed. In step S80, a third bonded wafer is bonded to the CMOS processed layers. In step S90 , the second bonded wafer is debonded from the combination of the third body wafer and its layers.

[0095] The embodiments may be further described using the following terms:

[0096] 1. A detector, comprising:

[0097] A semiconductor structure having a pn junction; and

[0098] A top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode comprising a doped layer and a buried portion at least partially below the doped layer, the buried portion being configured to reduce a series resistance of the top electrode.

[0099] 2. A detector according to clause 1, wherein:

[0100] The detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system, and

[0101] The semiconductor structure has an aperture through which a scanning light beam is transmitted to a target.

[0102] 3. The detector of clause 1, wherein the buried portion is configured to reduce the series resistance of the top electrode without changing the active area provided for detection.

[0103] 4. A detector according to clause 1, wherein:

[0104] The semiconductor structure is a silicon-based semiconductor structure,

[0105] The top electrode is an anode electrode, and

[0106] The doping layer is doped with a p-type dopant.

[0107] 5. The detector of clause 4, wherein the buried portion of the top electrode is formed by thermal treatment of the same type of dopant as the doped layer.

[0108] 6. The detector of clause 5, wherein the dopant used to form the buried portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

[0109] 7. The detector of clause 4, wherein the p-type dopant of the doped layer comprises boron.

[0110] 8. A detector according to clause 1, wherein:

[0111] The semiconductor structure is a silicon-based semiconductor structure,

[0112] The top electrode is a cathode electrode, and

[0113] The doping layer is doped with an n-type dopant.

[0114] 9. The detector of clause 8, wherein the buried portion of the top electrode is formed by thermal treatment of the same type of dopant as the doped layer.

[0115] 10. The detector of clause 9, wherein the dopant used to form the buried portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

[0116] 11. The detector of clause 9, wherein the same type of dopant for the buried portion of the top electrode and the doped layer are different n-type dopants.

[0117] 12. The detector of clause 8, wherein the n-type dopant of the doping layer comprises one or more of arsenic, phosphorus, or antimony.

[0118] 13. The detector according to claim 1 further includes a top electrode metal contact, which is arranged above the periphery of the semiconductor structure and overlaps with the doped layer portion of the top electrode, wherein the buried portion of the top electrode reduces the series resistance of the top electrode to facilitate the current generated by the pn junction through the detection of the electrons or electromagnetic radiation to be available at the top electrode metal contact.

[0119] 14. The detector of clause 1, further comprising a capping layer disposed over the doped layer.

[0120] 15. The detector according to clause 14, wherein the covering layer is a conductive layer.

[0121] 16. The detector of clause 1, wherein the pn junction is a pin junction.

[0122] 17. A detector according to clause 1, wherein:

[0123] the detector is a secondary electron (SE) detector and the detection of the electrons comprises detection of backscattered electrons from the target, or

[0124] The detector is a radiation detector and the detection of the electromagnetic radiation comprises detection of backscattered electromagnetic radiation from the target.

[0125] 18. The detector of clause 1, wherein the buried portion of the top electrode comprises a plurality of buried segments in the active area provided by the top electrode.

[0126] 19. The detector of clause 18, wherein the plurality of buried segments do not intersect each other.

[0127] 20. The detector of clause 19, wherein the plurality of buried segments comprises straight segments, curved segments, or both straight segments and curved segments.

[0128] 21. The detector of clause 19, wherein the plurality of buried segments are arranged in a grid configuration.

[0129] 22. The detector of clause 19, wherein the plurality of buried segments are arranged in a radial configuration.

[0130] 23. The detector of clause 1, wherein the detector is configured for off-axis operation in a SEM inspection system.

[0131] 24. A detector comprising:

[0132] a semiconductor structure having an aperture through which a scanning light beam is transmitted to a target, the semiconductor structure having a pn junction;

[0133] a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, and the top electrode comprising a doped layer; and

[0134] An isolation structure is formed in the semiconductor structure near a sidewall of the hole and is configured to electrically isolate the active area from the sidewall of the hole.

[0135] 25. The detector of clause 24, wherein the hole is formed at the center of the semiconductor structure.

[0136] 26. The detector of clause 24, wherein the isolation structure is configured to electrically isolate the active region from the sidewalls of the hole by being configured to limit a depletion region formed by the pn junction from reaching the sidewalls of the hole.

[0137] 27. The detector of clause 24, wherein the distance between the isolation structure and the sidewall of the hole is less than 60 microns.

[0138] 28. The detector of clause 24, wherein the isolation structure is a deep trench structure substantially parallel to but not contacting the sidewalls of the hole.

[0139] 29. The detector of clause 28, wherein the deep trench structure comprises doped sidewalls and provides a defect-free stopping plane to electrically isolate the active region by limiting a depletion region formed by the pn junction to reach the sidewalls of the hole.

[0140] 30. The detector of clause 24, wherein the isolation structure is a doped layer substantially parallel to and adjacent to the sidewalls of the hole.

[0141] 31. The detector of clause 30, wherein the distance between the isolation structure and the sidewalls of the hole is less than 1 micron.

[0142] 32. The detector of clause 30, wherein the doped layer is in contact with the sidewalls of the hole.

[0143] 33. A detector according to clause 24, wherein:

[0144] The semiconductor structure is a silicon-based semiconductor structure,

[0145] The top electrode is an anode electrode, and

[0146] The doping layer is doped with a p-type dopant.

[0147] 34. The detector of clause 33, wherein the p-type dopant of the doped layer comprises boron.

[0148] 35. A detector according to clause 24, wherein:

[0149] The semiconductor structure is a silicon-based semiconductor structure,

[0150] The top electrode is a cathode electrode, and

[0151] The doping layer is doped with an n-type dopant.

[0152] 36. The detector of clause 35, wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony.

[0153] 37. The detector of clause 24, wherein the pn junction is a pin junction.

[0154] 38. A detector according to clause 24, wherein:

[0155] the detector is a secondary electron (SE) detector and the detection of the electrons comprises detection of backscattered electrons from the target, or

[0156] The detector is a radiation detector and the detection of the electromagnetic radiation comprises detection of backscattered electromagnetic radiation from the target.

[0157] 39. The detector of clause 24, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system.

[0158] 40. A detector comprising:

[0159] a semiconductor structure having an aperture through which a scanning light beam is transmitted to a target, the semiconductor structure having a pn junction;

[0160] a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, the top electrode comprising a doped layer and a buried portion at least partially beneath the doped layer, the buried portion being configured to reduce a series resistance of the top electrode without altering the active area provided for the detection of the backscatter; and

[0161] An isolation structure is formed in the semiconductor structure near a sidewall of the hole and is configured to electrically isolate the active area from the sidewall of the hole.

[0162] 41. The detector of clause 40, wherein the hole is formed at the center of the semiconductor structure.

[0163] 42. A detector according to clause 40, wherein:

[0164] The semiconductor structure is a silicon-based semiconductor structure,

[0165] The top electrode is an anode electrode,

[0166] The doping layer is doped with a p-type dopant, and

[0167] The buried portion of the top electrode is formed by thermal treatment of the same type of dopant as the doped layer.

[0168] 43. The detector of clause 42, wherein the dopant used to form the buried portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

[0169] 44. The detector of clause 42, wherein the p-type dopant of the doped layer comprises boron.

[0170] 45. A detector according to clause 40, wherein:

[0171] The semiconductor structure is a silicon-based semiconductor structure,

[0172] The top electrode is a cathode electrode,

[0173] The doping layer is doped with an n-type dopant, and

[0174] The buried portion of the top electrode is formed by thermal treatment of the same type of dopant as the doped layer.

[0175] 46. ​​The detector of clause 45, wherein the dopant used to form the buried portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

[0176] 47. The detector of clause 45, wherein the same type of dopant for the buried portion of the top electrode and the doped layer are different n-type dopants.

[0177] 48. The detector of clause 45, wherein the n-type dopant of the doped layer comprises one or more of arsenic, phosphorus, or antimony.

[0178] 49. The detector of clause 40, wherein the isolation structure is:

[0179] a deep trench structure having doped sidewalls substantially parallel to but not contacting the sidewalls of the hole, or

[0180] A doped layer is substantially parallel to and adjacent to the sidewalls of the hole.

[0181] 50. A detector according to clause 40, wherein:

[0182] the detector is a secondary electron (SE) detector and the detection of the electrons comprises detection of backscattered electrons from the target, or

[0183] The detector is a radiation detector and the detection of the electromagnetic radiation comprises detection of backscattered electromagnetic radiation from the target.

[0184] 51. The detector of clause 40, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system.

[0185] 52. A method of forming a buried portion of a top electrode in a semiconductor detector, the method comprising:

[0186] depositing a dopant layer on a surface of the semiconductor structure having an active area of ​​the top electrode; and

[0187] A thermal treatment is applied to drive dopants from the dopant layer into the semiconductor structure and at least partially below the detection layer of the top electrode to form the buried portion of the top electrode, the buried portion of the top electrode comprising a plurality of buried segments that reduce the series resistance of the top electrode.

[0188] 53. The method of clause 52, wherein forming the plurality of buried segments comprises forming:

[0189] Multiple buried segments that do not cross each other,

[0190] a plurality of buried segments including straight segments, curved segments, or both straight segments and curved segments,

[0191] Multiple buried segments arranged in a grid configuration, or

[0192] A plurality of buried segments are arranged in a radial configuration.

[0193] 54. The method of clause 52, wherein the depositing of the dopant layer comprises depositing the dopant layer by a chemical vapor deposition process.

[0194] 55. The method of clause 52, further comprising depositing a capping layer over the dopant layer, wherein the capping layer is deposited prior to application of the thermal treatment.

[0195] 56. The method of clause 52, wherein the cover layer is a dielectric layer.

[0196] 57. A method according to clause 52, wherein:

[0197] The top electrode is an anode electrode, and

[0198] The dopant in the doping layer includes a p-type dopant.

[0199] 58. The method of clause 57, wherein the p-type dopant comprises boron.

[0200] 59. The method of clause 57, wherein the dopant of the detection layer is the same type as the dopant of the dopant layer.

[0201] 60. A method according to clause 52, wherein:

[0202] The top electrode is a cathode electrode, and

[0203] The dopant in the doping layer includes an n-type dopant.

[0204] 61. The method of clause 60, wherein the n-type dopant comprises one or more of arsenic, phosphorus, or antimony.

[0205] 62. The method of clause 60, wherein the dopant of the detection layer is the same type as the dopant of the dopant layer.

[0206] 63. A method according to clause 52, wherein:

[0207] The detector is a secondary electron (SE) detector configured to detect electrons over the active area, or

[0208] The detector is a radiation detector configured to detect electromagnetic radiation over the active area.

[0209] 64. A detector comprising:

[0210] a first layer of a first conductivity type on a first side of the substrate for forming an anode electrode for receiving secondary electrons of a scanning electron microscope (SEM) inspection system;

[0211] a buried portion of the first conductivity type at the first side of the substrate for reducing a series resistance of the anode electrode; and

[0212] A second layer of a second conductivity type is used to enable formation of a pn diode including the first layer and the second layer.

[0213] 65. The detector of clause 64, wherein the forming of the buried portion comprises implanting dopants into the substrate.

[0214] 66. A detector according to clause 65, wherein the dopant comprises boron.

[0215] 67. A detector according to clause 64, wherein the buried portions form a grid.

[0216] 68. A substrate comprising:

[0217] a semiconductor structure comprising a hole, the semiconductor structure comprising a deep trench isolation surrounding the hole;

[0218] a first layer of a first conductivity type on a first side of the semiconductor structure for receiving secondary electrons from a SEM system; and

[0219] A second layer of a second conductivity type is used to enable formation of a pn diode including the first layer and the second layer in the semiconductor structure, wherein the second layer is adjacent to the deep trench isolation.

[0220] 69. A method of manufacturing a semiconductor detector comprising an element for generating a signal in response to receiving radiation and a circuit system electrically connected to the element, the circuit system comprising at least one structure that cannot withstand a processing temperature exceeding a temperature T, the method comprising the steps of:

[0221] manufacturing a first portion of the circuit system, the first portion being able to withstand the temperature T;

[0222] performing a treatment step at said temperature T; and

[0223] A second portion of the circuit system is manufactured, the second portion comprising a structure that cannot withstand the temperature T.

[0224] 70. The method of clause 69, wherein performing the processing step at the temperature T comprises performing high temperature chemical vapor deposition.

[0225] 71. The method of clause 70, wherein performing high temperature chemical vapor deposition comprises performing high temperature chemical vapor deposition of boron.

[0226] 72. The method of clause 71, wherein performing high temperature chemical vapor deposition of boron comprises high temperature chemical vapor deposition of pure boron.

[0227] 73. The method of any of clauses 69 to 72, wherein fabricating the first portion of the circuitry comprises partial fabrication of CMOS circuitry.

[0228] 74. A method according to any of clauses 69 to 73, wherein fabricating the second portion of the circuitry comprises complete fabrication of the CMOS circuitry.

[0229] 75. The method according to any of clauses 69 to 74, wherein the temperature T is above 700°C.

[0230] 76. A method of manufacturing a semiconductor detector comprising an element for generating a signal in response to receiving radiation and CMOS circuitry electrically connected to the element, the CMOS circuitry comprising at least one structure that cannot withstand a processing temperature T exceeding 700° C., the method comprising the steps of:

[0231] manufacturing a first portion of the CMOS circuit system, the first portion being able to withstand the temperature T;

[0232] performing a HT PureB CVD process step at said temperature T; and

[0233] A second portion of the CMOS circuitry is fabricated, the second portion comprising structures that cannot withstand the temperature T.

[0234] 77. A process for manufacturing a single-die semiconductor detector, the process comprising the steps of:

[0235] Providing a starting wafer;

[0236] Performing a first partial circuit forming step on the processed side of the starting wafer to form a first partial circuit layer, the first partial circuit forming step being limited to forming a circuit system that can withstand a processing temperature T;

[0237] Bonding a first bonding wafer to the first partial circuit layer;

[0238] etching away a portion of the starting wafer to expose the first portion of the circuit layer;

[0239] depositing a boron layer on the first portion of the circuit layer;

[0240] bonding a second bonding wafer to the boron layer;

[0241] debonding the first bonded wafer from the first partial circuit layer;

[0242] performing a second partial circuit forming step on the first partial circuit layer to form a completed circuit layer, wherein the second partial circuit forming step includes forming a circuit structure that cannot withstand the processing temperature T;

[0243] bonding a third bonding layer to the completed circuit layer; and

[0244] The second bonded wafer is debonded from the boron layer.

[0245] 78. The process of clause 77, wherein performing a first partial circuit formation step comprises performing a first partial CMOS circuit formation step.

[0246] 79. A process according to any one of clauses 77 or 78, wherein performing a second partial circuit forming step on a first partial circuit layer to form a completed circuit layer comprises performing a second partial CMOS circuit forming step on the first partial circuit layer to form a completed CMOS circuit layer.

[0247] 80. The process of any of clauses 77 to 79, wherein depositing a boron layer on the first partial circuit layer comprises using HT PureB CVD.

[0248] 81. The process according to any of clauses 77 to 80, wherein the temperature T is above 700°C.

[0249] 82. A single-die semiconductor detector comprising an element for generating a signal in response to receiving radiation and CMOS circuitry electrically connected to the element, the CMOS circuitry comprising at least one structure that cannot withstand a processing temperature T exceeding 700° C., the semiconductor detector being manufactured by a method comprising the steps of:

[0250] manufacturing a first portion of the CMOS circuit system, the first portion being able to withstand the temperature T;

[0251] performing a HT PureB CVD process step at said temperature T; and

[0252] A second portion of the CMOS circuitry is fabricated, the second portion comprising structures that cannot withstand the temperature T.

[0253] The present disclosure (including FIGS. 1-9 and their corresponding descriptions) provides various techniques for improving the sensitivity, efficiency, and bandwidth of semiconductor detectors used in SEM systems. For example, the present disclosure describes the use of a "buried grid" or "buried portion" of a top electrode in combination with pure boron technology (e.g., a pure boron layer or similar layer for a cathode electrode) to achieve low noise and high speed response in electron detection, where there is no filtering / absorbing metal stack (e.g., an aluminum grid 240 is used for the active area (as is the case in extreme ultraviolet EUV applications)). In addition, the present disclosure describes the use of isolation structures to maximize the active area and new localization resolution of incident electrons within a certain segment of a semiconductor detector (e.g., a radial configuration).

[0254] The various figures described in conjunction with the accompanying drawings illustrate examples of possible implementations of the architecture, arrangement, functionality, and operation of various embodiments. With respect to the flow charts, each box may represent a portion of the entire method or process. It should also be noted that in some alternative implementations, the functions annotated in the boxes of the flow chart may not occur in the order annotated and / or may occur simultaneously with the functions of different boxes.

[0255] It should be understood that the described embodiments are not mutually exclusive, and elements, components, materials, or steps described in conjunction with one exemplary embodiment may be combined with or removed from other embodiments in a suitable manner to achieve desired design goals.

[0256] As used herein, unless specifically stated otherwise, the term "or" encompasses all possible combinations unless not feasible. For example, if it is stated that a component may include A or B, then unless otherwise explicitly stated or not feasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then unless otherwise explicitly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0257] In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

[0258] The use of figure numbers or figure reference labels in the claims is intended to facilitate interpretation of the claims. Such use should not be construed as necessarily limiting the scope of these claims to the embodiments or implementations shown in the corresponding figures.

[0259] It will be further understood that those skilled in the art may make various changes in the details, materials and arrangements of the parts described and illustrated for the purpose of explaining the nature of the described aspects or embodiments without departing from the scope expressed in the appended claims.

Claims

1. A detector, comprising: a semiconductor structure having an aperture through which a scanning light beam is transmitted to a target, the semiconductor structure having a pn junction; a top electrode for the pn junction, the top electrode providing an active area for detecting electrons or electromagnetic radiation, and the top electrode comprising a doped layer; and An isolation structure is formed in the semiconductor structure near a sidewall of the hole and is configured to electrically isolate the active area from the sidewall of the hole.

2. The detector of clause 1, wherein the hole is formed at the center of the semiconductor structure. 3 . The detector of claim 1 , wherein the isolation structure is configured to electrically isolate the active region from the sidewalls of the hole by being configured to limit a depletion region formed by the pn junction from reaching the sidewalls of the hole.

4. The detector of claim 1, wherein the distance between the isolation structure and the sidewall of the hole is less than 60 microns.

5. The detector of claim 1, wherein the isolation structure is a deep trench structure substantially parallel to but not contacting the sidewalls of the hole.

6. The detector of claim 5, wherein the deep trench structure comprises doped sidewalls and provides a defect-free stopping plane to electrically isolate the active area by limiting the depletion region formed by the pn junction to reach the sidewalls of the hole.

7. The detector of claim 1, wherein the isolation structure is a doped layer substantially parallel to and adjacent to the sidewalls of the hole.

8. The detector of claim 7, wherein the distance between the isolation structure and the sidewall of the hole is less than 1 micron.

9. The detector of claim 7, wherein the doped layer is in contact with the sidewalls of the hole.

10. The detector according to claim 1, wherein: The semiconductor structure is a silicon-based semiconductor structure, The top electrode is an anode electrode, and The doping layer is doped with a p-type dopant.

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