Oscillator and output frequency expansion method thereof

Abstract

The invention discloses an oscillator and an output frequency expansion method thereof. The oscillator comprises a first current module, a second current module, a resistor module, a capacitor module, a switch module and a comparison control module. According to the oscillator and the output frequency expansion method thereof, the clock signal output by the oscillator can be modulated into the clock signal of which the frequency is periodically changed by selecting one or more modes of adjusting the resistance value of the resistor module, adjusting the capacitance value of the capacitor module, adjusting the current on the resistor module and adjusting the current on the capacitor module; the energy is dispersed in a certain frequency range, and the purpose of clock spectrum spreading is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an oscillator and a method for extending its output frequency. Background Art

[0002] In complex SOC systems, due to the periodicity of high-frequency and high-speed transition-time digital signals, their energy is concentrated in a narrow band near harmonic frequencies. This energy can generate electromagnetic interference (EMI) through radiation. Among the many methods to reduce EMI, spread-spectrum clocking (SSC) is an effective and popular approach for high-speed systems. This technique modulates the system clock to reduce the radiated power level within a given bandwidth. Figure 1 A comparison of the power spectra of an unmodulated clock and a spread spectrum clock shows that the spread spectrum clock (SSC) has a certain attenuation effect on electromagnetic interference energy.

[0003] In typical systems, clock generation is accomplished through a phase-locked loop (PLL). A common technique for generating spread spectrum (SSC) clocks is to insert modulation into the PLL. For example, the clock frequency can be modulated by changing the division ratio using fractional division techniques, as shown in the example below. Figure 2 As shown, it includes a phase-locked loop (PLL), a Δ-Σ modulator, and a modulation waveform module. Here, a fractional frequency divider is used in the PLL.

[0004] However, in some systems that do not include a phase-locked loop (PLL), such as when the system clock is directly generated by a high-speed on-chip RC relaxation oscillator, the application of such designs in EMI-sensitive environments is limited because it is impossible to spread the frequency by adding a modulation clock to the PLL.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an oscillator and its output frequency extension method, which can perform frequency modulation to effectively reduce the impact of EMI.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides an oscillator, including: a first current module, a second current module, a resistor module, a capacitor module, a switch module, and a comparison control module.

[0008] The first current module has a first terminal connected to a first voltage and is used to generate a reference current. The second current module has a first terminal connected to the first voltage and is used to generate a charging current. The first terminal of the resistor module is connected to the second terminal of the first current module, and the second terminal of the resistor module is connected to a second voltage. The resistor module is used to generate a reference voltage based on the reference current. The first terminal of the capacitor module is connected to the second terminal of the second current module, and the second terminal of the capacitor module is connected to the second voltage. The capacitor module is used to generate a comparison voltage based on the charging current. The first terminal of the switch module is connected to the first terminal of the capacitor module, and the second terminal of the switch module is connected to the second voltage. The switch module is used to control the connection between the first terminal of the capacitor module and the second voltage. The comparison control module is used to generate a clock signal based on the reference voltage and the comparison voltage, and to control the switch module to turn on or off based on the clock signal. The oscillator resistor module adjusts the frequency of the clock signal by adjusting the resistance value of its own resistor module, adjusting the current on the resistor module, adjusting the capacitance value of the capacitor module, adjusting the current on the resistor module, and / or adjusting the current on the capacitor module.

[0009] In one or more embodiments of the present invention, the capacitor module includes a plurality of capacitors and a switching transistor, wherein the plurality of capacitors are connected in parallel and at least one switching transistor is connected in series with at least one capacitor, the control terminal of the switching transistor is used to receive a first calibration code or a control signal, the control signal having a duty cycle that varies with time, the capacitor includes a reference capacitor and a plurality of regulating capacitors, at least one regulating capacitor and a switching transistor are connected in series, and one end of the at least one regulating capacitor is connected to the first terminal of the reference capacitor and the second terminal of the second current module, and the other end is connected to the second terminal of the reference capacitor and the second voltage.

[0010] In one or more embodiments of the present invention, the regulating capacitor is provided with two capacitors, namely a first regulating capacitor and a second regulating capacitor, and the switching transistor is provided with two transistors, namely a first switching transistor and a second switching transistor. The first regulating capacitor is connected in series with the first switching transistor, and the second regulating capacitor is connected in series with the second switching transistor. The control terminal of the first switching transistor is used to receive a first control signal, and the control terminal of the second switching transistor is used to receive a second control signal. The duty cycle of the first control signal increases to a target value in a first time period, remains at the target value in a second time period, and decreases from the target value in a third time period. The duty cycle of the second control signal increases to the target value in the second time period and then decreases from the target value.

[0011] In one or more embodiments of the present invention, the second current module includes a plurality of first transistors, a first terminal of the first transistors is connected to a first voltage, a second terminal of the first transistors is connected to a first terminal of the capacitor module, and a control terminal of the first transistors is used to receive a second calibration code.

[0012] In one or more embodiments of the present invention, the resistor module includes a plurality of resistors and a control transistor, wherein the plurality of resistors are connected in series and / or in parallel and at least one control transistor is connected in series or in parallel with at least one resistor, and the control terminal of the control transistor is used to receive a third calibration code.

[0013] In one or more embodiments of the present invention, the oscillator further includes a third current module, a first terminal of which is connected to a first voltage, and the third current module is connected to a first terminal of a resistor module and / or a first terminal of a capacitor module. The third current module is used to generate an adjustment current to adjust the current on the resistor module or the current on the capacitor module.

[0014] In one or more embodiments of the present invention, the third current module includes a plurality of second transistors, the first terminal of the second transistors is connected to a first voltage, the second terminal of the second transistors is connected to the first terminal of the resistor module and / or the first terminal of the capacitor module, and the control terminal of the second transistors is used to receive a third calibration code.

[0015] The present invention also discloses an output frequency extension method for an oscillator, based on the aforementioned oscillator; the output frequency extension method includes:

[0016] A reference current is generated through the first current module;

[0017] The charging current is generated through the second current module;

[0018] A reference voltage is generated based on the reference current using a resistor module;

[0019] A comparison voltage is generated based on the charging current using a capacitor module;

[0020] The switching module controls the connection and disconnection between the first terminal of the capacitor module and the second voltage.

[0021] The comparison control module generates a clock signal based on the reference voltage and the comparison voltage, and controls the switching module to turn on or off based on the clock signal.

[0022] The frequency of the clock signal can be adjusted by selecting one or more of the following methods: adjusting the resistance value of the resistor module, adjusting the capacitance value of the capacitor module, adjusting the current on the resistor module, and adjusting the current on the capacitor module.

[0023] In one or more embodiments of the present invention, the capacitance value of the adjusting capacitor module includes:

[0024] The capacitor connection is controlled by turning the switching transistor in the capacitor module on or off using the first calibration code or control signal. If controlled by a control signal, the control signal with a duty cycle that changes over time is used.

[0025] In one or more embodiments of the present invention, using a control signal whose duty cycle varies with time to control the capacitor connection includes:

[0026] The connection time of at least one first regulating capacitor in the capacitor module is controlled by a first control signal whose duty cycle increases to the target value in the first time period, remains at the target value in the second time period, and decreases from the target value in the third time period.

[0027] The connection time of at least one second regulating capacitor in the capacitor module is controlled by a second control signal whose duty cycle increases to the target value during the second time period and then decreases from the target value.

[0028] Compared with the prior art, the oscillator and its output frequency spreading method of the present invention have an oscillation frequency that is related to the resistor, capacitor, and the ratio of the capacitor's charging current to the reference current. By selecting one or more of the following methods—adjusting the resistance value of the resistor module, adjusting the capacitance value of the capacitor module, adjusting the current on the resistor module, and adjusting the current on the capacitor module—the clock signal output by the oscillator can be modulated into a clock signal with periodically changing frequency, so that its energy is dispersed over a certain frequency range, thereby achieving the purpose of clock frequency spreading.

[0029] By selecting an appropriate range of variation for the above parameters, a suitable spread frequency range can be set; different spread types—center spread, upward spread, and downward spread—can be set by adjusting the resistance, capacitance, and current.

[0030] The oscillator and its output frequency spreading method of the present invention are not limited by the frequency spreading scheme of traditional phase-locked loop clock systems. The clock spreading is achieved by changing the parameters affecting the oscillation frequency in a low-frequency, continuous, and periodic manner, making such circuits more flexible in EMI-sensitive applications. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A comparison of the power spectra of an unmodulated clock signal and a spread-spectrum clock signal.

[0033] Figure 2 This is a circuit diagram of a phase-locked loop in the prior art.

[0034] Figure 3 This is a circuit diagram of the oscillator in Embodiment 1 of the present invention.

[0035] Figure 4 This is a circuit diagram of the capacitor module of the oscillator in Embodiment 1 of the present invention.

[0036] Figure 5 This is a schematic diagram showing the duty cycle change of the control signal of the oscillator in Embodiment 1 of the present invention.

[0037] Figure 6 This is a circuit diagram of the second current module of the oscillator in Embodiment 3 of the present invention.

[0038] Figure 7 This is a circuit diagram of the resistor module of the oscillator in Embodiment 4 of the present invention.

[0039] Figure 8 This is a circuit diagram of the oscillator in Embodiment 5 of the present invention.

[0040] Figure 9 This is a schematic diagram of the oscillator output frequency expansion method in this invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0042] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0043] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0044] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0045] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0046] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0047] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0048] Example 1

[0049] like Figure 3 As shown, an oscillator in one embodiment of the present invention includes: a first current module 10, a resistor module 20, a second current module 30, a capacitor module 40, a switch module 50, and a comparison control module 60.

[0050] The first terminal of the first current module 10 is connected to a first voltage, and the first current module 10 is used to generate a reference current Iref; the first terminal of the second current module 30 is connected to the first voltage, and the second current module 30 is used to generate a charging current Icharge; the first terminal of the resistor module 20 is connected to the second terminal of the first current module 10, and the second terminal of the resistor module 20 is connected to a second voltage, and the resistor module 20 is used to generate a reference voltage Vref based on the reference current Iref; the first terminal of the capacitor module 40 is connected to the second terminal of the second current module 30, and the second terminal of the capacitor module 40 is connected to the second voltage, and the capacitor module 40 is used to generate a comparison voltage Vc based on the charging current Icharge. In one embodiment, the first voltage is the power supply voltage, and the second voltage is the ground voltage.

[0051] The first terminal of the switch module 50 is connected to the first terminal of the capacitor module 40, and the second terminal of the switch module 50 is connected to the second voltage. The switch module 50 is used to control the connection and disconnection between the first terminal of the capacitor module 40 and the second voltage. The comparison control module 60 is used to generate a clock signal Clk based on the reference voltage Vref and the comparison voltage Vc, and to control the switch module 50 to turn on or off based on the clock signal Clk.

[0052] In one embodiment, during one charge-discharge cycle T of the capacitor module 40, the average voltage across the capacitor module 40 is... Must meet The comparison control module 60 generates a valid output. The two charge / discharge cycles T of capacitor module 40 correspond to one cycle of clock signal Clk, thus the frequency of clock signal Clk can be obtained. Where C is the capacitance of capacitor module 40, R is the resistance of resistor module 20, Iref is the reference current supplied to resistor module 20, and Icharge is the charging current for capacitor module 40. Therefore, it can be deduced that the oscillation frequency of the oscillator is related to resistor module 20, capacitor module 40, and the ratio of the charging current of capacitor module 40 to the reference current on resistor module 20.

[0053] In one embodiment, the capacitor module 40 adjusts the frequency of the clock signal Clk based on adjusting its own capacitance.

[0054] The capacitor module 40 includes multiple capacitors and a switching transistor. The capacitors are connected in parallel, and at least one switching transistor is connected in series with at least one capacitor. The control terminal of the switching transistor receives a control signal Vctrl, which has a duty cycle that varies with time. When the switching transistor is turned on by the control signal Vctrl, the capacitor on that branch can be connected to the circuit. In other embodiments, multiple capacitors can be connected in series, or a combination of series and parallel connections, to achieve the desired total capacitance value. Alternatively, the switching transistor and capacitors can be connected in parallel to short-circuit the capacitors when the switching transistor is turned on by the control signal Vctrl.

[0055] In one embodiment, the capacitor includes a reference capacitor Cint and a plurality of regulating capacitors Cctrl. At least one regulating capacitor Cctrl is connected in series with a switching transistor, and one end of the at least one regulating capacitor Cctrl is connected to the first end of the reference capacitor Cint and the second end of the second current module 30, and the other end is connected to the second end of the reference capacitor Cint and the second voltage.

[0056] In other embodiments, the number of reference capacitor Cint and regulating capacitor Cctrl can be set as needed, or the reference capacitor Cint can be omitted, and each regulating capacitor Cctrl can be connected in series with a corresponding switching transistor.

[0057] Figure 4 An exemplary structure of a capacitor module 40 is provided, wherein there is one reference capacitor Cint, two adjustment capacitors Cctrl are provided, namely a first adjustment capacitor Cctrl1 and a second adjustment capacitor Cctrl2, and two switching transistors M are provided, namely a first switching transistor M1 and a second switching transistor M2. The first adjustment capacitor Cctrl1 is connected in series with the first switching transistor M1, that is, the first terminal of the first adjustment capacitor Cctrl1 is connected to the second terminal of the first switching transistor M1, and the first terminal of the first switching transistor M1 is connected to a second voltage. The second terminal of the first adjustment capacitor Cctrl1 is connected to the first terminal of the reference capacitor Cint and the second terminal of the second current module 30, and the second terminal of the reference capacitor Cint is connected to the second voltage. The second adjustment capacitor Cctrl2 is connected in series with the second switching transistor M2, that is, the first terminal of the second adjustment capacitor Cctrl2 is connected to the second terminal of the second switching transistor M2, the first terminal of the second switching transistor M2 is connected to the second voltage, and the second terminal of the second adjustment capacitor Cctrl2 is connected to the first terminal of the reference capacitor Cint and the second terminal of the second current module 30. The control terminal of the first switch M1 is used to receive the first control signal Vctrl1, and the control terminal of the second switch M2 is used to receive the second control signal Vctrl2.

[0058] If the capacitance values ​​of the first regulating capacitor Cctrl1 and the second regulating capacitor Cctrl2 are both equal, and the first control signal Vctrl1 is a valid signal (high level) and the second control signal Vctrl2 is an invalid signal (low level), or the first control signal Vctrl1 is an invalid signal (low level) and the second control signal Vctrl2 is a valid signal (high level), then either the first switch M1 or the second switch M2 is turned on, and either the first regulating capacitor Cctrl1 or the second regulating capacitor Cctrl2 is connected to the circuit. That is, only one regulating capacitor is connected to the circuit. At this time, the frequency of the clock signal Clk is the center frequency f. default When both the first control signal Vctrl1 and the second control signal Vctrl2 are valid (high level), both the first switch M1 and the second switch M2 are turned on, and both the first regulating capacitor Cctrl1 and the second regulating capacitor Cctrl2 are connected to the circuit. At this time, the frequency of the clock signal Clk is the lowest frequency f. min When both the first control signal Vctrl1 and the second control signal Vctrl2 are invalid signals (low level), both the first switch M1 and the second switch M2 are turned off, and neither the first regulating capacitor Cctrl1 nor the second regulating capacitor Cctrl2 is connected to the circuit. At this time, the frequency of the clock signal Clk is the highest frequency f. max .

[0059] In one embodiment, both the first switch M1 and the second switch M2 are N-channel MOSFETs. The first terminal of the first switch M1 and the first terminal of the second switch M2 are the sources, and the second terminals of the first switch M1 and the second switch M2 are the drains. The control terminals of the first switch M1 and the second switch M2 are the gates. In other embodiments, the first switch M1 and the second switch M2 can be P-channel MOSFETs.

[0060] The first control signal Vctrl1 increases its duty cycle to the target value in the first time period, maintains its duty cycle at the target value in the second time period, and decreases its duty cycle from the target value in the third time period. The second control signal Vctrl2 increases its duty cycle to the target value in the second time period and then decreases its duty cycle from the target value.

[0061] like Figure 5 As shown, the first time period ①, the second time period ②, the third time period ③ and the fourth time period ④ can be considered to constitute a variation period T. In one embodiment, a variation period T is approximately 31.25 μs (corresponding to a modulation frequency fm ≈ 32 kHz).

[0062] During the first time period ①, the duty cycle of the first control signal Vctrl1 increases linearly from 0% to 100% (target value). During the second time period ② and the third time period ③, the duty cycle of the first control signal Vctrl1 remains at 100%. During the fourth time period ④, the duty cycle of the first control signal Vctrl1 decreases linearly from 100% (target value) to 0%.

[0063] During the first time period ① and the fourth time period ④, the duty cycle of the second control signal Vctrl2 is maintained at 0%. During the second time period ②, the duty cycle of the second control signal Vctrl2 increases linearly from 0% to 100% (target value). During the third time period ③, the duty cycle of the second control signal Vctrl2 decreases linearly from 100% (target value) to 0%.

[0064] The first control signal Vctrl1 and the second control signal Vctrl2 are both square wave signals with continuously changing duty cycles. During the first time period ①, the duty cycle of the second control signal Vctrl2 is maintained at 0%, meaning the second regulating capacitor Cctrl2 is not connected. The duty cycle of the first control signal Vctrl1 increases linearly from 0% to 100% (target value), at which point the first regulating capacitor Cctrl1 is connected. Furthermore, as time increases, the time the second regulating capacitor Cctrl is connected also gradually increases, corresponding to a gradual decrease in the frequency of the clock signal Clk. When the duty cycle of the first control signal Vctrl1 is 0%, only the reference capacitor Cint is charging and discharging, and at this time, the frequency of the clock signal Clk is the highest frequency f. max As the duty cycle of the first control signal Vctrl1 increases, the first regulating capacitor Cctrl1 is connected, and the frequency of the clock signal Clk gradually decreases to the center frequency f. default .

[0065] During the second time period ② and the third time period ③, the duty cycle of the first control signal Vctrl1 is maintained at 100%, meaning the first regulating capacitor Cctrl1 is always connected. Simultaneously, during the second time period ②, the duty cycle of the second control signal Vctrl2 linearly increases from 0% to 100% (the target value), meaning the second regulating capacitor Cctrl2 is connected, and the time the second regulating capacitor Cctrl2 is connected also increases with time. Correspondingly, the frequency of the clock signal Clk decreases from the center frequency f. default Gradually decrease to the lowest frequency f min During the third time period ③, the duty cycle of the second control signal Vctrl2 decreases linearly from 100% (target value) to 0%, the time for connecting the second regulating capacitor Cctrl2 gradually decreases to 0%, and the frequency of the corresponding clock signal Clk decreases from the lowest frequency f. min Gradually increase to the center frequency f default .

[0066] During the fourth time period ④, the duty cycle of the second control signal Vctrl2 remains at 0%, meaning the second regulating capacitor Cctrl2 is not connected. The duty cycle of the first control signal Vctrl1 decreases linearly from 100% (target value) to 0%, meaning the time the first regulating capacitor Cctrl1 is connected gradually decreases to 0. The corresponding clock signal Clk frequency decreases from the center frequency f. default Gradually increase to the highest frequency f max .

[0067] Therefore, it can be seen that within one cycle, by periodically changing the duty cycle of the first control signal Vctrl1 and the second control signal Vctrl2, the capacitance value actually connected to the circuit can be periodically controlled, and the oscillation frequency of the oscillator's clock signal Clk reaches its highest frequency f. max →Center frequency f default →Lowest frequency f min →Center frequency f default →Highest frequency f max The cyclical change transforms the fixed frequency of the primary side into a frequency based on the center frequency f. default By continuously up-and-down spreading the frequency, a center spreading effect can be achieved. In practical applications, appropriate values ​​for the reference capacitor Cint and the adjusting capacitor Cctrl can be selected to ensure that the frequency change caused by each capacitor is within a suitable range, allowing the frequency modulation range to be 1% to 3% of the center frequency.

[0068] In other embodiments, the duty cycle changes of the first control signal Vctrl1 and the second control signal Vctrl2 can also be in forms other than linear.

[0069] like Figure 3 As shown, the comparison control module 60 includes a comparator COM, a latch, a first inverter INV1, and a second inverter INV2. The first input terminal of the comparator COM is connected to the first terminal of the resistor module 20, the second input terminal of the comparator COM is connected to the first terminal of the capacitor module 40, and the output terminal of the comparator COM is connected to the input terminal of the latch. The output terminal of the latch is used to output a clock signal Clk. The output terminal of the latch is connected to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the switch module 50. In one embodiment, the clock signal Clk is processed by the first inverter INV1 and the second inverter INV2 before controlling the switching module 50 to turn on or off.

[0070] In other embodiments, the first inverter INV1 and the second inverter INV2 may not be provided, and the latch may not be provided.

[0071] Example 2

[0072] Based on Embodiment 1, in this embodiment, the control signal received by the control terminal of the switching transistor can be changed to receive the first calibration code. The duty cycle of the first calibration code will not change. For example, when there are two switching transistors connected in series with two regulating capacitors, namely the first switching transistor M1 and the second switching transistor M2, the first switching transistor M1 and the second switching transistor M2 correspond to a 2-bit first calibration code. The 2-bit first calibration code can be set as follows: 00 (both the first switching transistor M1 and the second switching transistor M2 are off), 01 (the first switching transistor M1 is off and the second switching transistor M2 is on), 10 (the first switching transistor M1 is on and the second switching transistor M2 is off), 11 (both the first switching transistor M1 and the second switching transistor M2 are on). The more regulating capacitors and switching transistors there are, the more bits the first calibration code has, and the smaller the step size of the adjustment frequency is. By using a multi-bit first calibration code to control the number of connected regulating capacitors, the total capacitance value of the capacitor module 40 is changed, thereby changing the frequency of the clock signal Clk and achieving a spread spectrum effect.

[0073] Example 3

[0074] like Figure 3 As shown, the frequency of the clock signal Clk can be adjusted based on the current on the adjusting capacitor module 40.

[0075] In one embodiment, the charging current Icharge generated by the second current module 30 can be adjusted to regulate the current on the capacitor module 40, thereby achieving frequency expansion. In other embodiments, a third current module can be added, which is connected to the first terminal of the capacitor module 40. The third current module generates an adjustment current to regulate the current on the capacitor module 40. In this case, the charging current of the capacitor module 40 is equal to the sum of the current generated by the second current module 30 and the adjustment current generated by the third current module.

[0076] Specifically, the second current module 30 includes multiple first transistors Q. The first terminal of each first transistor Q is connected to a first voltage, and the second terminal of the first transistor is connected to the first terminal of the capacitor module 40. The control terminal of the first transistor Q is used to receive a second calibration code Trim code2. That is, the first transistors Q are connected in parallel, and the number of connected first transistors Q is controlled by the second calibration code Trim code2, thereby adjusting the magnitude of the charging current Icharge. Figure 6A specific structure of the second current module 30 is shown. The second current module 30 includes three first transistors Q. The three first transistors Q correspond to a 3-bit second calibration code Trim code2. The 3-bit second calibration code Trim code2 can be 001, 010, 011, 100, 101, 110, or 111 to control the turning on and off of the three first transistors Q.

[0077] Since the frequency of the clock signal Clk is proportional to the charging current Icharge, the oscillation frequency can be continuously changed upwards and downwards by adding or subtracting the second calibration code Trim code2. This allows for up-and-down frequency spread-out based on the center frequency. For frequency accuracy considerations, the unit current within the second current module 30 is typically set to a small value (i.e., the current generated by each first transistor Q is small). In one embodiment, selecting a suitable adjustment range can also adjust the frequency modulation range to 1% to 3% of the center frequency.

[0078] In other embodiments, the number of first transistors Q can be increased or decreased as needed. A greater number of first transistors Q results in a larger number of bits in the second calibration code Trim code2, and a smaller step size for adjusting the frequency. The first transistor Q is a P-channel MOSFET, with its first terminal being the source, its second terminal being the drain, and its control terminal being the gate. In other embodiments, the first transistor Q can be an N-channel MOSFET. In other embodiments, the second current module 30 can also have other structures to adjust the magnitude of the charging current Icharge.

[0079] Example 4

[0080] like Figure 3 As shown, resistor module 20 can adjust the frequency of clock signal Clk based on adjusting its own resistance value.

[0081] The resistor module 20 includes multiple resistors and a control transistor D. The multiple resistors are connected in series, and at least one control transistor D is connected in parallel with at least one resistor. The control terminal of the control transistor D is used to receive a third calibration code (Trim code 3). When the control transistor D is turned on under the control of the third calibration code (Trim code 3), it can short-circuit the resistors connected in parallel. In other embodiments, multiple resistors can be connected in parallel, or a combination of series and parallel connections can be used to achieve the desired total resistance value. Alternatively, multiple resistors can be connected in parallel, and the control transistor D can be connected in series with the corresponding resistors so that the resistors are connected when the control transistor D is turned on after receiving the third calibration code (Trim code 3).

[0082] like Figure 7As shown, the resistor includes a reference resistor R0 and multiple adjustable resistors R1. At least one adjustable resistor R1 is connected in parallel with a control transistor D. The reference resistor R0 and the multiple adjustable resistors R1 are connected in series, with one end connected to the second terminal of the first current module 10 and the other end connected to the second voltage.

[0083] In one embodiment, two adjustable resistors R1 are set, corresponding to a 2-bit third calibration code Trim code3. The 2-bit third calibration code Trim code3 controls the opening and closing of two control transistors D, thereby controlling the total resistance value of the resistor module 20.

[0084] Frequency expansion is achieved by adjusting the third calibration code (Trim code 3). The frequency of the clock signal Clk is inversely proportional to the resistance value of the resistor module 20. Similarly, the oscillation frequency can be continuously changed upwards and downwards by adding or subtracting the third calibration code (Trim code 3). In one embodiment, selecting an appropriate resistor value can adjust the frequency modulation range to 1% to 3% of the center frequency.

[0085] In other embodiments, the number of reference resistors R0 and adjustment resistors R1 can be set as needed. The more control transistors D there are, the more bits the third calibration code Trim code3 has. Alternatively, reference resistors R0 can be omitted, and each adjustment resistor R1 can be connected in series with a corresponding control transistor D.

[0086] Example 5

[0087] In some designs with high frequency accuracy requirements, it is necessary to incorporate temperature coefficient (TC) calibration. This can be achieved by superimposing a positive temperature coefficient current onto the reference current branch. For example... Figure 8 As shown, the frequency of the clock signal Clk can be adjusted by adding a third current module 70 to regulate the current on the resistor module 20.

[0088] The first terminal of the third current module 70 is connected to the first voltage, and the second terminal of the third current module 70 is connected to the first terminal of the resistor module 20. The third current module 70 is used to generate an adjustment current Itc_trim to adjust the current on the resistor module 20. At this time, the current on the resistor module 20 is equal to the sum of the reference current Iref generated by the first current module 10 and the adjustment current Itc_trim generated by the third current module 70. The adjustment current Itc_trim is a positive temperature coefficient current. Since the oscillation frequency is related to the ratio of the charging current and the reference current, changing the magnitude of the adjustment current Itc_trim can also achieve the purpose of modulating the oscillation frequency.

[0089] The third current module 70 includes multiple second transistors. The first terminal of each second transistor is connected to a first voltage, and the second terminal of each second transistor is connected to the first terminal of the resistor module 20. The control terminal of the second transistor is used to receive a third calibration code. The structure of the third current module 70 can be similar to... Figure 6 The second current module 30 has the same structure. In other embodiments, the third current module 70 may also be other circuit structures capable of generating a regulating current Itc_trim.

[0090] like Figure 9 As shown, based on various embodiments, the present invention also discloses an output frequency extension method for an oscillator. Based on the aforementioned oscillator, the output frequency extension method includes:

[0091] A reference current Iref is generated by the first current module 10.

[0092] The charging current Icharge is generated by the second current module 30.

[0093] The reference voltage Vref is generated by the resistor module 20 based on the reference current Iref.

[0094] The capacitor module 40 generates a comparison voltage Vc based on the charging current Icharge.

[0095] The switching module 50 controls the connection and disconnection between the first terminal of the capacitor module 40 and the second voltage.

[0096] The comparison control module 60 generates a clock signal Clk based on the reference voltage Vref and the comparison voltage Vc, and controls the switching module 50 to turn on or off based on the clock signal Clk.

[0097] The frequency of the clock signal Clk can be adjusted by selecting one or more of the following methods: adjusting the resistance value of the resistor module 20, adjusting the capacitance value of the capacitor module 40, adjusting the current on the resistor module 20, and adjusting the current on the capacitor module 40.

[0098] The adjustment of the capacitance value of the capacitor module 40 includes: controlling the switching transistor in the capacitor module 40 to turn on or off by controlling the connection of the capacitor by controlling the switching transistor in the capacitor module 40 through a first calibration code or a control signal. If the control is controlled by a control signal, the control signal whose duty cycle changes with time is used.

[0099] The method of using a control signal whose duty cycle varies with time to control the capacitor connection includes:

[0100] The connection time of at least one first regulating capacitor Cctrl1 in capacitor module 40 is controlled by a first control signal that increases the duty cycle to the target value in the first time period, maintains the target value in the second time period, and decreases from the target value in the third time period.

[0101] The connection time of at least one second regulating capacitor Cctrl2 in capacitor module 40 is controlled by a second control signal whose duty cycle increases to the target value during the second time period and then decreases from the target value.

[0102] The specific implementation method for adjusting the capacitance value of capacitor module 40 can be referred to the above embodiment 1.

[0103] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0104] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An oscillator, characterized in that: include: A first current module, wherein a first end of the first current module is connected to a first voltage, and the first current module is used to generate a reference current; a second current module, wherein a first end of the second current module is connected to a first voltage, and the second current module is used to generate a charging current; a resistance module, wherein a first end of the resistance module is connected to a second end of the first current module, a second end of the resistance module is connected to a second voltage, and the resistance module is used to generate a reference voltage based on a reference current; A capacitor module, wherein a first end of the capacitor module is connected to a second end of the second current module, a second end of the capacitor module is connected to a second voltage, and the capacitor module is used to generate a comparison voltage based on a charging current; A switch module, wherein a first end of the switch module is connected to a first end of the capacitor module, a second end of the switch module is connected to a second voltage, and the switch module is used to control the connection between the first end of the capacitor module and the second voltage; as well as A comparison control module, used to generate a clock signal based on a reference voltage and a comparison voltage, and control the on or off of the switch module based on the clock signal; The oscillator adjusts the frequency of the clock signal based on one or more of adjusting the resistance of the resistor module, adjusting the current on the resistor module, adjusting the capacitance of the capacitor module, and adjusting the current on the capacitor module.

2. The oscillator according to claim 1, characterized in that The capacitor module includes multiple capacitors and switching tubes, the multiple capacitors are connected in parallel with each other and at least one switching tube is connected in series with at least one capacitor, the control end of the switching tube is used to receive a first calibration code or a control signal, the control signal has a duty cycle that changes with time, the capacitor includes a reference capacitor and multiple adjustment capacitors, at least one adjustment capacitor is connected in series with a switching tube, and one end of the at least one adjustment capacitor is connected to the first end of the reference capacitor and the second end of the second current module, and the other end is connected to the second end of the reference capacitor and the second voltage.

3. The oscillator according to claim 2, characterized in that The regulating capacitor is provided with two, namely a first regulating capacitor and a second regulating capacitor; the switching tube is provided with two, namely a first switching tube and a second switching tube; the first regulating capacitor is connected in series with the first switching tube, and the second regulating capacitor is connected in series with the second switching tube; the control end of the first switching tube is used to receive a first control signal, and the control end of the second switching tube is used to receive a second control signal; the duty cycle of the first control signal in the first time period increases to a target value, the duty cycle in the second time period remains at the target value, and the duty cycle in the third time period decreases from the target value; the duty cycle of the second control signal in the second time period increases to a target value and then decreases from the target value.

4. The oscillator according to claim 1, characterized in that The second current module includes a plurality of first transistors, wherein a first end of the first transistor is connected to a first voltage, a second end of the first transistor is connected to a first end of the capacitor module, and a control end of the first transistor is used to receive a second calibration code.

5. The oscillator according to claim 1, characterized in that The resistor module includes multiple resistors and control tubes. The multiple resistors are connected in series and / or in parallel with each other, and at least one control tube is connected in series or in parallel with at least one resistor. The control end of the control tube is used to receive a third calibration code.

6. The oscillator according to claim 1, characterized in that The oscillator also includes a third current module, a first end of the third current module is connected to the first voltage, the third current module is connected to the first end of the resistance module and / or the first end of the capacitance module, and the third current module is used to generate an adjustment current to adjust the current on the resistance module or the current on the capacitance module.

7. The oscillator according to claim 6, characterized in that The third current module includes multiple second transistors, the first ends of the second transistors are connected to the first voltage, the second ends of the second transistors are connected to the first end of the resistance module and / or the first end of the capacitance module, and the control ends of the second transistors are used to receive the third calibration code.

8. A method for extending the output frequency of an oscillator, characterized in that: Based on the oscillator according to any one of claims 1 to 7; The output frequency expansion method comprises: generating a reference current by a first current module; generating a charging current through a second current module; generating a reference voltage based on a reference current through a resistor module; generating a comparison voltage based on the charging current by a capacitor module; Controlling the connection and disconnection between the first end of the capacitor module and the second voltage through the switch module; Generate a clock signal based on the reference voltage and the comparison voltage through the comparison control module, and control the switch module to turn on or off based on the clock signal; The frequency of the clock signal is adjusted by selecting one or more of the following methods: adjusting the resistance value of the resistor module, adjusting the capacitance value of the capacitor module, adjusting the current on the resistor module, and adjusting the current on the capacitor module.

9. The output frequency expansion method according to claim 8, characterized in that: The capacitance of the adjusting capacitor module includes: The first calibration code or control signal is used to control the on or off of the switch tube in the capacitor module to control the access of the capacitor. If controlled by a control signal, a control signal whose duty cycle changes with time is used.

10. The output frequency expansion method according to claim 9, characterized in that: Using a control signal whose duty cycle varies with time to control the capacitor connection includes: A first control signal whose duty cycle increases to a target value in a first time period, remains at the target value in a second time period, and decreases from the target value in a third time period is used to control the access time of at least one first regulating capacitor in the capacitor module; A second control signal whose duty cycle increases to a target value within a second time period and then decreases from the target value is used to control the access time of at least one second regulating capacitor in the capacitor module.

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