Analog-to-digital converter and control method thereof

Abstract

The invention provides an analog-to-digital converter and a control method thereof, the analog-to-digital converter has a successive approximation structure, and the control method comprises the following steps: after a sampling stage, controlling second ends of capacitors corresponding to a first capacitor array and a second capacitor array to be switched from a first reference voltage to a second reference voltage, the amplitude of the common-mode input voltage is adjusted; and switching the second ends of the capacitors of the first capacitor array and the second capacitor array from the first phase to the final phase according to a preset switching rule, so that the common-mode input voltage is the preset voltage at the final phase. According to the control method, the common-mode input range can be dynamically adjusted, so that the balance between the speed and the noise is optimized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an analog-to-digital converter and a control method thereof. Background Art

[0002] The charge redistribution type successive approximation register (SAR) analog-to-digital converter (ADC) is a common analog-to-digital converter used to convert analog signals into digital signals. In the SAR ADC, the analog input signal is converted into digital form by step-by-step approximation. The working principle is as follows: First, the analog input signal is loaded into a capacitor; then, the comparator inside the ADC compares this input signal with a reference voltage; based on the comparison result, the ADC will decide whether the bit is 0 or 1; the ADC will perform this comparison and decision-making process bit by bit until all bits are determined; finally, the digital output signal is a combination of these bits.

[0003] However, during the switching process of the traditional monotonic switching SAR ADC, the common-mode input range will continue to decrease. Taking the monotonic downward switching as an example, if a P-type input dynamic comparator is used, when the common-mode input range is low, the comparator is faster but the noise performance is poor. When the common-mode input range is high, the comparator is slower but the noise performance is better. Therefore, when the traditional monotonic switching SAR ADC continues to reduce the common-mode input during the switching process, the noise performance of the comparator will become worse and worse. In the last switching process, the least significant bit (LSB) is switched. At this time, if the noise performance is poor, the effective number of bits of the SAR ADC will be reduced.

[0004] Therefore, a new successive approximation ADC and its control method need to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above problems, an object of the present disclosure is to provide an analog-to-digital converter and a control method thereof, so as to solve the problem of balancing noise and speed as the common-mode input voltage changes.

[0006] According to one aspect of the present disclosure, a control method of an analog-to-digital converter is provided, wherein the analog-to-digital converter has a successive approximation structure and comprises:

[0007] Comparator;

[0008] A first capacitor array, wherein a first end of each capacitor in the first capacitor array is connected to a non-inverting input end of the comparator;

[0009] A second capacitor array, wherein a first end of each capacitor in the second capacitor array is connected to an inverting input end of the comparator;

[0010] A first switch array, used to control the second end of each capacitor in the first capacitor array to select receiving a first reference voltage or a second reference voltage; and

[0011] a second switch array, configured to control the second end of each capacitor in the second capacitor array to select receiving the first reference voltage or the second reference voltage;

[0012] The control method comprises:

[0013] After the sampling stage, controlling the second ends of the capacitors corresponding to the first capacitor array and the second capacitor array to switch from the first reference voltage to the second reference voltage to adjust the common mode input voltage; and

[0014] According to a preset switching rule, from the first phase to the final phase, the second ends of the capacitors of the first capacitor array and the second capacitor array are switched so that in the final phase, the common-mode input voltage is a preset voltage.

[0015] Optionally, the comparator includes one of an N-type comparator and a P-type comparator.

[0016] Optionally, when the comparator comprises a P-type comparator, the first reference voltage is greater than the second reference voltage,

[0017] After the sampling phase, the second ends of the capacitors corresponding to the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

[0018] Optionally, the preset switching rule includes: in a preset last one or several phases, controlling the second end of the corresponding capacitor in the first capacitor array or the second capacitor array to switch from the second reference voltage to the first reference voltage.

[0019] Optionally, in the sampling phase, controlling the second ends of the first capacitor, the third capacitor and the fourth capacitor in the first capacitor array and the second capacitor array to receive the first reference voltage, and controlling the second ends of the remaining capacitors to receive the second reference voltage; and

[0020] The sampling switch is controlled so that a first input signal and a second input signal are input to the first capacitor array and the second capacitor array respectively.

[0021] Optionally, after the sampling phase and before the first phase,

[0022] Controlling the sampling switch to stop the first input signal and the second input signal from being input to the non-inverting input terminal and the inverting input terminal of the comparator; and

[0023] The second ends of the third capacitors of the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

[0024] Optionally, switching the second ends of the capacitors of the first capacitor array and the second capacitor array from the first phase to the final phase according to a preset switching rule includes:

[0025] In a first phase, controlling the second end of the first capacitor in the first capacitor array or the second capacitor array to switch from the first reference voltage to the second reference voltage;

[0026] In a fourth phase, controlling the second end of the fourth capacitor in the first capacitor array or the second capacitor array to switch from the first reference voltage to the second reference voltage; and

[0027] In other phases, the second ends of the capacitors corresponding to each phase in the first capacitor array or the second capacitor array are controlled to switch from the second reference voltage to the first reference voltage.

[0028] Optionally, in the sampling phase, the second ends of the first capacitor to the fourth capacitor in the first capacitor array and the second capacitor array are controlled to receive the first reference voltage, and the second ends of the remaining capacitors are controlled to receive the second reference voltage; and

[0029] The sampling switch is controlled so that a first input signal and a second input signal are input to the first capacitor array and the second capacitor array respectively.

[0030] Optionally, after the sampling phase and before the first phase,

[0031] Controlling the sampling switch to stop the first input signal and the second input signal from being input to the non-inverting input terminal and the inverting input terminal of the comparator; and

[0032] The second ends of the first capacitor to the fourth capacitor of the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

[0033] Optionally, switching the second ends of the capacitors of the first capacitor array and the second capacitor array from the first phase to the final phase according to a preset switching rule includes: controlling the second ends of the capacitors corresponding to each phase in the first capacitor array or the second capacitor array to switch from the second reference voltage to the first reference voltage from the first phase to the final phase.

[0034] According to another aspect of the present disclosure, there is provided an analog-to-digital converter having a successive approximation structure and comprising:

[0035] Comparator;

[0036] A first capacitor array, wherein a first end of each capacitor in the first capacitor array is connected to a non-inverting input end of the comparator;

[0037] A second capacitor array, wherein a first end of each capacitor in the second capacitor array is connected to an inverting input end of the comparator;

[0038] A first switch array, used to control the second end of each capacitor in the first capacitor array to select receiving a first reference voltage or a second reference voltage;

[0039] a second switch array, configured to control the second end of each capacitor in the second capacitor array to select receiving the first reference voltage or the second reference voltage; and

[0040] A control module controls the analog-to-digital converter using the control method described above.

[0041] One of the above technical solutions has the following beneficial effects:

[0042] In the comparison cycle conversion in the front stage of the SAR ADC, by allowing one end of the corresponding capacitor in the first capacitor array and the second capacitor array to switch from the first reference voltage to the second reference voltage at the same time, compared with the common-mode input voltage in the sampling stage, the amplitude of the common-mode input voltage after the synchronous switching of the capacitors is changed (for example, decreased), thereby improving the overall analog-to-digital conversion speed in the SAR ADC.

[0043] In addition, during the last few preset phases of the SAR ADC, the amplitude of the common-mode input voltage increases, thereby reducing the noise in the SAR ADC and increasing the effective number of bits.

[0044] Furthermore, the SAR ADC is controlled to switch the capacitors of each capacitor array according to a preset switching rule, so that at the final phase, the common-mode input voltage is a preset voltage. Therefore, no matter what the output result of the SAR ADC disclosed in the present invention is, when the final phase is reached, the common-mode input voltage is consistent and is a preset fixed value, so that the noise of the SAR ADC is more controllable.

[0045] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0047] Figure 1 A schematic diagram of waveforms of an input signal and a common-mode input voltage of a SAR ADC in the related art at each stage is shown;

[0048] Figure 2 A schematic diagram showing the relationship between the common-mode input voltage of a SAR ADC and noise and speed in the related art is shown;

[0049] Figure 3 A schematic diagram of the circuit structure of the SAR ADC according to an embodiment of the present disclosure is shown;

[0050] Figures 4 to 9 The circuit structure diagram of the control method of the SAR ADC in some stages of the first embodiment of the present disclosure is shown.

[0051] Fig.10 A schematic diagram showing waveforms of an input signal and a common-mode input voltage of a SAR ADC according to the first embodiment of the present disclosure at various stages is shown;

[0052] Figures 11 to 13 A circuit structure diagram of a control method for a SAR ADC according to a second embodiment of the present disclosure in some stages is shown;

[0053] Fig.14 A schematic diagram showing waveforms of the input signal and the common-mode input voltage of the SAR ADC according to the second embodiment of the present disclosure at various stages is shown. DETAILED DESCRIPTION

[0054] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0055] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0056] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0057] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0058] Figure 1 The figure shows the waveform diagram of the input signal and the common-mode input voltage of the SAR ADC in each stage in the related art.

[0059] See also Figure 1 In the related art, during the switching process of the monotonic switching SAR ADC, the common-mode input voltage Vicm will continue to decrease. Specifically, in the sampling phase Psa and the first phase P1, the first input signal VinP and the second input signal VinN remain consistent, and the voltage difference is △V1. In the second phase P2, the voltage difference between the first input signal VinP and the second input signal VinN is △V2. Among them, from the first phase P1 to the last phase, it is hoped that the difference between the first input signal VinP and the second input signal VinN tends to become smaller and smaller.

[0060] Figure 2FIG. 1 shows a schematic diagram of the relationship between the common-mode input voltage of the SAR ADC in the related art, noise and speed, respectively, wherein: Figure 2 The horizontal axis represents the common-mode input voltage Vicm, in millivolts (mV), the vertical axis on the left represents the noise, in millivolts (mV), and the vertical axis on the right represents the delay time, in picoseconds (ps). The solid line curve represents the changing trend of the noise, and the dotted line curve represents the changing trend of the delay amount.

[0061] See also Figure 2 , taking the monotonic downward switching type (only switching the capacitors in the first capacitor array or the second capacitor array from VREF to GND) as an example, if a P-type input dynamic comparator is used, as the common-mode input voltage Vicm decreases, the speed of the comparator increases, but the noise also increases. Conversely, when the common-mode input voltage Vicm is high, the speed of the comparator slows down but the noise decreases. If the comparator is an N-type input dynamic comparator, a monotonic upward switching type (only switching the capacitors in the first capacitor array or the second capacitor array from GND to VREF) is required, and the common-mode input voltage Vicm will continue to rise.

[0062] Therefore, in the related art, when the monotonic switching SAR ADC continuously lowers the common-mode input voltage Vicm during the switching process, the noise performance of the comparator will become worse and worse. The last switching process is to switch the least significant bit. If the noise is large at this time, the number of effective bits of the SAR ADC will be reduced. In addition, since the comparison speed in the early stage is slow in the gradual comparison process, the overall conversion speed of the SAR ADC is low. On the contrary, when the monotonic switching SAR ADC continuously increases the common-mode input voltage Vicm during the switching process, the speed of the comparator will become slower and slower, and the noise performance will become better and better.

[0063] The purpose of the present disclosure is to provide a successive approximation ADC and a control method thereof, so as to solve the problem of balancing noise and speed as the common-mode input voltage changes.

[0064] Figure 3 A circuit structure diagram of the SAR ADC according to an embodiment of the present disclosure is shown.

[0065] See also Figure 3 The circuit of the SAR ADC of the embodiment of the present disclosure includes: a first capacitor array 110, a second capacitor array 120, a comparator 130, a control module 140, a first switch array S1, a second switch array S2, and sampling switches S31 and S32. The comparator 130 is a P-type comparator.

[0066] The first capacitor array 110 includes a first capacitor C1 to an eleventh capacitor C11, and the capacitance values ​​of the capacitors C1 to C11 decrease in sequence. The first ends of the capacitors C1 to C11 are all connected to the non-inverting input end of the comparator 130. The first switch array S1 includes a plurality of switches, which correspond to the plurality of capacitors in the first capacitor array 110, respectively. The first switch array S1 is used to control the second end of each capacitor in the first capacitor array 110 to select receiving the first reference voltage VREF or the second reference voltage GND.

[0067] The second capacitor array 120 includes a first capacitor C1' to an eleventh capacitor C11', and the capacitance values ​​of the capacitors C1' to C11' decrease in sequence. The first ends of the capacitors C1' to C11' are all connected to the inverting input end of the comparator 130. The second switch array S2 includes a plurality of switches, which correspond to the plurality of capacitors in the second capacitor array 120, respectively. The second switch array S2 is used to control the second end of each capacitor in the second capacitor array 120 to select receiving the first reference voltage VREF or the second reference voltage GND.

[0068] The sampling switches S31 and S32 are used to control the first input signal VinP and the second input signal VinN to be input into the first capacitor array 110 and the second capacitor array 120 respectively.

[0069] The control module 140 sends a control signal Vctrl1 to the first switch array S1 and a control signal Vctrl2 to the second switch array S2 according to the output signal Dout of the comparator 130 and the preset switching rule, thereby controlling the second end of each capacitor in the first capacitor array 110 and the second capacitor array 120 to switch to the first reference voltage VREF or the second reference voltage GND. The first reference voltage VREF is greater than the second reference voltage GND.

[0070] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings for the number of capacitors in the first capacitor array 110 and the second capacitor array 120 as needed. Other settings may also be made for the capacitance value of each capacitor in the first capacitor array 110 and the second capacitor array 120. For example, the capacitance of the most significant bit (MSB) in this embodiment corresponds to the capacitors C1 and C1', and the capacitors C1 and C1' may be split into two or three smaller capacitors in other embodiments. In addition, the type of the comparator 130 may also be an N-type comparator.

[0071] Figures 4 to 9 FIG. 4 is a schematic diagram showing a circuit structure of a control method for a SAR ADC according to a first embodiment of the present disclosure in some stages. Fig.10Schematic diagram of waveforms of the input signal and common-mode input voltage of the SAR ADC of the first embodiment of the present disclosure at various stages is shown, wherein: Figures 4 to 9 The first switch array S1 and the second switch array S2 are omitted to more clearly illustrate the switching process of the capacitors.

[0072] In the first embodiment, the comparator 130 is a P-type comparator as an example for specific description. Figure 4 and Fig.10 In the sampling phase Psa, the control module 140 controls the second ends of the capacitors C1, C3, and C4 in the first capacitor array 110 to receive the first reference voltage VERF (high), and the second ends of the capacitors C2, C5, C6, C7, C8, C9, C10, and C11 to receive the second reference voltage GND (low). And the second ends of the capacitors C1', C3', and C4' in the second capacitor array 120 are controlled to receive the first reference voltage VERF (high), and the second ends of the capacitors C2', C5', C6', C7', C8', C9', C10', and C11' receive the second reference voltage GND (low). The sampling switches S31 and S32 are closed, so that the first input signal VinP and the second input signal VinN are input to the first capacitor array 110 and the second capacitor array 120 so as to be sampled and stored.

[0073] See also Figure 5 and Fig.10 , after the sampling phase Psa ends, the sampling switches S31 and S32 are disconnected. In the common-mode input voltage Vicm control phase Pc, the control module 140 controls the second end of the capacitor C3 in the first capacitor array 110 to switch from receiving the first reference voltage VERF to the second reference voltage GND (from high to low), and controls the second end of the capacitor C3' in the second capacitor array 120 to switch from high to low. Compared with the sampling phase Psa, in the control phase Pc, the decrease amplitude of the common-mode input voltage Vicm is VREF*C3 / Ctotal, where Ctotal is the sum of all the capacitance values ​​in the first capacitor array of digital-to-analog conversion (the sum of the capacitance values ​​also includes the parasitic capacitance not shown in the first capacitor array).

[0074] See also Figure 6 and Fig.10, the first cycle of comparison has been completed in the first phase P1, and it is concluded that the positive end is greater than the negative end. Specifically, since the first input signal VinP received by the comparator 130 is greater than the second input signal VinN in the control phase Pc, the voltage of the positive input terminal of the comparator 130 is greater than the voltage of the negative input terminal (the positive end is greater than the negative end). Since in the SAR ADC, it is hoped that the difference between the first input signal VinP and the second input signal VinN tends to become smaller and smaller, when the positive end of the comparator 130 is greater than the negative end, there are two options, one is to switch the capacitor C1 in the first capacitor array 110 from a high position to a low position, and the other option is to switch the capacitor C1' in the second capacitor array 120 from a low position to a high position. On the contrary, if the negative end of the comparator 130 is greater than the positive end, it is necessary to switch the capacitor C1 in the first capacitor array 110 from a low position to a high position, or to switch the capacitor C1' in the second capacitor array 120 from a high position to a low position in the first phase P1.

[0075] In order to be able to adjust the common-mode input voltage Vicm in a directionally manner, in this embodiment, it is necessary to execute a preset switching rule. In the first phase P1, the capacitor C1 or C1' is controlled to switch downward (from a high position to a low position), and in the fourth phase P4, the capacitor C4 or C4' is controlled to switch downward. In the second phase P2, the third phase P3, and the fifth phase P5 to the eleventh phase P11, the capacitors corresponding to each phase in the first capacitor array 110 or the second capacitor array 120 are controlled to switch upward. That is, P1: down, P2: up, P3: up, P4: down, P5: up, P6: up, and the subsequent ones are all up. Therefore, in this embodiment, since the positive end of the comparator 130 is greater than the negative end in the previous phase of the first phase P1, according to the preset switching rule P1: down, the capacitor C1 needs to be switched from the first reference voltage VREF to the second reference voltage GND.

[0076] Furthermore, in the sampling phase Psa, the connection of the capacitors is also determined according to the preset switching rules. For example, in the first phase P1, the capacitor C1 or C1' needs to be controlled to switch downward, and in the fourth phase P4, the capacitor C4 or C4' needs to be controlled to switch downward. Therefore, in the sampling phase Psa, the second ends of the capacitors C1, C1', C4, and C4' all need to be connected to the high position. In phases P2, P3, and P5 to P11, the corresponding capacitors switch upward. Therefore, in the sampling phase Psa, the second ends of the capacitors corresponding to phases P2, P3, and P5 to P11 originally need to be connected to the low position. However, since it is necessary to reduce the amplitude of the common-mode input voltage Vicm to VREF*C3 / Ctotal in the control phase Pc, in the sampling phase Psa, the second ends of the capacitors C3 and C3' need to be connected to the high position. After the control phase Pc ends, the second ends of the capacitors C3 and C3' will also switch to the low position. In the subsequent third phase P3, the preset switching rule P3: can still be executed.

[0077] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may set other settings for the preset switching rules and the control stage Pc to reduce the amplitude of the common-mode input voltage Vicm as needed. In addition, the control stage Pc is not limited to being set between the sampling stage Psa and the first phase P1. After the sampling stage Psa is completed, at any time point, as long as the positive end and the negative end are switched in the same direction at the same time, and the purpose is to adjust the speed and noise of the same comparator, it should be classified in this scheme.

[0078] See also Figure 7 and Fig.10 Since the positive terminal of the comparator 130 is greater than the negative terminal in the first phase P1, according to the preset switching rule P2:, the capacitor C2' needs to be switched from the second reference voltage GND to the first reference voltage VREF in the second phase P2. If the positive terminal of the comparator 130 is less than the negative terminal in the first phase P1, according to the preset switching rule P2:, the capacitor C2 needs to be switched from the second reference voltage GND to the first reference voltage VREF in the second phase P2.

[0079] See also Figure 8 and Fig.10 Since the positive terminal of the comparator 130 is smaller than the negative terminal in the second phase P2, according to the preset switching rule P3:, the capacitor C3 needs to be switched from the second reference voltage GND to the first reference voltage VREF in the third phase P3. If the positive terminal of the comparator 130 is larger than the negative terminal in the second phase P2, according to the preset switching rule P3:, the capacitor C3' needs to be switched from the second reference voltage GND to the first reference voltage VREF in the third phase P3.

[0080] See also Fig. 9 and Fig.10 Since the positive terminal of the comparator 130 is greater than the negative terminal in the third phase P3, according to the preset switching rule P4:, the capacitor C4 needs to be switched from the first reference voltage VREF to the second reference voltage GND in the fourth phase P4. If the positive terminal of the comparator 130 is less than the negative terminal in the third phase P3, according to the preset switching rule P4:, the capacitor C4' needs to be switched from the first reference voltage VREF to the second reference voltage GND in the fourth phase P4.

[0081] See also Fig.10 In the fifth phase P5 to the eleventh phase P11, according to the preset switching rule P5 to P11:, in this cycle, when the positive end is greater than the negative end, the capacitance of the negative end will be switched from a low position to a high position. Otherwise, the capacitance of the positive end will be switched from a low position to a high position.

[0082] The embodiments of the present disclosure are not limited thereto. For different up and down switching sequences, any method that adjusts the common-mode input amplitude to optimize the comparator speed and noise performance can become an alternative technical solution.

[0083] Figures 11 to 13 FIG. 4 is a schematic diagram showing a circuit structure of a control method for a SAR ADC according to a second embodiment of the present disclosure in some stages. Fig.14 Schematic diagram of waveforms of the input signal and common-mode input voltage of the SAR ADC of the second embodiment of the present disclosure at various stages is shown. Figures 11 to 13 The first switch array S1 and the second switch array S2 are omitted to more clearly illustrate the switching process of the capacitors.

[0084] In the second embodiment of the present disclosure, the comparator 130 is a P-type comparator as an example for specific description, and the preset switching rule is that, from the first phase P1 to the fourth phase P11, the corresponding capacitor is controlled to switch upward, that is, P1 to P11: up. Therefore, in the sampling stage Psa, the second ends of the capacitors C1 to C11 and C1' to C11' all need to be connected to the low position. However, since it is necessary to reduce the amplitude of the common-mode input voltage Vicm to VREF*(C1+C2+C3+C4) / Ctotal in the control stage Pc, the second ends of the capacitors C1 to C4 and C1' to C4' need to be connected to the high position in the sampling stage Psa. After the control stage Pc ends, the second ends of the capacitors C1 to C4 and C1' to C4' will also switch to the low position. In the subsequent first phase P1 to the fourth phase P4, the preset switching rule can still be executed: switch upward.

[0085] See also Fig.11 and Fig.14 In the sampling phase Psa, the control module 140 controls the second ends of the capacitors C1, C2, C3, and C4 in the first capacitor array 110 to receive the first reference voltage VERF (high), and the second ends of the capacitors C5 to C11 to receive the second reference voltage GND (low). And the second ends of the capacitors C1', C2', C3', and C4' in the second capacitor array 120 are controlled to receive the first reference voltage VERF (high), and the second ends of the capacitors C5' to C11' receive the second reference voltage GND (low). The sampling switches S31 and S32 are closed, so that the first input signal VinP and the second input signal VinN are input to the first capacitor array 110 and the second capacitor array 120 so as to be sampled and stored.

[0086] See also Fig.12 and Fig.14, after the sampling phase Psa ends, the sampling switches S31 and S32 are disconnected. In the common-mode input voltage Vicm control phase Pc, the control module 140 controls the second ends of the capacitors C1 to C4 in the first capacitor array 110 to switch from receiving the first reference voltage VREF to the second reference voltage GND (from high to low), and controls the second ends of the capacitors C1' to C4' in the second capacitor array 120 to also switch from high to low. Compared with the sampling phase Psa, in the control phase Pc, the decrease in the common-mode input voltage Vicm is VREF*(C1+C2+C3+C4) / Ctotal, where Ctotal is the sum of all the capacitance values ​​in the first capacitor array of digital-to-analog conversion (the sum of the capacitance values ​​includes the parasitic capacitance not shown in the first capacitor array).

[0087] See also Fig.13 and Fig.14 , since the positive terminal of the comparator 130 is greater than the negative terminal in the control phase Pc, according to the preset switching rule P1:, the capacitor C1' needs to be switched from the second reference voltage GND to the first reference voltage VREF in the first phase P1. If the positive terminal received by the comparator 130 is less than the negative terminal in the control phase Pc, according to the preset switching rule P1:, the capacitor C1 needs to be switched from the second reference voltage GND to the first reference voltage VREF in the first phase P1. The switching rules of subsequent phases are similar and will not be repeated here.

[0088] In the second embodiment of the present disclosure, each cycle from the first to the final phase is changed from the conventional downward switching to upward switching, which can make each cycle slower than the previous cycle, thereby making the noise smaller than the previous one.

[0089] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may set other settings for the preset switching rules and the control stage Pc to reduce the amplitude of the common-mode input voltage Vicm as needed. In addition, the control stage Pc is not limited to being set between the sampling stage Psa and the first phase P1. After the sampling stage Psa is completed, at any time point, as long as the positive end and the negative end are switched in the same direction at the same time, and the purpose is to adjust the speed and noise of the same comparator, it should be classified in this scheme.

[0090] In some related technologies, sometimes in the same comparison phase, the input common mode potential is switched in different directions because of different values ​​of the comparator output. This will cause the common mode input voltage to not be fixed when the entire analog-to-digital converter reaches the final phase, and the non-ideal effects of the comparator, such as the offset voltage caused by the mismatch effect, cannot be fixed, causing the performance of the analog-to-digital converter to decrease. In the scheme provided by the embodiment of the present disclosure, the entire digital-to-analog conversion process has been planned in advance. For example, when the preset switching rule of the first embodiment is used, the switching direction is always: common mode input range adjustment phase Pc: down, P1: down, P2: up, P3: up, P4: down, P5 and subsequent phases: up, when the final phase is reached, the common mode input voltage Vicm is all the preset value. Similarly, for example, when the preset switching rule of the second embodiment is used, the switching direction is always: common mode input range adjustment phase Pc: down, P1 and subsequent phases: up, when the final phase is reached, the common mode input voltage Vicm is all the preset value.

[0091] In the corresponding related art, the comparator is an N-type input dynamic comparator, and a monotonic upward switching method is used to make the common-mode input voltage Vicm continue to rise. According to the scheme of the embodiment of the present disclosure, when an N-type comparator is used, for example, several preset capacitors in the first capacitor array and the second capacitor array can be switched from GND to VREF at the same time during the sampling phase (at this time, GND is the first reference voltage, VREF is the second reference voltage, and the second reference voltage VREF is greater than the first reference voltage GND), so that the common-mode input voltage Vicm rises to a preset amplitude, and then in the preset phase in the middle of the cycle, the common-mode input voltage Vicm is reduced, and in the last few phases, the common-mode input voltage Vicm is increased, so as to balance the noise and speed of the circuit during the entire comparison process. The embodiment of the present disclosure is not limited to this. For different up and down switching sequences, as long as the method of adjusting the common-mode input amplitude to optimize the speed and noise performance of the comparator can become an alternative technical solution.

[0092] Compared to the SAR ADC in the related art, which may also have a change in the common-mode input voltage in each phase but does not specifically optimize the common-mode input voltage, the embodiment of the present disclosure can be freely adjusted and customized, including using a preset switching rule and controlling the capacitors corresponding to the first capacitor array and the second capacitor array to switch simultaneously to adjust the amplitude of the common-mode input voltage. Therefore, even in the same SAR ADC architecture, the noise and speed of the balanced circuit can still be optimized.

[0093] According to the embodiments of the present disclosure as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modifications based on the present disclosure. The scope of protection of the present disclosure shall be based on the scope defined by the claims of the present disclosure and their equivalents.

Claims

1. A control method for an analog-to-digital converter, wherein the analog-to-digital converter has a successive approximation structure and include: Comparator; A first capacitor array, wherein a first end of each capacitor in the first capacitor array is connected to a non-inverting input end of the comparator; A second capacitor array, wherein a first end of each capacitor in the second capacitor array is connected to an inverting input end of the comparator; A first switch array, used to control the second end of each capacitor in the first capacitor array to select receiving a first reference voltage or a second reference voltage; as well as a second switch array, configured to control the second end of each capacitor in the second capacitor array to select receiving the first reference voltage or the second reference voltage; The control method comprises: After the sampling stage, controlling the second ends of the capacitors corresponding to the first capacitor array and the second capacitor array to switch from the first reference voltage to the second reference voltage to adjust the common mode input voltage; as well as According to a preset switching rule, from the first phase to the final phase, the second ends of the capacitors of the first capacitor array and the second capacitor array are switched so that in the final phase, the common-mode input voltage is a preset voltage.

2. The control method according to claim 1, in, The comparator includes one of an N-type comparator and a P-type comparator.

3. The control method according to claim 1, in, When the comparator comprises a P-type comparator, the first reference voltage is greater than the second reference voltage, After the sampling phase, the second ends of the capacitors corresponding to the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

4. The control method according to claim 3, in, The preset switching rule includes: in a preset last one or several phases, controlling the second end of the corresponding capacitor in the first capacitor array or the second capacitor array to switch from the second reference voltage to the first reference voltage.

5. The control method according to claim 3, in, In the sampling phase, controlling the second ends of the first capacitor, the third capacitor and the fourth capacitor in the first capacitor array and the second capacitor array to receive the first reference voltage, and the second ends of the remaining capacitors to receive the second reference voltage; as well as The sampling switch is controlled so that a first input signal and a second input signal are input to the first capacitor array and the second capacitor array respectively.

6. The control method according to claim 5, in, After the sampling phase and before the first phase, Controlling the sampling switch to stop the first input signal and the second input signal from being input to the non-inverting input terminal and the inverting input terminal of the comparator; as well as The second ends of the third capacitors of the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

7. The control method according to claim 6, in, The switching of the second ends of the capacitors of the first capacitor array and the second capacitor array from the first phase to the final phase according to the preset switching rule includes: In a first phase, controlling the second end of the first capacitor in the first capacitor array or the second capacitor array to switch from the first reference voltage to the second reference voltage; In a fourth phase, controlling the second end of the fourth capacitor in the first capacitor array or the second capacitor array to switch from the first reference voltage to the second reference voltage; and In other phases, the second ends of the capacitors corresponding to each phase in the first capacitor array or the second capacitor array are controlled to switch from the second reference voltage to the first reference voltage.

8. The control method according to claim 3, in, In the sampling phase, the second ends of the first capacitor to the fourth capacitor in the first capacitor array and the second capacitor array are controlled to receive the first reference voltage, and the second ends of the remaining capacitors are controlled to receive the second reference voltage; as well as The sampling switch is controlled so that a first input signal and a second input signal are input to the first capacitor array and the second capacitor array respectively.

9. The control method according to claim 8, in, After the sampling phase and before the first phase, Controlling the sampling switch to stop the first input signal and the second input signal from being input to the non-inverting input terminal and the inverting input terminal of the comparator; as well as The second ends of the first capacitor to the fourth capacitor of the first capacitor array and the second capacitor array are controlled to switch from the first reference voltage to the second reference voltage to reduce the common mode input voltage.

10. The control method according to claim 9, in, The switching of the second ends of the capacitors of the first capacitor array and the second capacitor array from the first phase to the final phase according to the preset switching rule includes: controlling the second ends of the capacitors corresponding to each phase in the first capacitor array or the second capacitor array to switch from the second reference voltage to the first reference voltage from the first phase to the final phase.

11. An analog-to-digital converter having a successive approximation structure, and include: Comparator; A first capacitor array, wherein a first end of each capacitor in the first capacitor array is connected to a non-inverting input end of the comparator; A second capacitor array, wherein a first end of each capacitor in the second capacitor array is connected to an inverting input end of the comparator; A first switch array, used to control the second end of each capacitor in the first capacitor array to select receiving a first reference voltage or a second reference voltage; a second switch array, used for controlling the second end of each capacitor in the second capacitor array to select receiving the first reference voltage or the second reference voltage; as well as A control module, which controls the analog-to-digital converter using the control method according to any one of claims 1 to 10.

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