A TDC delay chain delay calibration system and calibration method based on direct digital synthesis

Abstract

A TDC delay chain time delay calibration system and calibration method based on direct digital synthesis calibrates TDC by generating a high-precision adjustable phase difference signal, thereby achieving accurate measurement and calibration of the delay chain nonlinearity. The signal generated by this method using DDS technology has high stability and a precisely controllable phase difference, which can produce a very small time step, thereby greatly improving the accuracy of the calibration. Through the coordinated work of the main control module, the signal screening module and the delay chain module, the calibration process can be completed automatically without the need for external complex equipment. This calibration system and calibration method are suitable for TDC applications under various environmental conditions, and can effectively deal with nonlinear changes caused by external factors such as temperature and voltage, providing strong technical support for high-precision time interval measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of digital measurement of time quantities, and in particular to a TDC delay chain time delay calibration system and calibration method based on direct digital synthesis (DDS). Background Art

[0002] Time-to-digital converter (TDC) is a precise time interval measurement technology, which is widely used in cutting-edge technology fields such as Beidou timing, laser radar, ultrasonic detection, particle physics experiments and frequency synthesis. It is also a key technology to ensure time and frequency synchronization in the construction of digital economy, blockchain and smart cities. This technology can convert the interval between two time events into a digital signal, providing key support for high-precision time measurement.

[0003] FPGA-based TDC design usually adopts a combination of coarse and fine counting methods. Coarse counting is responsible for counting the number of complete clock cycles between the start signal and the end signal, while fine counting accurately measures the time interval less than one clock cycle by counting the number of delay units that the signal passes through. Combining the coarse and fine counting results, a high-precision time interval measurement value can be obtained. The performance of TDC is mainly affected by three factors: the resolution is determined by the delay time of a single delay unit; the measurement range depends on the length of the delay chain; and the nonlinearity is affected by many factors, including the inconsistency of the delay unit time, chip process technology differences, voltage and temperature fluctuations, etc.

[0004] In order to evaluate and calibrate the nonlinearity of TDC, researchers have developed a code density test method. This method inputs a large number of random time intervals into the TDC, analyzes the distribution of the TDC's fine count output codes, and calculates the deviation between the actual output and the ideal output, thereby deriving the differential nonlinearity and integral nonlinearity values ​​of the TDC. Although this statistical method is widely used, it may have some inaccuracies. The core of the code density test is to evaluate its nonlinear characteristics by analyzing the output distribution of the TDC after a large number of random time intervals are input. However, in practical applications, this ideal state is difficult to achieve, and the statistical method itself may also introduce some errors. Summary of the invention

[0005] To solve the above problems, the purpose of the present invention is to propose a TDC delay chain delay calibration system and calibration method based on DDS. The TDC nonlinear calibration method proposed in the present invention adopts a TDC nonlinear calibration system, wherein the nonlinear calibration system includes a main control module, a DDS signal generation module, a signal screening module, a delay chain module, and a storage module.

[0006] The main control module is connected to other modules to control the initialization, operation enable and working status of other modules.

[0007] The DDS signal generation module is used to generate two square wave signals S1 and S2 with the same frequency and different phases. The output signal frequency is fixed at 150MHz, and the phase difference between the two output signals is adjustable from 0° to 360°. The phase difference is controlled by a 14-bit binary number, which can divide 360° into 16384 parts, each of which is 0.022°. From a time perspective, 1 / 150MHz=6.667ns, and a phase step of 0.022° per part can generate a time step of 6.667*0.022 / 360=0.407ps. That is, based on the S1 signal, the S2 signal has the same frequency as the S1 signal, and its phase is 0.407*N ps later than the S1 signal, where the number of signal control words N is controlled by the main control module.

[0008] The signal screening module is controlled by the main control module, and extracts a rising edge from the continuous signal S1 as the Start signal output of the delay chain. The rising edge of S2 closest to this rising edge is selected as the Stop signal output. The signal screening module screens out the Start and Stop signals once each time it is controlled by the main control module.

[0009] The delay chain module includes a delay chain unit, a sampling unit, and a decoding unit. The delay chain unit is composed of a plurality of identical delay components connected end to end. The sampling unit samples the delay chain unit according to the clock signal. The decoding unit decodes and outputs the data latched by the sampling unit. The Start signal is sent to the delay chain module and connected to the delay chain unit. The Stop signal is sent to the delay chain module and connected to the sampling unit.

[0010] The storage module is connected to the main control module and the decoding unit in the delay chain module, and is controlled by the main control module to store the output of the decoding unit.

[0011] The calibration method of the present invention comprises the following specific steps:

[0012] Step 1: At the beginning of calibration, the main control module controls the DDS signal generation module to generate two signals S1 and S2 with the same frequency and phase, and the value of the initialization signal control word N is 1.

[0013] Step 2: The main control module writes the signal control word N into the DDS signal generation module, so that the S2 signal has the same frequency as the S1 signal and a phase 0.407*N ps later than the S1 signal.

[0014] Step 3: The main control module controls the signal filtering module to filter out the Start and Stop signals from S1 and S2.

[0015] Step 4: Send the Start and Stop signals to the delay chain module, the Start signal to the delay chain unit, and the Stop signal to the sampling unit. After completing the measurement and sampling of the delay chain, the sampled data is decoded by the decoding unit, and the number M of delay components that the Start signal passes through from the Start signal to the Stop signal is decoded.

[0016] Step 5: The decoding unit sends M to the main control module, which adds one to the signal control word N and then starts to repeat the operations from step 2 to step 4. The above operations will be repeated many times until the output of the decoding unit jumps from M to M+1. The value of N at the time of the jump is recorded as Ndata, and the value of M+1 at the time of the jump is recorded as Maddr.

[0017] Step 6: The main control module controls and stores the values ​​of Maddr and Ndata into the storage module. Then, the operations of step 2 to step 5 are repeated. Finally, the number of Maddr is equal to the number of delay devices in the delay unit, and the calibration is stopped. At this time, the number of Maddr groups stored in the storage unit is recorded as the total time of each delay unit after calibration.

[0018] Beneficial effects of the present invention:

[0019] The present invention proposes a TDC delay chain delay calibration method based on DDS, which calibrates the TDC by generating a high-precision adjustable phase difference signal, thereby realizing accurate measurement and calibration of the delay chain nonlinearity. The signal generated by the DDS technology in this method has high stability and a precisely controllable phase difference, which can produce a very small time step, thereby greatly improving the accuracy of the calibration. Through the coordinated work of the main control module, the signal screening module and the delay chain module, the method can automatically complete the calibration process without the need for external complex equipment. This calibration method is suitable for TDC applications under various environmental conditions, and can effectively deal with nonlinear changes caused by external factors such as temperature and voltage, providing strong technical support for high-precision time interval measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a block diagram of a TDC delay chain delay calibration method based on DDS according to an embodiment of the present invention;

[0021] Figure 2 is a block diagram of a DDS signal generating module in an embodiment of the present invention;

[0022] Figure 3 It is a block diagram of the delay chain module of the embodiment of the present invention;

[0023] Figure 4A flowchart of a TDC nonlinear calibration method based on multi-delay chain switching according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Example

[0025] A TDC delay chain delay calibration system based on DDS, such as Figure 1 As shown, it includes a main control module, a DDS signal generation module, a signal screening module, a delay chain module and a storage module.

[0026] The main control module is connected to other modules and is responsible for controlling the initialization, working enablement and working status of each module.

[0027] The structure of DDS signal generation module is as follows Figure 2 As shown in the figure, it includes two identical circuits, each of which is composed of ADS9852 and low-pass filter circuit, which is used to generate two square wave signals S1 and S2 with the same frequency and adjustable phase difference. The output signal frequency is fixed at 150MHz, and the phase difference can be accurately adjusted in the range of 0°~360°, achieving a minimum time step of 0.407ps.

[0028] The signal filter module extracts the Start and Stop signals from the S1 and S2 signals under the control of the main control module. Only one set of Start and Stop signals is filtered out each time.

[0029] The structure of the delay chain module is as follows Figure 3 As shown, it includes a delay chain unit, a sampling unit and a decoding unit. The delay chain unit is composed of a plurality of identical delay components connected end to end, the sampling unit samples the delay chain, and the decoding unit decodes the sampling result.

[0030] The working process of the TDC delay chain delay calibration method of the present invention is as follows: Figure 4 As shown, the steps include:

[0031] Step 1: At the beginning of calibration, the main control module controls the DDS signal generation module to generate two signals S1 and S2 with the same frequency and phase, and the value of the initialization signal control word N is 1.

[0032] Step 2: The main control module writes the signal control word N into the DDS signal generation module, so that the S2 signal has the same frequency as the S1 signal and a phase 0.407*N ps later than the S1 signal.

[0033] Step 3: The main control module controls the signal filtering module to filter out the Start and Stop signals from S1 and S2.

[0034] Step 4: Send the Start and Stop signals to the delay chain module, the Start signal to the delay chain unit, and the Stop signal to the sampling unit. After completing the measurement and sampling of the delay chain, the sampled data is decoded by the decoding unit, and the number M of delay components that the Start signal passes through from the Start signal to the Stop signal is decoded.

[0035] Step 5: The decoding unit sends M to the main control unit, and the main control module adds one to the signal control word N, and then starts to repeat the operations of steps 2 to 4. The above operations will be repeated many times until the output of the decoding unit jumps from M to M+1. The value of N at the time of the jump is recorded as Ndata, and the value of M+1 at the time of the jump is recorded as Maddr.

[0036] Step 6: The main control unit controls and stores the values ​​of Maddr and Ndata into the storage module. Then, the operations of step 2 to step 5 are repeated. Finally, the number of Maddr is equal to the number of delay devices in the delay unit, and the calibration is stopped. At this time, the number of Maddr groups stored in the storage unit is recorded as the total time of each delay unit after calibration.

Claims

1. A time-to-digital converter (TDC) delay chain delay calibration system based on direct digital synthesis (DDS), characterized in that The calibration system includes a main control module, a DDS signal generation module, a signal screening module, a delay chain module, and a storage module. The main control module is connected to the DDS signal generation module, signal screening module, delay chain module and storage module to control the initialization, working enable and working status of the DDS signal generation module, signal screening module, delay chain module and storage module; The DDS signal generation module includes two identical circuits, each of which includes ADS9852 and a low-pass filter circuit, which is used to generate two square wave signals S1 and S2 with the same frequency and adjustable phase difference. The output signal frequency is fixed at 150MHz, and the phase difference can be accurately adjusted in the range of 0° to 360° to achieve a minimum time step of 0.407ps. The signal screening module is controlled by the main control module, and extracts a rising edge from the continuous square wave signal S1 as the Start signal output of the delay chain, and selects the rising edge of S2 closest to the rising edge as the Stop signal output; the signal screening module screens out the Start and Stop signals once each time it is controlled by the main control module; The delay chain module includes a delay chain unit, a sampling unit, and a decoding unit, wherein the delay chain unit is composed of a plurality of identical delay components connected end to end; the sampling unit samples the delay chain unit according to a clock signal; The decoding unit decodes and outputs the data latched by the sampling unit; the Start signal is sent to the delay chain module and connected to the delay chain unit; the Stop signal is sent to the delay chain module and connected to the sampling unit; The storage module is connected to the main control module and the decoding unit in the delay chain module, and is controlled by the main control module to store the output of the decoding unit.

2. The time delay calibration system of a time-to-digital converter (TDC) delay chain based on direct digital synthesis (DDS) according to claim 1, characterized in that: The phase difference is specifically controlled by a 14-bit binary number, dividing 360° into 16384 parts, each with a phase step of 0.022°, resulting in a time step of 6.667*0.022 / 360=0.407ps; taking the S1 signal as a reference, the S2 signal has the same frequency as the S1 signal, and its phase is 0.407*N ps later than the S1 signal, where N is the signal control word, and its number is controlled by the main control module.

3. A calibration method for a time delay calibration system of a time-to-digital converter (TDC) delay chain based on direct digital synthesis (DDS) according to any one of claims 1 to 2, wherein the specific calibration steps are as follows: Step 1: At the beginning of calibration, the main control module controls the DDS signal generation module to generate two signals S1 and S2 with the same frequency and phase, and the value of the initialization signal control word N is 1; Step 2: The main control module writes the signal control word N into the DDS signal generation module, so that the S2 signal has the same frequency as the S1 signal and the phase is 0.407*N ps later than the S1 signal; Step 3: The main control module controls the signal filtering module to filter out the Start and Stop signals from S1 and S2; Step 4: Send the Start and Stop signals to the delay chain module, where the Start signal is sent to the delay chain unit of the delay chain module, and the Stop signal is sent to the sampling unit of the delay chain module to complete a delay chain measurement and sampling. The sampled data is decoded by the decoding unit. The decoding starts from the Start signal and ends with the Stop signal. The number of delay components that the Start signal passes through is M; Step 5: The decoding unit sends M to the main control module, and the main control module adds one to the signal control word N, and then starts to repeat the operations from step 2 to step 4. The above operations will be repeated many times until the output of the decoding unit jumps from M to M+1; the value of N at the time of the jump is recorded as Ndata, and the value of M+1 at the time of the jump is recorded as Maddr; Step 6: The main control module controls and stores the values ​​of Maddr and Ndata into the storage module; then repeats the operations of step 2 to step 5; until finally, the number of Maddr is equal to the number of delay devices in the delay unit, and the calibration is stopped. At this time, the storage unit stores the number of Maddr groups, which is recorded as the total time accumulated by each delay unit after calibration.

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