Optical module

Abstract

The invention discloses an optical module, and an MCU is used for adjusting a first trigger signal into a second trigger signal, so that the falling edge of the second trigger signal falls in a burst optical signal. The MCU comprises a time delay circuit and a logic circuit, the input end of the time delay circuit is used for receiving the first trigger signal, the output end of the time delay circuit is connected with the first input end of the logic circuit, the second input end of the logic circuit is used for receiving the first trigger signal, and the output end of the logic circuit is used for outputting a second trigger signal. The delay circuit is used for delaying the first trigger signal. The logic circuit outputs a second trigger signal according to first trigger signals of the first input end and the second input end. The delay time of the delay circuit is smaller than the signal width of the burst optical signal. In the application, the MCU adjusts the first trigger signal into the second trigger signal with the falling edge falling in the burst optical signal, so that the sampling capacitor controlled by the second trigger signal is charged completely, and deviation of the received optical power sampled by the optical module is avoided.

Description

Technical Field

[0001] The present application relates to the field of optical fiber communication technology, and in particular to an optical module. Background Art

[0002] OLT includes OLT system equipment and OLT optical module. After the ONU successfully registers with the OLT, the OLT system equipment will control the ONU to send a burst optical signal in the allocated time slot. At the same time, the MAC chip in the OLT system equipment sends a trigger signal (Trigger) to the OLT optical module in the corresponding time slot. The Trigger directly controls the sampling capacitor in the OLT optical module. The OLT optical module calculates the signal strength of the current burst optical signal based on the charging status of the sampling capacitor.

[0003] However, different OLT system devices send different trigger widths, and the trigger signal falls at different positions within the burst optical signal. When the falling edge of the trigger falls outside the burst optical signal, the sampling capacitor controlled by the trigger will not be fully charged, which will cause the received optical power sampled by the OLT optical module to be too small. Summary of the invention

[0004] The present application provides an optical module to avoid deviation in received optical power obtained by sampling.

[0005] An optical module, comprising:

[0006] The light receiving component comprises:

[0007] A photodetector, used for receiving a burst optical signal and converting the burst optical signal into a first current signal;

[0008] The circuit board is connected to the light receiving component and is provided with:

[0009] A mirror current source, a first output end of which is connected to the photodetector, and is used to mirror the first current signal into a second current signal;

[0010] A sampling circuit is connected to the second output terminal of the mirror current source and is used to collect a second current signal according to a second trigger signal;

[0011] The MCU is connected to the sampling circuit and is used to adjust the first trigger signal to the second trigger signal so that the falling edge of the second trigger signal falls within the burst optical signal; wherein the MCU includes a delay circuit and a logic circuit, the input end of the delay circuit is used to receive the first trigger signal, the output end of the delay circuit is connected to the first input end of the logic circuit, the second input end of the logic circuit is used to receive the first trigger signal, the output end of the logic circuit is used to output the second trigger signal, the delay circuit is used to delay the first trigger signal, and the logic circuit is used to output the second trigger signal according to the first trigger signal at the first input end and the first trigger signal at the second input end, wherein the delay time of the delay circuit is less than the signal width of the burst optical signal.

[0012] Beneficial effects: The present application provides an optical module, including a circuit board and a light receiving component, which is connected to the circuit board. The light receiving component includes a photodetector, which is used to receive a burst optical signal and convert the burst optical signal into a first current signal. A mirror current source, a sampling circuit and an MCU are provided on the circuit board, wherein the first output end of the mirror current source is connected to the photodetector, the second output end of the mirror current source is connected to the sampling circuit, and the MCU is also connected to the sampling circuit. The mirror current source is used to mirror the first current signal into a second current signal. The sampling circuit is used to collect the second current signal according to the second trigger signal. When the falling edge of the Trigger falls outside the burst optical signal, the sampling capacitor controlled by the Trigger will be incompletely charged, thereby causing the received optical power obtained by sampling the OLT optical module to be too small. In order to avoid this problem, the MCU is designed to adjust the first trigger signal to the second trigger signal so that the falling edge of the second trigger signal falls within the burst optical signal. Wherein, the MCU includes a delay circuit and a logic circuit, the input end of the delay circuit is used to receive the first trigger signal, the output end of the delay circuit is connected to the first input end of the logic circuit, the second input end of the logic circuit is used to receive the first trigger signal, and the output end of the logic circuit is used to output the second trigger signal. The delay circuit is used to delay the first trigger signal. The logic circuit outputs the second trigger signal according to the first trigger signal of the first input end and the first trigger signal of the second input end. When the first trigger signal is at a low level, the first trigger signal of the second input end of the logic circuit is at a low level, the first trigger signal of the first input end of the logic circuit is at a low level, the reverse of the first trigger signal of the first input end of the logic circuit is still at a high level, and the second trigger signal outputted from the output end of the logic circuit is at a low level. Since the delay circuit is used to delay the first trigger signal entering the first input end of the logic circuit, when the first trigger signal is switched from a low level to a high level, the first trigger signal of the second input end of the logic circuit is instantly switched from a low level to a high level, the first trigger signal of the first input end of the logic circuit is still at a low level, the reverse of the first trigger signal of the first input end of the logic circuit is at a high level, and the second trigger signal outputted from the output end of the logic circuit is switched from a low level to a high level. When the first trigger signal switches from a low level to a high level and then remains at a high level, the first trigger signal at the second input end of the logic circuit is at a high level, the first trigger signal at the first input end of the logic circuit is at a high level, the reverse of the first trigger signal at the first input end of the logic circuit is at a low level, and the second trigger signal output from the output end of the logic circuit switches from a high level to a low level. When the first trigger signal switches from a low level to a high level, the second trigger signal also switches from a low level to a high level; when the first trigger signal switches from a low level to a high level and then remains at a high level, the second trigger signal switches from a high level to a low level.The delay time of the delay circuit is much smaller than the signal width of the burst optical signal, and the signal width of the second trigger signal is much smaller than the signal width of the burst optical signal, so that the falling edge of the second trigger signal will not fall outside the burst optical signal. In the present application, the delay circuit and the logic circuit cooperate with each other, and the delay time of the delay circuit is smaller than the signal width of the burst optical signal, so that the MCU adjusts the first trigger signal to the second trigger signal, and the falling edge of the second trigger signal falls within the burst optical signal, thereby making the sampling capacitor controlled by the second trigger signal fully charged, avoiding deviations in the received optical power obtained by sampling the optical module. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0014] Figure 1 A partial architecture diagram of an optical communication system provided according to some embodiments;

[0015] Figure 2 A partial structural diagram of a host computer provided according to some embodiments;

[0016] Figure 3 A structural diagram of an optical module provided according to some embodiments;

[0017] Figure 4 is an exploded view of an optical module provided according to some embodiments;

[0018] Figure 5 A structural diagram of an optical module with a housing and unlocking components removed according to some embodiments;

[0019] Figure 6 A sampling principle diagram of an optical module provided according to some embodiments;

[0020] Figure 7 A structural diagram of an MCU provided according to some embodiments;

[0021] Figure 8 A structural diagram of a first delay circuit provided according to some embodiments;

[0022] Fig. 9 is a structural diagram of a second delay circuit provided according to some embodiments;

[0023] Fig.10is a structural diagram of a third delay circuit provided according to some embodiments;

[0024] Fig.11 It is a structural diagram of a fourth delay circuit provided according to some embodiments. DETAILED DESCRIPTION

[0025] Optical communication technology establishes information transmission between information processing devices. Optical communication technology loads information onto light and uses the propagation of light to achieve information transmission. Light loaded with information is an optical signal. When optical signals propagate in information transmission equipment, they can reduce the loss of optical power and achieve high-speed, long-distance, and low-cost information transmission. Information that can be processed by information processing equipment exists in the form of electrical signals. Optical network terminals / gateways, routers, switches, mobile phones, computers, servers, tablets, and televisions are common information processing devices, and optical fibers and optical waveguides are common information transmission equipment.

[0026] The mutual conversion of optical signals and electrical signals between information processing equipment and information transmission equipment is realized through optical modules. For example, an optical fiber is connected to the optical signal input end and / or the optical signal output end of the optical module, and an optical network terminal is connected to the electrical signal input end and / or the electrical signal output end of the optical module; the first optical signal from the optical fiber is transmitted into the optical module, the optical module converts the first optical signal into a first electrical signal, and the optical module transmits the first electrical signal into the optical network terminal; the second electrical signal from the optical network terminal is transmitted into the optical module, the optical module converts the second electrical signal into a second optical signal, and the optical module transmits the second optical signal into the optical fiber. Since information processing devices can be connected to each other through an electrical signal network, at least one type of information processing device needs to be directly connected to the optical module, and it is not necessary for all types of information processing devices to be directly connected to the optical module. The information processing device directly connected to the optical module is called the host computer of the optical module.

[0027] Figure 1 FIG. 1 is a partial architecture diagram of an optical communication system provided according to some embodiments. Figure 1 As shown, the optical communication system is partially presented as a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 and a network cable 103 .

[0028] One end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end is connected to the optical interface of the optical module 200. The optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the direction of total reflection can almost maintain the original optical power. The optical signal is totally reflected multiple times in the optical fiber 101, and the optical signal from the direction of the remote information processing device 1000 is transmitted into the optical module 200, or the light from the optical module 200 is propagated toward the remote information processing device 1000, so as to realize long-distance and low-power-loss information transmission.

[0029] The number of optical fibers 101 may be one or more (two or more); the optical fiber 101 and the optical module 200 may be connected in a pluggable movable manner or in a fixed manner.

[0030] The host computer 100 has an optical module interface 102, which is configured to access the optical module 200, so that the host computer 100 establishes a unidirectional / bidirectional electrical signal connection with the optical module 200; the host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor and control the working status of the optical module 200.

[0031] The host computer 100 has an external electrical interface, such as a Universal Serial Bus (USB) interface and a network cable interface 104, which can be connected to an electrical signal network. For example, the network cable interface 104 is configured to connect to the network cable 103, so that the host computer 100 and the network cable 103 establish a unidirectional / bidirectional electrical signal connection.

[0032] Optical Network Unit (ONU), Optical Line Terminal (OLT), Optical Network Equipment (ONT) and Data Center Server are common host computers.

[0033] One end of the network cable 103 is connected to the local information processing device 2000 , and the other end is connected to the host computer 100 . The network cable 103 establishes an electrical signal connection between the local information processing device 2000 and the host computer 100 .

[0034] For example, the third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal. The optical module 200 transmits the second optical signal into the optical fiber 101. The second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.

[0035] For example, a first optical signal from the direction of a remote information processing device 1000 propagates through the optical fiber 101, the first optical signal from the optical fiber 101 is transmitted into the optical module 200, the optical module 200 converts the first optical signal into a first electrical signal, the optical module 200 transmits the first electrical signal into the host computer 100, the host computer 100 generates a fourth electrical signal based on the first electrical signal, and the host computer 100 transmits the fourth electrical signal to the local information processing device 2000.

[0036] The optical module is a tool for realizing the mutual conversion between optical signals and electrical signals. During the conversion process between optical signals and electrical signals, the information does not change, but the encoding and decoding method of the information can change.

[0037] Figure 2 FIG. 1 is a partial structural diagram of a host computer according to some embodiments. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structures related to the host computer 100 and the optical module 200 are shown. Figure 2 As shown, the host computer 100 also includes a PCB circuit board 105 arranged in the shell, a cage 106 arranged on the surface of the PCB circuit board 105, a heat sink 107 arranged on the cage 106, and an electrical connector (not shown in the figure) arranged inside the cage 106. The heat sink 107 has a protruding structure that increases the heat dissipation area, and the fin-shaped structure is a common protruding structure.

[0038] The optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is transferred to the cage 106 and then diffused through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 106.

[0039] Figure 3 is a structural diagram of an optical module provided according to some embodiments, Figure 4 FIG. 1 is an exploded view of an optical module provided according to some embodiments. Figure 3 and Figure 4 As shown, the optical module 200 includes a shell, a circuit board 300 disposed in the shell, a light emitting component 400 and a light receiving component 500. However, the present disclosure is not limited thereto. In some embodiments, the optical module 200 includes one of the light emitting component 400 and the light receiving component 500.

[0040] The housing comprises an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square body.

[0041] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and arranged perpendicular to the bottom plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0042] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and vertically arranged with the bottom plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and vertically arranged with the cover plate 2011, and the two upper side plates are combined with the two lower side plates 2022 to realize that the upper shell 201 covers the lower shell 202.

[0043] The direction of the line connecting the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or may be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 ( Figure 3 The opening 205 is also located at the end of the optical module 200 ( Figure 3 Alternatively, the opening 204 is located at the end of the optical module 200, and the opening 205 is located at the side of the optical module 200. The opening 204 is an electrical interface, and the gold finger of the circuit board 300 extends from the electrical interface and is inserted into the electrical connector of the host computer; the opening 205 is an optical port, which is configured to access the optical fiber 101 so that the optical fiber 101 is connected to the optical emitting component 400 and / or the optical receiving component 500 in the optical module 200.

[0044] The assembly method of combining the upper shell 201 and the lower shell 202 is adopted, which facilitates the installation of components such as the circuit board 300, the light emitting component 400, and the light receiving component 500 into the above-mentioned shell, and the upper shell 201 and the lower shell 202 can encapsulate and protect the shapes of these components. In addition, when assembling components such as the circuit board 300, the light emitting component 400 and the light receiving component 500, it is convenient to deploy the positioning components, heat dissipation components, and electromagnetic shielding components of these devices, which is conducive to the automated implementation of production.

[0045] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials to facilitate electromagnetic shielding and heat dissipation.

[0046] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0047] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a snap-fit ​​component that matches the cage 106 of the host computer. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the snap-fit ​​component and the host computer, so as to release the snap-fit ​​fixed connection between the optical module 200 and the host computer, so that the optical module 200 can be pulled out of the cage 106.

[0048] The circuit board 300 includes circuit traces, electronic components and chips, etc. The electronic components and chips are connected together according to the circuit design through the circuit traces to realize the functions of power supply, electrical signal transmission and grounding. The electronic components may include capacitors, resistors, triodes, metal-oxide-semiconductor field-effect transistors (MOSFET), etc. The chips may include microcontroller units (MCU), laser driver chips, transimpedance amplifiers (TIA), limiting amplifiers, clock and data recovery chips (CDR), power management chips, and digital signal processing (DSP) chips.

[0049] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board is also easy to insert into the electrical connector in the upper computer cage.

[0050] The circuit board 300 also includes a gold finger formed on the end surface thereof, and the gold finger is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger is connected to the electrical connector in the cage 106. The gold finger can be provided on the surface of only one side of the circuit board 300 (for example, Figure 4 The gold finger is configured to establish an electrical connection with the host computer to achieve power supply, grounding, I2C signal transmission, data signal transmission, etc.

[0051] Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.

[0052] The light emitting component 400 and / or the light receiving component 500 are located on a side of the circuit board 300 away from the gold finger; in some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors; in some embodiments, the light emitting component and / or the light receiving component can be directly set on the circuit board 300, can be set on the surface of the circuit board, and can also be set on the side of the circuit board.

[0053] In some embodiments, the light receiving component 500 includes a photodetector and a transimpedance amplifier, and the photodetector is connected to a transimpedance amplifier (TIA). The photodetector is used to receive a burst optical signal and convert the burst optical signal into a first current signal. The transimpedance amplifier is used to convert the first current signal into a voltage signal and amplify the voltage signal.

[0054] The present application does not limit the specific form of the photodetector. For example, an avalanche photodiode (APD) is a common photodetector; after a reverse bias voltage is applied to the PN junction of the APD, the received photons are absorbed by the PN junction to form a photocurrent; increasing the reverse bias voltage will multiply the photocurrent, resulting in an "avalanche" phenomenon.

[0055] like Figure 4 As shown, the optical receiving component 500 includes a receiving tube socket, a receiving tube cap and a receiving tube pin. The receiving tube cap is covered on the receiving tube socket. A photodetector and a transimpedance amplifier are arranged on the receiving tube socket. The receiving tube pin extends from the bottom surface of the receiving tube socket to the top surface of the receiving tube socket. One end of the receiving tube pin is connected to the circuit board 300 through a flexible circuit board, and the other end of the receiving pin is connected to the photodetector and the transimpedance amplifier on the receiving tube socket.

[0056] Figure 5 A structural diagram of an optical module with a housing and unlocking components removed according to some embodiments. Figure 6 FIG. 1 is a sampling principle diagram of an optical module according to some embodiments. Figure 5 and Figure 6As shown, in some embodiments, an MCU 301, a mirror current source 302, a boost circuit 303, a sampling circuit 304 and a holding circuit 305 are provided on the circuit board 300, an input end of the mirror current source 302 is connected to the boost circuit 303, a first output end of the mirror current source 302 is connected to the photodetector of the light receiving component 500, a second output end of the mirror current source 302 is connected to a first end of the sampling circuit 304, a second end of the sampling circuit 304 is connected to a first end of the holding circuit 305, a third end of the sampling circuit 304 is connected to the MCU 301, and a second end of the holding circuit 305 is also connected to the MCU 301.

[0057] In the present application, the first trigger signal is adjusted to the second trigger signal by MCU301, so that the falling edge of the second trigger signal is located within the burst optical signal; the first current signal is mirrored by the mirror current source to obtain the second current signal; the second current signal is collected according to the second trigger signal by the sampling circuit 304, and the second current signal is converted into a sampling voltage. At the same time, the sampling voltage at both ends of the sampling capacitor is maintained for a preset time by the holding circuit 305 to ensure the relative stability of the sampling voltage. MCU301 then monitors the burst received optical power by reading the sampling voltage maintained by the holding circuit 305, while ensuring the monitoring accuracy.

[0058] Since the photodetector (eg APD) needs to work under a relatively high bias voltage, in some embodiments, a boost circuit 303 is provided on the circuit board 300. The boost circuit 303 is used to provide the photodetector with a relatively high bias voltage required for operation.

[0059] Since the photodetector requires a relatively high reverse bias voltage, in some embodiments, the positive electrode of the boost circuit 303 is electrically connected to the negative electrode of the photodetector, and the negative electrode of the boost circuit is grounded. The positive electrode of the photodetector is electrically connected to the positive electrode of the transimpedance amplifier, and the negative electrode of the transimpedance amplifier is also grounded, and then connected to the ground of the boost circuit through the ground of the transimpedance amplifier to increase the reverse bias voltage to the photodetector.

[0060] Since the working bias voltage of the photodetector is obtained by boosting the voltage using a boost switch circuit, switching the switch back and forth will bring about a large noise. Therefore, in some embodiments, the boost circuit 303 is electrically connected to a filter capacitor CH with a high withstand voltage. The capacitance of the filter capacitor has a preset range. If the capacitance of the filter capacitor is lower than a certain value, the filtering effect is not good, resulting in a poor signal-to-noise ratio of the photodetector, and thus poor sensitivity; if the capacitance of the filter capacitor is higher than a certain value, due to the large power difference between different optical packets reaching the OLT, generally within a dynamic range of 15dB, if the front light is strong, the front light will form charge accumulation in CH, resulting in tailing. After the rear light arrives, it will be superimposed on the front light tailing, resulting in distortion of the monitoring optical power, which exemplarily causes the monitoring optical power to be too large.

[0061] In some embodiments, the host computer MAC chip sends a first trigger signal Trigger to MCU301 to specify the corresponding received optical power monitoring when a certain ONU optical module reaches the OLT. Exemplarily, when the host computer needs to monitor the received optical power of a certain burst optical signal, the host computer MAC chip sends the first trigger signal Trigger to MCU301 through the gold finger.

[0062] However, different OLT system devices send different Trigger widths, and the Trigger signal falls at different positions within the burst optical signal. When the falling edge of the Trigger falls outside the burst optical signal, the sampling capacitor controlled by the Trigger will not be fully charged, which will cause the received optical power sampled by the OLT optical module to be too small. In order to avoid this problem, in some embodiments, the first trigger signal Trigger is adjusted to the second trigger signal Trigger1 through MCU301, so that the falling edge of the second trigger signal Trigger1 is located within the burst optical signal.

[0063] Since the response current of the photodetector is different under different light intensities, the mirror current source 302 is used to mirror the current flowing to the photodetector. Then the current flowing to the photodetector can directly reflect the size of the received optical power. Therefore, the burst received optical power can be monitored by collecting the current flowing to the photodetector.

[0064] like Figure 6 As shown, in some embodiments, the mirror current source 302 includes a first transistor and a second transistor that are symmetrically arranged. The first transistor and the second transistor are PNP transistors, and may also be other types of transistors.

[0065] The emitter of the first transistor is electrically connected to the input end of the mirror current source 302, that is, to the output end of the boost circuit 303, to receive the bias voltage provided by the boost circuit 303; the collector of the first transistor is electrically connected to the photodetector to output a first current signal; the base of the first transistor is electrically connected to the base of the second transistor.

[0066] The emitter of the second transistor is electrically connected to the input end of the mirror current source 302, that is, to the output end of the boost circuit 303; the collector of the second transistor is electrically connected to the sampling circuit 304 to output a second current signal.

[0067] The current magnitudes of the first current signal and the second current signal are in a certain ratio. For example, a delay resistor R1 is provided between the first transistor and the photodetector, and a second resistor R2 is provided between the second transistor and the sampling circuit 304, then the first current signal*R1=the second current signal*R2, and then the first current signal: the second current signal=R2:R1. For example, the first current signal: the second current signal is 10:5.

[0068] like Figure 6 As shown, in some embodiments, the image current is collected by the sampling circuit 304 to monitor the burst received optical power. The sampling circuit 304 includes a sampling switch and a sampling capacitor, the sampling switch has a control end, a fixed end, a first active end and a second active end, the control end of the sampling switch is connected to the MCU, the fixed end of the sampling switch is connected to the sampling capacitor, the first active end of the sampling switch is connected to the second output end of the image current source 302, and the second active end of the sampling switch is connected to one end of the holding circuit.

[0069] The sampling switch receives the second trigger signal Trigger1 sent by the MCU through the control end. The sampling switch is used to turn on or off the connection between the second current source and the sampling capacitor according to the high and low level attributes of the second trigger signal Trigger1, so as to respond to or interrupt the charging of the sampling capacitor. Exemplarily, when the received second trigger signal Trigger1 is at a low level, no action is triggered. When the second trigger signal Trigger1 is at a high level, the sampling switch turns on the connection between the second output end of the mirror current source 302 and the sampling capacitor, and the sampling capacitor starts to charge. The second current signal output from the second output end of the mirror current source 302 charges the sampling capacitor, and the current is converted into an average voltage during the charging process; when the second trigger signal Trigger1 reaches the falling edge, that is, when the second trigger signal Trigger1 is converted from a high level to a low level, the sampling switch disconnects the connection between the second output end of the mirror current source 302 and the sampling capacitor, thereby interrupting the charging of the sampling capacitor.

[0070] In some embodiments, when the received second trigger signal Trigger1 is at a high level, the sampling switch turns on the connection between the second output terminal of the mirror current source 302 and the sampling capacitor, thereby responding to the charging of the sampling capacitor. The second current signal output from the second output terminal of the mirror current source 302 charges the sampling capacitor. The sampling capacitor has an averaging effect during the charging process, and the second current signal output from the second output terminal of the mirror current source 302 is converted into an average voltage. The average voltage represents the average effect of the output voltage of the transimpedance amplifier, eliminates unstable factors such as optical packet jitter, reduces errors, and increases measurement accuracy. When the second trigger signal Trigger1 is converted from a high level to a low level, the sampling switch disconnects the connection between the second output terminal of the mirror current source 302 and the sampling capacitor, thereby interrupting the charging of the sampling capacitor.

[0071] The optical module has different interrupt priorities for the second trigger signal Trigger1, so the time for triggering the interrupt when MCU301 receives the second trigger signal Trigger1 is not fixed, resulting in a time deviation in the reading of MCU301, so that different voltage values ​​may be read at different times, reducing the reading accuracy. At the same time, since the ADC conversion module of MCU302 requires a certain amount of time to perform signal conversion, when the second trigger signal Trigger1 has a falling edge, the voltage at both ends of the sampling capacitor is maintained by the holding circuit 305, and the collected voltage is maintained for a preset time, ensuring the relative stability of the voltage and the accuracy of the reading of MCU301.

[0072] like Figure 6 As shown, in some embodiments, the optical module further includes a limiting amplifier (LA), which is connected to the transimpedance amplifier. The LA can be placed on the receiving tube socket or on the circuit board 300. The voltage signal output by the TIA is transmitted to the LA, and then transmitted to the host computer after being processed by the LA. The voltage signal output by the TIA forms a digital service channel with the signal branch where the LA is located.

[0073] Figure 7 FIG. 1 is a structural diagram of an MCU provided according to some embodiments. Figure 7As shown, in some embodiments, the MCU includes a delay circuit 3011 and a logic circuit 3012, the input end of the delay circuit 3011 is used to receive the first trigger signal, the output end of the delay circuit 3011 is connected to the first input end (end A) of the logic circuit 3012, the second input end (end B) of the logic circuit 3012 is used to receive the first trigger signal, and the output end of the logic circuit 3012 is used to output the second trigger signal. The delay circuit 3011 is used to delay the first trigger signal so that the first trigger signal entering the first input end of the logic circuit 3012 lags behind the first trigger signal entering the second input end of the logic circuit 3012. The logic circuit 3012 is used to output the second trigger signal according to the first trigger signal at the first input end and the second trigger signal at the second input end.

[0074] In some embodiments, the logic circuit 3012 is an AND gate circuit, that is, when the reverse of the first trigger signal at the first input terminal of the logic circuit 3012 and the first trigger signal at the second output terminal of the logic circuit 3012 are both high levels, the second trigger signal output at the output terminal of the logic circuit 3012 is high level; when the reverse of the first trigger signal at the first input terminal of the logic circuit 3012 and the first trigger signal at the second output terminal of the logic circuit 3012 are not both high levels, the second trigger signal output at the output terminal of the logic circuit 3012 is low level.

[0075] When the first trigger signal is at a low level, the first trigger signal at the second input end of the logic circuit is at a low level, the first trigger signal at the first input end of the logic circuit is at a low level, the reverse of the first trigger signal at the first input end of the logic circuit is still at a high level, and the second trigger signal output at the output end of the logic circuit is at a low level. Since the delay circuit is used to delay the first trigger signal entering the first input end of the logic circuit, when the first trigger signal is switched from a low level to a high level, the first trigger signal at the second input end of the logic circuit is instantly switched from a low level to a high level, the first trigger signal at the first input end of the logic circuit is still at a low level, the reverse of the first trigger signal at the first input end of the logic circuit is at a high level, and the second trigger signal output at the output end of the logic circuit is switched from a low level to a high level. When the first trigger signal is switched from a low level to a high level and then remains at a high level, the first trigger signal at the second input end of the logic circuit is at a high level, the first trigger signal at the first input end of the logic circuit is at a high level, the reverse of the first trigger signal at the first input end of the logic circuit is at a low level, and the second trigger signal output at the output end of the logic circuit is switched from a high level to a low level.

[0076] When the first trigger signal switches from a low level to a high level, the second trigger signal also switches from a low level to a high level. When the first trigger signal switches from a low level to a high level and then remains at a high level, the second trigger signal switches from a high level to a low level. Since the delay time of the delay circuit is much smaller than the signal width of the burst optical signal, the signal width of the second trigger signal is much smaller than the signal width of the burst optical signal, and the falling edge of the second trigger signal will not fall outside the burst optical signal. Among them, the signal width of the burst optical signal refers to the time difference between the moment when the burst optical signal cannot be received and the moment when the burst optical signal is just received.

[0077] In some embodiments, the delay circuit and the logic circuit cooperate with each other, and the delay time of the delay circuit is less than the signal width of the burst optical signal, so that the MCU adjusts the first trigger signal to the second trigger signal, and the falling edge of the second trigger signal falls within the burst optical signal, thereby making the sampling capacitor controlled by the second trigger signal fully charged, thereby avoiding deviations in the received optical power obtained by sampling the optical module.

[0078] Figure 8 FIG. 1 is a structural diagram of a first delay circuit provided according to some embodiments. Figure 8 As shown, in some embodiments, the delay circuit 3011 includes a delay resistor 311a and a delay capacitor 311b, the delay resistor 311a is used to receive the first trigger signal, one end of the delay capacitor 311b is connected to the delay resistor 311a, and the other end of the delay capacitor 311b is connected to the first input end of the logic circuit 3012.

[0079] Since the delay circuit 3011 is equivalent to the input voltage charging the delay capacitor 311b through the delay resistor 311a, the corresponding relationship between the output voltage and the charging time is as follows: t = -R*C*ln((EV) / E), where t is the charging time, R is the resistance value, C is the capacitance value, E is the input voltage, V is the voltage across the capacitor, and EV is the output voltage.

[0080] Combining the corresponding relationship between the output voltage and the charging time, it can be known that the charging time t is proportional to R*C, that is, the larger the R*C is, the longer the charging time t is. Among them, the delay time of the delay circuit 3011 refers to the charging time of the delay circuit 3011.

[0081] Since the delay time of the delay circuit is shorter than the signal width of the burst optical signal, the charging time of the delay circuit 3011 is shorter than the signal width of the burst optical signal.

[0082] Fig. 9 FIG. 1 is a structural diagram of a second delay circuit provided according to some embodiments. Fig. 9As shown, in some embodiments, the delay circuit 3011 only includes a first logic unit 311c, which only serves as a load. The input end of the first logic unit 311c is used to receive a first trigger signal, and the output end of the first logic unit 311c is connected to the first input end of the logic circuit 3012.

[0083] When the delay circuit 3011 includes only the first logic unit 311c, the delay time of the delay circuit 3011 is short, and the signal width of the second trigger signal output by the logic circuit 3012 is narrow. In order to slightly extend the delay time of the delay circuit 3011, in some embodiments, the delay circuit 3011 includes a first logic unit 311c and a second logic unit 311d. The input end of the first logic unit 311c is used to receive the first trigger signal. The input end of the second logic unit 311d is connected to the output end of the first logic unit, and the output end of the second logic unit 311d is connected to the first input end of the logic circuit 3012.

[0084] The delay circuit 3011 including the first logic unit 311c and the second logic unit 311d has a longer delay time than the delay circuit 3011 including only the first logic unit 311c, and the signal width of the second trigger signal output by the logic circuit 3012 is slightly wider.

[0085] Fig.10 FIG. 1 is a structural diagram of a third delay circuit provided according to some embodiments. Fig.10 As shown, in some embodiments, the delay circuit 3011 only includes a trigger 311f, the first input terminal of the trigger 311f is connected to the clock signal generator (that is, the first input terminal of the trigger 311f is used to receive the clock signal), the second input terminal of the trigger 311f is used to receive the first trigger signal, and the output terminal is connected to the first input terminal of the logic circuit 3012.

[0086] In some embodiments, the trigger 311f is a D trigger. When the trigger 311f receives a clock signal (i.e., the clock signal is at a high level), the trigger 311f is triggered to monitor whether the first trigger signal received at the second input end of the trigger 311f is at a high level or a low level. When the first trigger signal received at the second input end of the trigger 311f is at a high level, the output end of the trigger 311f outputs a high level. When the first trigger signal received at the second input end of the trigger 311f is at a low level, the output end of the trigger 311f outputs a low level.

[0087] When the trigger 311f does not receive the clock signal (i.e., the clock signal is at a low level), the trigger 311f is not triggered, and the first trigger signal received by the second input terminal of the trigger 311f is not monitored, and the output terminal of the trigger 311f maintains the output of the output terminal of the trigger 311f in the previous round. When the first trigger signal received by the second input terminal of the trigger 311f is at a low level, the output terminal of the trigger 311f outputs a low level. When the first trigger signal received by the second input terminal of the trigger 311f switches from a low level to a high level, the output terminal of the trigger 311f outputs a low level. When the first trigger signal received by the second input terminal of the trigger 311f switches from a low level to a high level and remains at a high level, the output terminal of the trigger 311f outputs a high level.

[0088] The time when the trigger 311f receives the clock signal affects the signal width of the second trigger signal, so that the signal width of the second trigger signal is not fixed. For example, the period of the clock signal is 600ns, and the signal width of the second trigger signal is 50ns-600ns.

[0089] The first trigger signal at the second input terminal of the trigger 311f is switched from a low level to a high level at time T1, the trigger 311f does not receive the clock signal at time T1, the first trigger signal at the output terminal of the trigger 311f is at a low level, and the second trigger signal outputted from the output terminal of the logic circuit 3012 is switched from a high level to a high level. When the trigger 311f receives the clock signal at time T1+ΔT, the trigger 311f detects that the first trigger signal at the second input terminal of the trigger 311f is at a high level, the first trigger signal at the output terminal of the trigger 311f is at a high level, and the second trigger signal outputted from the output terminal of the logic circuit 3012 is switched from a high level to a low level.

[0090] The signal width of the second trigger signal outputted from the output terminal of the logic circuit 3012 refers to the time difference ΔT between the moment T1+ΔT when the second trigger signal changes from high level to low level and the moment T1 when the second trigger signal changes from low level to high level.

[0091] The smaller ΔT is, the smaller the signal width of the second trigger signal is; the larger ΔT is, the larger the signal width of the second trigger signal is. ΔT is related to the period of the clock signal, that is, ΔT≤the period of the clock signal.

[0092] In some embodiments, the clock signal is a system clock signal, and the clock signal generator for generating the clock signal is a clock module in the MCU.

[0093] In some embodiments, the clock signal is a clock signal of a timer, and the clock signal generator for generating the clock signal is a timer outside the MCU.

[0094] like Fig.10 As shown, in some embodiments, the delay circuit 3011 includes a logic unit 311e and a trigger 311f, the input end of the logic unit 311e is used to receive the first trigger signal, the first input end of the trigger 311f is connected to the clock signal generator, the second input end of the trigger 311f is connected to the output end of the logic unit 311e, and the output end is connected to the first input end of the logic circuit 3012. The logic unit 311e can be the first logic unit 311c, the second logic unit 311d, or the first logic unit 311c and the second logic unit 311d.

[0095] Fig.11 FIG. 4 is a structural diagram of a fourth delay circuit provided according to some embodiments. Fig.11 As shown, in some embodiments, the delay circuit 3011 includes a delay resistor 311a, a delay capacitor 311b and a trigger 311f, the delay resistor 311a is used to receive a first trigger signal, one end of the delay capacitor 311b is connected to the delay resistor 311a, the other end of the delay capacitor 311b is connected to the second input end of the trigger 311f, and the first input end of the trigger 311f is connected to the clock signal generator.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An optical module, characterized in that: include: The light receiving component comprises: A photodetector, configured to receive a burst optical signal and convert the burst optical signal into a first current signal; A circuit board, connected to the light receiving component, is provided with: A mirror current source, a first output end of which is connected to the photodetector, and is used to mirror the first current signal into a second current signal; A sampling circuit, connected to the second output terminal of the mirror current source, and used for collecting the second current signal according to a second trigger signal; An MCU is connected to the sampling circuit and is used to adjust the first trigger signal to the second trigger signal so that the falling edge of the second trigger signal falls within the burst optical signal; wherein the MCU includes a delay circuit and a logic circuit, the input end of the delay circuit is used to receive the first trigger signal, the output end of the delay circuit is connected to the first input end of the logic circuit, the second input end of the logic circuit is used to receive the first trigger signal, the output end of the logic circuit is used to output the second trigger signal, the delay circuit is used to delay the first trigger signal, and the logic circuit is used to output the second trigger signal according to the first trigger signal at the first input end and the first trigger signal at the second input end, wherein the delay time of the delay circuit is less than the signal width of the burst optical signal.

2. The optical module according to claim 1, characterized in that: The logic circuit is configured as follows: when the reverse of the first trigger signal at the first input terminal and the first trigger signal at the second input terminal are both high levels, the output second trigger signal is high level; when the reverse of the first trigger signal at the first input terminal and the first trigger signal at the second input terminal are not both high levels, the output second trigger signal is low level.

3. The optical module according to claim 1, characterized in that: The delay circuit comprises: A delay resistor, used for receiving the first trigger signal; A delay capacitor has one end connected to the delay resistor and the other end connected to the first input end of the logic circuit.

4. The optical module according to claim 1, characterized in that: The delay circuit comprises: A trigger, wherein the first input terminal is used to receive a clock signal, the second input terminal is used to receive the first trigger signal, and the output terminal is connected to the first input terminal of the logic circuit; wherein when the clock signal is at a high level, the trigger is triggered; and when the clock signal is at a low level, the trigger is not triggered.

5. The optical module according to claim 1, characterized in that: The delay circuit comprises: A first logic unit, an input end of which is used to receive the first trigger signal; The second logic unit has an input end connected to the output end of the first logic unit, and an output end connected to the first input end of the logic circuit.

6. The optical module according to claim 1, characterized in that: The delay circuit comprises: A logic unit, an input end of which is used to receive the first trigger signal; A trigger, wherein the first input terminal is used to receive a clock signal, the second input terminal is connected to the output terminal of the logic unit, and the output terminal is connected to the first input terminal of the logic circuit; wherein when the clock signal is at a high level, the trigger is triggered; and when the clock signal is at a low level, the trigger is not triggered.

7. The optical module according to claim 1, characterized in that: The sampling circuit comprises: Sampling capacitor; A sampling switch, wherein a control end is connected to the output end of the logic circuit, a fixed end is connected to the sampling capacitor, a first active end is connected to the second output end of the mirror current source, and a second active end is connected to the MCU, and is used to turn on or interrupt the connection between the second output end of the mirror current source and the sampling capacitor according to a received trigger signal, so as to turn on or interrupt the charging of the sampling capacitor by the second current signal.

8. The optical module according to claim 1, characterized in that: Also included is a holding circuit; The holding circuit is connected to the second active end of the sampling switch and is also connected to the MCU, and is used to collect the voltage across the sampling capacitor when charging of the sampling capacitor is interrupted, and to keep the collected voltage for a preset time.

9. The optical module according to claim 1, characterized in that: Also includes: a transimpedance amplifier, connected to the photodetector, and configured to convert the first current signal into a voltage signal and amplify the voltage signal; The limiting amplifier is located on the circuit board and connected to the transimpedance amplifier.

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