Display panel and display device

Abstract

The invention discloses a display panel and a display device. A pixel circuit of the display panel comprises a driving transistor and a threshold compensation transistor. The signal lines comprise a plurality of data signal lines and data connecting lines, and the data signal lines located in the second display area are electrically connected with the fan-out wires through the data connecting lines; the pixel circuit further comprises a connecting part; the connecting part is connected with the active layer of the driving transistor and the active layer of the threshold compensation transistor; the data connecting line comprises a first data branch, and the minimum distance between the orthographic projection of the first data branch on the plane where the substrate is located and the orthographic projection of the connecting part on the plane where the substrate is located in the second direction is smaller than a preset distance; the display panel further comprises a functional structure part, and the functional structure part and the first data branch are overlapped in the thickness direction of the display panel. According to the technical scheme, the coupling capacitance between the first data branch and the connecting part can be reduced, the influence caused by signal jump in the first data branch is weakened, and the display uniformity is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, the border of display panels is required to be narrower and narrower. In order to reduce the bottom border of the display panel, a technology of laying out part of the fan-out line in the display area (Fanout in AA, FIAA) has emerged. However, based on the existing FIAA fan-out line layout, the display area has a display unevenness (Mura) phenomenon. Summary of the invention

[0003] In view of this, the present invention provides a display panel and a display device to propose a better wiring method to improve the display uniformity of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a plurality of pixel circuits and a plurality of signal lines;

[0005] The pixel circuit includes a driving transistor and a threshold compensation transistor; the signal line includes a plurality of data signal lines, and the plurality of data signal lines extend along a first direction and are arranged along a second direction;

[0006] The display panel further includes a display area and a non-display area at least partially surrounding the display area, the display area includes a first display area and a second display area, the second display area is located at least on one side of the first display area along the second direction; the first display area and the second display area both include a plurality of data signal lines; the non-display area includes a fan-out area located on one side of the display area along the first direction, the fan-out area includes a plurality of fan-out routing lines; the signal line also includes a data connection line, the data signal line located in the second display area is electrically connected to the fan-out routing line through the data connection line;

[0007] The pixel circuit further includes a connection portion, the connection portion connecting the active layer of the driving transistor and the active layer of the threshold compensation transistor; the data connection line includes a first data portion, the first data portion extending along a first direction; the display panel further includes a substrate, and a minimum distance in a second direction between an orthographic projection of the first data portion on a plane where the substrate is located and an orthographic projection of the connection portion on a plane where the substrate is located is less than a preset distance;

[0008] The display panel also includes a functional structure portion, which is insulated from the first data portion; along the thickness direction of the display panel, the functional structure portion overlaps with the first data portion.

[0009] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel according to the first aspect of the present invention.

[0010] The display panel provided by the embodiment of the present invention, by arranging the functional structure part and the first data division to overlap along the thickness direction of the display panel, forms a coupling capacitor structure between the overlapping functional structure part and the first data division, and the coupling capacitor structure can disperse or shield at least part of the signal in the first data division, reduce the coupling capacitance between the first data division and the connecting part, thereby reducing or eliminating the influence of the first data division transmission signal on the node potential in the pixel circuit, weakening the influence of signal jump, and improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the structure of a display panel in a related technology provided by an embodiment of the present invention;

[0012] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0013] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0014] Figure 4 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 5 A schematic diagram of a film layer structure of a pixel circuit provided by an embodiment of the present invention;

[0016] Figure 6 for Figure 5 Schematic diagram of the cross-sectional structure along the A-A' direction;

[0017] Figure 7 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 8 A schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present invention;

[0019] Fig. 9 for Figure 7 A schematic diagram of a portion of the structure of the display panel is shown;

[0020] Fig.10 for Figure 7 A schematic diagram of another part of the structure of the display panel is shown;

[0021] Fig.11 for Figure 7 A schematic diagram of another part of the structure of the display panel is shown;

[0022] Fig.12 for Figure 7 A schematic diagram of another part of the structure of the display panel is shown;

[0023] Fig.13 for Figure 7 A schematic diagram of another part of the structure of the display panel is shown;

[0024] Fig.14 A schematic diagram of the circuit structure of another pixel circuit provided by an embodiment of the present invention;

[0025] Fig.15 A schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present invention;

[0026] Fig.16 for Figure 7 Another schematic diagram of the structure of the first semiconductor layer in the display panel shown;

[0027] Fig.17 for Figure 7 Another schematic diagram of the structure of the first metal layer in the display panel is shown;

[0028] Fig.18 for Figure 7 Another schematic diagram of the structure of the second metal layer in the display panel is shown;

[0029] Fig.19 for Figure 7 Another schematic diagram of the structure of the fifth metal layer in the display panel is shown;

[0030] Fig. 20 for Figure 7 Another schematic diagram of the structure of the sixth metal layer in the display panel is shown;

[0031] Fig.21 A schematic diagram of a circuit structure of another pixel circuit provided by an embodiment of the present invention;

[0032] Fig. 22 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0033] Fig.23 A schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present invention;

[0034] Fig.24 for Fig. 22 A schematic diagram of a portion of the structure of the display panel is shown;

[0035] Fig.25 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0036] Fig.26 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0037] Fig. 27 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0038] Fig.28 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0039] Fig.29 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0040] Fig.30 for Fig. 22 A schematic diagram of another part of the structure of the display panel is shown;

[0041] Fig.31 A schematic diagram of the structure of a first metal layer and a second metal layer provided in an embodiment of the present invention;

[0042] Fig.32 A schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present invention;

[0043] Fig.33 for Fig.32 A schematic diagram of the structure of the film layer where the second functional structure part is located;

[0044] Fig.34 for Fig.32 Schematic diagram of the enlarged structure;

[0045] Fig.35 A schematic diagram of an electric field provided by an embodiment of the present invention;

[0046] Fig.36 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0047] Fig.37 A schematic diagram of the structure of an anode layer in a display panel provided by an embodiment of the present invention;

[0048] Fig.38 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0050] It should be noted that the terms “having”, “including”, “comprising”, etc. described in the present application are all open-ended meanings, that is, when describing a module as “having”, “including” or “comprising” a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. In addition, ordinal numbers such as “first”, “second” and “third” in the present application are not intended to limit a specific order, but are only intended to distinguish between the various parts. In the present application, when describing that layer A and layer B are “set in the same layer”, it means that layer A and layer B are made of the same material and process.

[0051] Figure 1 A schematic diagram of a display panel structure in a related art provided by an embodiment of the present invention, referring to Figure 1 In the related art, along the thickness direction of the display panel, the connection line 20' located in the display area may overlap with the node connected to the driving transistor T3 in the pixel driving circuit, such as the N3 node shown in the figure, thereby causing parasitic capacitance between the connection line and the N3 node. When the signal transmitted in the connection line 20' jumps, it will also cause the change of the potential of the N3 node, and finally cause bright and dark stripes to appear in the display area, affecting the display uniformity.

[0052] Based on the above-mentioned defects of the related art, the present application provides a display panel, including a plurality of pixel circuits and a plurality of signal lines;

[0053] The pixel circuit includes a driving transistor and a threshold compensation transistor; the signal line includes a plurality of data signal lines, and the plurality of data signal lines extend along a first direction and are arranged along a second direction;

[0054] The display panel further includes a display area and a non-display area at least partially surrounding the display area, the display area includes a first display area and a second display area, the second display area is located at least on one side of the first display area along the second direction; the first display area and the second display area both include a plurality of data signal lines; the non-display area includes a fan-out area located on one side of the display area along the first direction, the fan-out area includes a plurality of fan-out routing lines; the signal line also includes a data connection line, the data signal line located in the second display area is electrically connected to the fan-out routing line through the data connection line;

[0055] The pixel circuit further includes a connection portion, the connection portion connecting the active layer of the driving transistor and the active layer of the threshold compensation transistor; the data connection line includes a first data portion, the first data portion extending along a first direction; the display panel further includes a substrate, and a minimum distance in a second direction between an orthographic projection of the first data portion on a plane where the substrate is located and an orthographic projection of the connection portion on a plane where the substrate is located is less than a preset distance;

[0056] The display panel also includes a functional structure portion, which is insulated from the first data portion; along the thickness direction of the display panel, the functional structure portion overlaps with the first data portion.

[0057] Through the above technical solution, a coupling capacitor structure is formed between the overlapping functional structure part and the first data division. The coupling capacitor structure can disperse or shield at least part of the signal in the first data division, reduce the coupling capacitance between the first data division and the connecting part, thereby reducing or eliminating the influence of the first data division transmission signal on the node potential in the pixel circuit, weakening the influence of signal jumps, and improving display uniformity.

[0058] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 4 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention is provided. Figure 5 A schematic diagram of a film structure of a pixel circuit provided by an embodiment of the present invention can be referred to Figure 2 to Figure 5In an embodiment of the present invention, the display panel includes a plurality of pixel circuits 10 and a plurality of signal lines 20; the pixel circuit 10 includes a driving transistor T3 and a threshold compensation transistor T4; the signal line 20 includes a plurality of data signal lines Data, the plurality of data signal lines Data extend along a first direction X and are arranged along a second direction Y; the display panel also includes a display area AA and a non-display area NA at least partially surrounding the display area AA, the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 is located at least on one side of the first display area AA1 along the second direction Y; the first display area AA1 and the second display area AA2 both include a plurality of data signal lines Data; the non-display area NA includes a fan-out area NA1 located on one side of the display area AA along the first direction X, the fan-out area NA1 includes a plurality of fan-out wirings 30; the signal line 20 also includes a data The data signal line Data located in the second display area AA2 is electrically connected to the fan-out wiring 30 through the data connection line 201; the pixel circuit 10 also includes a connection part 101, and the connection part 101 connects the active layer of the driving transistor T3 and the active layer of the threshold compensation transistor T4; the data connection line 201 includes a first data division 2011, and the first data division 2011 extends along the first direction X; the display panel also includes a substrate 40, and the minimum distance between the orthographic projection of the first data division 2011 on the plane where the substrate 40 is located and the orthographic projection of the connection part 101 on the plane where the substrate 40 is located in the second direction Y is less than a preset distance; the display panel also includes a functional structure part 50, and the functional structure part 50 is insulated from the first data division 2011; along the thickness direction of the display panel, the functional structure part 50 overlaps with the first data division 2011.

[0060] like Figure 2 to Figure 5 As shown, the pixel circuit 10 is electrically connected to the light emitting element D in the display panel to drive the light emitting element D to emit light. The signal line 20 is configured to provide a voltage signal and / or a current signal to the pixel circuit 10, thereby realizing the driving of the light emitting element D by the pixel circuit 10. In this embodiment, the signal line 20 at least includes a data signal line Data, and the data signal line Data is electrically connected to the pixel circuit 10 to provide a data signal to the pixel circuit 10. The data signal line Data extends along a first direction X and is arranged along a second direction Y. The first direction X may be a column direction, and the second direction Y may be a row direction. One data signal line Data may be connected to a plurality of pixel circuits 10 arranged along the first direction X, so that one data signal line Data is used to provide a data signal to a plurality of pixel circuits 10 in the same column.

[0061] Continue to refer Figure 2 to Figure 5The display panel includes a display area AA and a non-display area NA. The display area AA includes a light-emitting element D and a data signal line Data connected to the light-emitting element D, etc., for realizing the display function of the display panel. The non-display area NA includes a display controller connected to the data signal line Data, such as a driver chip (not specifically shown in the figure), and the display controller provides a data signal to the data signal line Data, thereby driving the display panel to realize the display function. The non-display area NA surrounds at least part of the display area AA. The embodiment of the present invention does not specifically limit the specific positions of the display area AA and the non-display area NA.

[0062] Furthermore, in this embodiment, the display area AA may include a first display area AA1 and a second display area AA2. Figure 3 In the example, the second display area AA2 is located on both sides of the first display area AA1 along the second direction Y, but it is not limited thereto. Figure 3 In the direction shown in FIG. 1 , the second display area AA2 is located between the first display area AA1 and the non-display areas NA on the left and right sides. Along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The non-display area NA includes a fan-out area NA1, which is located on one side of the display area AA along the first direction X. Figure 3 Taking the lower side as an example, the fan-out area NA1 may be provided with a plurality of fan-out wirings 30 , and the fan-out wirings 30 are electrically connected to the data signal lines Data, thereby connecting the data signal lines Data to the display controller to ensure stable transmission of the data signals.

[0063] Continue to refer Figure 2 to Figure 5 , a plurality of data signal lines Data are arranged in the first display area AA1 and the second display area AA2, and the data signal lines Data in the first display area AA1 can be directly electrically connected to the fan-out wiring 30. The data signal lines Data in the second display area AA2 are electrically connected to the fan-out wiring 30 through the data connection lines 201 in the display area AA. Specifically, the data connection lines 201 may include a first data division 2011 and a second data division 2012, the first data division 2011 extends along a first direction X, and the second data division 2012 extends along a second direction Y, the first data division 2011 may be arranged in the first display area AA1, a first end of the first data division 2011 is connected to the fan-out wiring 30, a second end of the first data division 2011 is connected to a first end of the second data division 2012, and a second end of the second data division 2012 extends to the second display area AA2 and is electrically connected to the data signal lines Data in the second display area AA2.

[0064] So, along Figure 3As shown in the orientation, the fan-out wiring 30 can be concentrated in the fan-out area NA1 below the first display area AA1, thereby reducing the space occupied by the fan-out wiring 30 and reducing the setting area of ​​the fan-out area NA1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display panel display area AA, increasing the display effect of the display panel, and realizing a narrow frame.

[0065] Further, such as Figure 2 to Figure 5 As shown, the pixel circuit 10 may include elements such as transistors and capacitors, wherein the transistors at least include a driving transistor T3 and a threshold compensation transistor T4, the driving transistor T3 generates a driving current to drive the light-emitting element D to emit light, and the threshold compensation transistor T4 is used to compensate for the threshold voltage of the driving transistor T3. The pixel circuit 10 has various configuration modes. Figure 4 The pixel circuit 10 shown is a "7T1C" pixel circuit 10, which includes 7 transistors and 1 capacitor, but is not actually limited to this. The "7T1C" pixel circuit 10 is used as an example for explanation below. Based on the setting method of this pixel circuit 10, technicians in this field can make adaptive adjustments according to needs.

[0066] Specifically, if Figure 4As shown, in addition to the driving transistor T3 and the threshold compensation transistor T4, the pixel circuit 10 may also include an initialization transistor T5, a data writing transistor T2, an anode reset transistor T7, a first light emission control transistor T1, a second light emission control transistor T6 and a storage capacitor Cst. The first electrode of the initialization transistor T5 is connected to the first initialization signal line Vref1, the second electrode of the initialization transistor T5 is connected to the gate of the driving transistor T3 and the first electrode of the storage capacitor Cst, the gate of the initialization transistor T5 is connected to the first scanning signal line S1, and the connection node between the initialization transistor T5 and the driving transistor T3 is the first node N1. The first electrode of the data writing transistor T2 is connected to the data signal line Data; the second electrode of the data writing transistor T2 is connected to the first electrode of the driving transistor T3, the gate of the data writing transistor T2 is connected to the third scanning signal line SP, and the connection node between the data writing transistor T2 and the driving transistor T3 is the second node N2. The first electrode of the threshold compensation transistor T4 is connected to the second electrode of the driving transistor T3, the second electrode of the threshold compensation transistor T4 is connected to the first node N1, the gate of the threshold compensation transistor T4 can be connected to the second scanning signal line S2, and the connection node between the threshold compensation transistor T4 and the driving transistor T3 is the third node N3. The first electrode of the first light-emitting control transistor T1 is connected to the first power supply voltage signal line PVDD, and the second electrode of the first light-emitting control transistor T1 is connected to the first electrode of the driving transistor T3; the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element D, and the gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM. The first electrode of the anode reset transistor T7 is connected to the second initialization signal line Vref2, the second electrode of the anode reset transistor T7 is connected to the anode of the light-emitting element D, and the gate of the anode reset transistor T7 can be connected to the third scanning signal line SP. The second electrode plate of the storage capacitor Cst is connected to the first electrode of the first light-emitting control transistor T1. The wirings connected to the above transistors are all signal lines 20.

[0067] Figure 4The working sequence of the pixel circuit 10 shown is as follows: in the initialization period, the initialization transistor T5 is turned on under the control of the first scanning signal, and the first initialization signal is written into the gate of the driving transistor T3, that is, the first node N1, to initialize the gate of the driving transistor T3. In the data writing stage, the data writing transistor T2 is turned on under the control of the second scanning signal, the threshold compensation transistor T4 is turned on under the control of the third scanning signal, the driving transistor T3 is turned on, and the data signal is applied to the first node N1 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4, and the potential of the first node N1 gradually increases. At the same time, in the data writing stage, the anode reset transistor T7 is turned on, and the second initialization signal is written into the anode of the light-emitting element D to initialize the anode of the light-emitting element D. In the light-emitting stage, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, and the first power supply voltage signal is transmitted to the driving transistor T3, so that the driving transistor T3 generates a driving current, and the driving current is transmitted to the anode of the light-emitting element D, driving the light-emitting element D to emit light.

[0068] In the pixel circuit 10 , transistors are generally connected via active layers. The portion where the active layer of the driving transistor T3 and the active layer of the threshold compensation transistor T4 are connected can be defined as a connecting portion 101 , which corresponds to the third node N3 . Figure 5 FIG. 1 shows some of the film layers in the pixel circuit, referring to FIG. Figure 5 , the minimum distance between the orthographic projection of the first data portion 2011 on the substrate 40 and the orthographic projection of the connecting portion 101 on the substrate 40 in the second direction Y can represent the minimum spacing between the two in the second direction Y. Based on the current wiring arrangement, the minimum spacing between the orthographic projections of the first data portion 2011 and the connecting portion 101 on the substrate 40 in the second direction Y is generally very small or even 0, and the figure exemplarily shows that the first data portion 2011 and the connecting portion 101 overlap in the thickness direction of the display panel.

[0069] For further information, please refer to Figure 5In order to avoid the parasitic capacitance between the first data division 2011 and the connection part 101, which affects the potential of the third node N3, the embodiment of the present invention proposes that a functional structure part 50 can be set in the display panel, and the film layer where the functional structure part 50 is located is different from the film layer where the first data division 2011 and the film layer where the connection part 101 are located, and the functional structure part 50 overlaps with the first data division 2011 in the thickness direction of the display panel. Under this arrangement, a coupling capacitor structure can be formed between the overlapping functional structure part 50 and the first data division 2011, and the coupling capacitor structure can disperse or shield at least part of the signal in the first data division 2011, thereby reducing the coupling capacitance between the first data division 2011 and the connection part 101, thereby reducing or eliminating the influence of the signal transmitted by the first data division 2011 on the potential of the third node N3, weakening the influence of signal jump, and improving display uniformity.

[0070] The embodiment of the present invention does not limit the film layer where the functional structure part 50 is located, and those skilled in the art can set it according to actual conditions.

[0071] In an embodiment of the present invention, by adding a functional structure portion in the display panel and overlapping the functional structure portion with the first data portion in the thickness direction of the display panel, the coupling capacitance between the first data portion and the connecting portion can be reduced, the influence of the signal transmitted by the first data portion on the potential of the third node can be reduced or eliminated, the influence of signal jumps can be weakened, the display uniformity can be improved, and the display panel can have a better display effect.

[0072] Optionally, in a possible embodiment, the functional structure portion is electrically connected to the fixed potential signal line.

[0073] By connecting the functional structure part to the fixed potential signal line, a stable voltage is provided in the functional structure part, thereby ensuring the stability of the coupling capacitance between the functional structure part and the first data section, and also preventing the signal in the functional structure part from affecting other signal lines.

[0074] The fixed potential signal line may be a signal line for transmitting a fixed voltage already in the display panel, such as a positive power supply voltage signal line for transmitting a positive power supply voltage signal, an initialization signal line for transmitting an initialization signal, or a negative power supply signal line connected to the cathode of a light-emitting element, but is not limited thereto. In this way, there is no need to set up an additional fixed potential signal line, which can reduce the difficulty of wiring.

[0075] Optional, Figure 6 for Figure 5 The cross-sectional structure diagram along the A-A' direction can be combined with reference Figure 5 and Figure 6The functional structure part 50 may include a first functional structure part 501, and the film layer where the first functional structure part 501 is located is located between the film layer where the connecting part 101 is located and the film layer where the first data division 2011 is located; the orthographic projection of the first data division 2011 on the plane where the substrate 40 is located and the orthographic projection of the connecting part 101 on the plane where the substrate 40 is located have an overlapping area B; the orthographic projection of the first functional structure part 501 on the plane where the substrate 40 is located covers at least part of the overlapping area B.

[0076] Specifically, if Figure 5 and Figure 6 As shown, in this embodiment, the first data division 2011 and the connecting portion 101 overlap along the thickness direction Z of the display panel. As an optional scheme, a first functional structure portion 501 can be set between the film layer where the connecting portion 101 is located and the film layer where the first data division 2011 is located, and along the thickness direction Z of the display panel, the first functional structure portion 501 covers at least a partial overlapping area B of the first data division 2011 and the connecting portion 101. It can also be understood that the first functional structure portion 501 is inserted into one or more layers between the overlapping first data division 2011 and the connecting portion 101.

[0077] In this configuration, the first functional structure portion 501 can shield the coupling between the first data division 2011 and the connecting portion 101 to a large extent, thereby eliminating or reducing the influence of the transmission signal of the first data division 2011 on the potential of the third node N3 to a large extent.

[0078] Exemplarily, in some embodiments, the orthographic projection of the first functional structure portion 501 on the substrate 40 can be set to completely cover the overlapping area B between the first data division 2011 and the connecting portion 101, thereby avoiding the generation of coupling capacitance between the first data division 2011 and the connecting portion 101 and eliminating the influence of the jump signal on the potential of the third node N3.

[0079] Figure 7 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, Figure 8 A schematic diagram of a film layer structure of another pixel circuit provided in an embodiment of the present invention, Figure 8 The film structure shown can correspond to Figure 4 The pixel circuit provided, Figure 8 The cross-sectional film structure of the pixel circuit shown in Figure 7 Shown in. Fig. 9 for Figure 7 The schematic diagram of a part of the structure of the display panel is shown. Fig.10 for Figure 7 The schematic diagram of another part of the structure of the display panel is shown. Fig.11 for Figure 7 The schematic diagram of another part of the structure of the display panel is shown. Fig.12 for Figure 7 The schematic diagram of another part of the structure of the display panel is shown. Fig.13 for Figure 7 The schematic diagram of another part of the structure of the display panel is shown. Figure 7 to Figure 13 In some possible embodiments, the pixel circuit further includes at least one first type transistor, the first type transistor includes a driving transistor T3 and a threshold compensation transistor T4; the pixel circuit further includes a storage capacitor Cst, the storage capacitor Cst includes a first electrode C1 and a second electrode C2 arranged opposite to each other; the display panel further includes a first semiconductor layer POLY, a first metal layer M1 and a second metal layer MC arranged in a stacked manner, the second metal layer MC is located on the side of the first metal layer M1 away from the substrate 40; the active layer of the driving transistor T3, the active layer of the threshold compensation transistor T4 and the connecting portion 101 are all located in the first semiconductor layer POLY; the first electrode C1 is located in the first metal layer M1; the second electrode C2 is located in the second metal layer MC; the first data division 2011 is located on the side of the second metal layer MC away from the substrate 40; the first functional structure portion 501 is located in the first metal layer M1 and / or the second metal layer MC.

[0080] The first type transistor may be a low temperature polysilicon transistor, and the active layer of the first type transistor is a silicon semiconductor layer, forming an LTPS display panel. Figure 6 to Figure 12 As shown, the film layer structure of the pixel circuit from the bottom to the light-emitting side of the display panel can be a substrate 40, a buffer layer 601, a first semiconductor layer POLY, a first insulating layer 602, a first metal layer M1, an interlayer insulating layer 603, a second metal layer MC, a second insulating layer 604, a fifth metal layer M2, a third insulating layer 605, a sixth metal layer M3, a planarization layer 606 and an anode layer RE, and the first semiconductor layer POLY is the above-mentioned silicon semiconductor layer. For the film layer structure of a specific pixel circuit, adaptive adjustments can be made according to actual needs, such as adding or removing some film layers, and any of the above film layers can include at least one sublayer, which is not specifically limited in the embodiment of the present invention.

[0081] Figure 8 FIG. 1 shows a partial film stack diagram in a pixel circuit, including a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC and a fifth metal layer M2. The schematic diagrams of other film layers can be referred to in FIG. Figures 9 to 13 The single film structure diagram in . Among them, Fig. 9 The figure shows the structure diagram of the first semiconductor layer POLY. Fig.10 FIG. 1 is a schematic diagram showing the structure of the first metal layer M1. Fig.11 It is a schematic diagram of the structure of the second metal layer MC. Fig.12 FIG. 1 is a schematic diagram showing the structure of the fifth metal layer M2. Fig.13FIG. 1 is a schematic diagram of the structure of the sixth metal layer M3. In this embodiment, each transistor in the pixel circuit can be a first type transistor. Taking the driving transistor T3 and the threshold compensation transistor T4 as examples, the active layers of the driving transistor T3 and the threshold compensation transistor T4 are both located in the first semiconductor layer POLY, and the connecting portion 101 of the active layers of the two is located in the first semiconductor layer POLY. Optionally, as an optional solution, Figure 7 to Figure 13As shown, the first electrode C1 of the storage capacitor Cst can be formed in the first metal layer M1, and the first metal layer M1 can also be used to form a portion of the scanning signal lines extending along the second direction Y, such as the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line SP and the light-emitting control signal line EM, etc.; the gate of the transistor is formed at the intersection of the above signal lines and the active layer of the transistor, that is, the gates of transistors such as the driving transistor T3 and the threshold compensation transistor T4 can be located in the first metal layer M1. The first initialization signal line Vref1 may include a first sub-initialization signal line Vref11 and a second sub-initialization signal line Vref12, the first sub-initialization signal line Vref11 extends along the second direction Y and is arranged in the first direction X, and the second sub-initialization signal line Vref12 extends along the first direction X and is arranged in the second direction Y. The first sub-initialization signal line Vref11 and the second sub-initialization signal line Vref12 are connected to form a grid-like routing; the second initialization signal line Vref2 may include a third sub-initialization signal line Vref21 and a fourth sub-initialization signal line Vref22, the third sub-initialization signal line Vref21 extends along the second direction Y and is arranged in the first direction X, and the fourth sub-initialization signal line Vref22 extends along the first direction X and is arranged in the second direction Y; the third sub-initialization signal line Vref21 and the fourth sub-initialization signal line Vref22 are connected to form a grid-like routing. The grid-like routing is conducive to reducing routing resistance and improving signal transmission effect. The second electrode C2 of the storage capacitor Cst can be formed in the second metal layer MC, and the second metal layer MC can also be used to form a portion of the signal line extending along the second direction Y and the shielding structure 60, for example, the first sub-initialization signal line Vref11 and / or the third sub-initialization signal line Vref21 are extended along the second direction Y, and the shielding structure 60 can be located between the signal line with signal jump and the first node, and the shielding structure 60 can be set to be electrically connected to the fixed potential, so as to prevent the jump of other signals from affecting the potential of the first node. The second data division 2012 can be formed in the fifth metal layer M2, and the fifth metal layer M2 can also be used to form a portion of the signal line extending along the first direction X and a portion of the connecting jump line 61, for example, the second sub-initialization signal line Vref12 and / or the fourth sub-initialization signal line Vref22 extending along the first direction X, and the connecting jump line 61 between the signal line and the transistor, etc. The first data division 2011 may be formed in the sixth metal layer M3. The sixth metal layer M3 may also be used to form a portion of signal lines extending along the first direction X, such as a first power voltage signal line PVDD and a data signal line Data extending along the first direction X.

[0082] In this embodiment, the first functional structure part 501 can be formed in at least one metal layer between the first semiconductor layer POLY and the sixth metal layer M3, for example, it can be set in the first metal layer M1 and / or the second metal layer MC. Figure 7 to Figure 13It can be seen that compared with the fifth metal layer M2 , the wiring in the first metal layer M1 and the second metal layer MC is simpler, which is beneficial to the layout of the first functional structure part 501 . Figure 6 to Figure 12 FIG. 5 exemplarily shows that the first functional structure part 501 is located in the second metal layer MC, but the present invention is not limited thereto.

[0083] Fig.14 A schematic diagram of a circuit structure of another pixel circuit provided by an embodiment of the present invention, Fig.14 The pixel circuit 10 may include a first light emission control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization transistor T5, a second light emission control transistor T6, an anode reset transistor T7, a bias transistor T8 and a storage capacitor Cst. The connection relationship between the above transistors is the same as that of the above Figure 4 The embodiments shown are basically the same and will not be described again here. In this embodiment, the gate of the threshold compensation transistor T4 and the gate of the data writing transistor T2 can be connected to the second scanning signal line S2, the gate of the initialization transistor T5 is connected to the first scanning signal line S1, and the gate of the anode reset transistor T7 and the gate of the bias transistor T8 are connected to the third scanning signal line SP. The first electrode of the newly added bias transistor T8 is connected to the bias signal line DVH, and the second electrode of the bias transistor T8 can be connected to the first electrode and / or the second electrode of the driving transistor T3; the gate of the bias transistor T8 and the gate of the anode reset transistor T7 can be connected to the fourth scanning signal line SP. Among them, the working process of the pixel circuit 10 is the same as Figure 4 The process of the corresponding pixel circuit 10 is similar and will not be described in detail here. In this embodiment, the bias transistor T8 is used to write a bias signal to the first electrode and / or the second electrode of the driving transistor T3 during the data writing phase to bias the second node N2 and / or the third node N3.

[0084] Furthermore, in some embodiments, each transistor in the “8T1C” pixel circuit may be a first type transistor, that is, a low temperature polysilicon transistor. Fig.15 A schematic diagram of a film layer structure of another pixel circuit provided in an embodiment of the present invention, Fig.15 The cross-sectional film structure of the pixel circuit shown is still referenced Figure 7 , Fig.15 and Figure 8 The difference between the illustrated embodiments lies in the layout design of the various film layers. Fig.16 for Figure 7 Another schematic diagram of the structure of the first semiconductor layer in the display panel is shown. Fig.17 for Figure 7 Another schematic diagram of the structure of the first metal layer in the display panel is shown. Fig.18 for Figure 7Another schematic diagram of the structure of the second metal layer in the display panel is shown. Fig.19 for Figure 7 Another schematic diagram of the structure of the fifth metal layer in the display panel is shown. Fig. 20 for Figure 7 Another schematic diagram of the structure of the sixth metal layer in the display panel is shown, Fig.15 The pixel circuit shown is Fig.14 correspond, Fig.15 FIG. 1 shows a partial film stack diagram in a pixel circuit, including a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC and a fifth metal layer M2. The schematic diagrams of other film layers can be referred to in FIG. Figures 16 to 20 Figure 2 shows the structure of a single film layer. Figures 14 to 20 In the illustrated embodiment, each transistor in the pixel circuit may still be a first type transistor, the active layers of the driving transistor T3 and the threshold compensation transistor T4 are both located in the first semiconductor layer POLY, and the connection portion 101 of the active layers of the two is located in the first semiconductor layer POLY.

[0085] Optional, such as Figure 7 , Figures 14 to 20As shown, the bias signal line DVH may include a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the second direction Y and is arranged in the first direction X, and the second sub-bias signal line DVH2 extends along the first direction X and is arranged in the second direction Y; the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are connected to form a grid-like routing, thereby reducing the resistance of the bias signal line DVH and improving the signal transmission effect. The first electrode C1 of the storage capacitor Cst, the first scan signal line S1, the second scan signal line S2, the third scan signal line SP and the light-emitting control signal line EM may be located in the first metal layer M1. The second electrode C2 of the storage capacitor Cst, the first sub-initialization signal line Vref11 extending along the second direction Y, the third sub-initialization signal line Vref21 and the first sub-bias signal line DVH1, etc. may be located in the second metal layer MC; wherein the third sub-initialization signal line Vref21 and the first sub-bias signal line DVH1 located in the second metal layer MC may be arranged alternately along the first direction X. The second data division 2012, the fourth sub-initialization signal line Vref22 and the second sub-bias signal line DVH2 extending along the first direction X, and the connecting cross-line, etc. may be located in the fifth metal layer M2; wherein the fourth sub-initialization signal line Vref22 and the second sub-bias signal line DVH2 located in the fifth metal layer M2 may be arranged alternately along the second direction Y. The third sub-initialization signal line Vref21 and the fourth sub-initialization signal line Vref22 are connected to form a grid-like routing, and the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are connected to form a grid-like routing. The first data division 2011, the first power voltage signal line PVDD and the data signal line Data extending in the first direction X may be located in the sixth metal layer M3. In this embodiment, the first functional structure portion 501 may also be disposed in the first metal layer M1 and / or the second metal layer MC, and the orthographic projection of the first functional structure portion 501 on the substrate 40 covers at least a portion of the overlapping area of ​​the first data division 2011 and the connecting portion 101. Fig.18 It is shown in the figure that the first functional structure part 501 is located in the second metal layer MC, but it is not limited thereto.

[0086] Optionally, in another possible embodiment, the pixel circuit also includes at least one first type transistor and at least one second type transistor; the first type transistor includes a driving transistor, and the second type transistor includes a threshold compensation transistor; the pixel circuit also includes a storage capacitor, and the storage capacitor includes a first electrode and a second electrode arranged opposite to each other; the display panel also includes a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer and a third metal layer arranged in a stacked manner, and the third metal layer is located on the side of the second semiconductor layer away from the substrate; the active layer of the driving transistor is located in the first semiconductor layer, the first electrode is located in the first metal layer, the second electrode is located in the second metal layer, the active layer of the threshold compensation transistor is located in the second semiconductor layer, the connecting portion is located in the first semiconductor layer and / or the second semiconductor layer, and the top gate of the second type transistor is located in the third metal layer; the first data portion is located on the side of the third metal layer away from the substrate; the connecting portion is located in the first semiconductor layer, and the first functional structure portion is located in at least one of the first metal layer, the second metal layer, the second semiconductor layer or the third metal layer; or, the connecting portion is located in the second semiconductor layer, and the first functional structure portion is located in the third metal layer.

[0087] In this embodiment, the pixel circuit may include two types of transistors. The first type of transistor is described in the above embodiment and will not be repeated here. The second type of transistor may be an oxide transistor, and the active layer of the second type of transistor is an oxide semiconductor layer to form an LTPO display panel. In this way, the pixel circuit has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility and low power of the low-temperature polysilicon transistor. Exemplarily, in the pixel circuit, the threshold compensation transistor and the initialization transistor may be the second type of transistor, and other transistors such as the drive transistor may be the first type of transistor.

[0088] Fig.21 A circuit structure diagram of another pixel circuit provided by an embodiment of the present invention is shown. Fig. 22 A schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present invention, Fig.21 The pixel circuit shown may still be an "8T1C" pixel circuit. Fig.21 and Fig. 22As shown, the film layer structure of the pixel circuit 10 from the bottom to the light-emitting side of the display panel may be a substrate 40, a buffer layer 601, a first semiconductor layer POLY, a first insulating layer 602, a first metal layer M1, an interlayer insulating layer 603, a second metal layer MC, a second insulating layer 604, a second semiconductor layer IGZO, a third insulating layer 605, a third metal layer MG, a fourth insulating layer 607, a fifth metal layer M2, a fifth insulating layer 608, a sixth metal layer M3, a sixth insulating layer 609, a seventh metal layer M4, a planarization layer 606 and an anode layer RE, the first semiconductor layer POLY is a silicon semiconductor layer, and the second semiconductor layer IGZO is an oxide semiconductor layer. For the specific film layer structure of the pixel circuit 10, adaptive adjustments can be made according to actual needs, such as adding or removing some film layers, and any one of the above film layers can include at least one sublayer, which is not specifically limited in the embodiment of the present invention.

[0089] Fig.21 In the pixel circuit shown, the threshold compensation transistor T4 and the initialization transistor T5 are both second type transistors. The connection relationship between the above transistors is the same as that of the above Figure 4 In this embodiment, the gate of the data writing transistor T2 is connected to the fourth scanning signal line SP*, the gate of the threshold compensation transistor T4 is connected to the second scanning signal line S2, the gate of the initialization transistor T5 is connected to the first scanning signal line S1, and the gate of the anode reset transistor T7 and the gate of the bias transistor T8 are connected to the third scanning signal line SP.

[0090] Fig.23 A schematic diagram of a film layer structure of another pixel circuit provided in an embodiment of the present invention, Fig.23 The film structure shown can correspond to Fig.21 The pixel circuit provided, Fig.23 The cross-sectional film structure of the pixel circuit shown in Fig. 22 Shown in. Fig.24 for Fig. 22 The schematic diagram of a part of the structure of the display panel is shown. Fig.25 for Fig. 22 The schematic diagram of another part of the structure of the display panel is shown. Fig.26 for Fig. 22 The schematic diagram of another part of the structure of the display panel is shown. Fig. 27 for Fig. 22 The schematic diagram of another part of the structure of the display panel is shown. Fig.28 for Fig. 22 The schematic diagram of another part of the structure of the display panel is shown. Fig.29 for Fig. 22 The schematic diagram of another part of the structure of the display panel is shown. Fig.30 for Fig. 22The schematic diagram of another part of the structure of the display panel is shown. Fig.23 FIG. 1 shows a partial film stack diagram in a pixel circuit, including a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a second semiconductor layer IGZO, a third metal layer MG and a fifth metal layer M2. The schematic diagrams of other film layers can be referred to in FIG. Figure 23 to Figure 30 The single film structure diagram in . Among them, Fig.23 The figure shows the structure diagram of the first semiconductor layer POLY. Fig.23 FIG. 1 is a schematic diagram showing the structure of the first metal layer M1. Fig.25 It is a schematic diagram of the structure of the second metal layer MC. Fig.26 The figure shows the structure diagram of the second semiconductor layer IGZO. Fig. 27 FIG. 1 is a schematic diagram of the structure of the third metal layer MG, a schematic diagram of the structure of the fifth metal layer M2, Fig.13 FIG. 4 is a schematic diagram showing the structure of the sixth metal layer M3.

[0091] refer to Figure 21 to Figure 30, the active layer of the driving transistor T3 is located in the first semiconductor layer POLY, the first electrode C1 of the storage capacitor Cst can be formed in the first metal layer M1, and the first metal layer M1 can also be used to form a portion of the scanning signal lines extending along the second direction Y, such as the third scanning signal line SP, the fourth scanning signal line SP* and the light-emitting control signal line EM, etc., and the gate of the driving transistor T3 is located in the first metal layer M1. The second electrode C2 of the storage capacitor Cst can be formed in the second metal layer MC, and the second metal layer MC can also be used to form a portion of the signal lines extending along the second direction Y, such as the first sub-initialization signal line Vref11 extending along the second direction Y, the first scanning signal line S1-1 and the second scanning signal line S2-1 extending along the second direction Y, etc. The active layer of the threshold compensation transistor T4 may be located in the second semiconductor layer IGZO; the third metal layer MG may include a first scan signal line S1-2, a second scan signal line S2-2, a third sub-initialization signal line Vref21, and a first sub-bias signal line DVH1 extending along the second direction Y; the third sub-initialization signal line Vref21 and the first sub-bias signal line DVH1 may be alternately arranged along the first direction X. The active layer of the threshold compensation transistor T4 overlaps with the second scan signal line S2-1 to form the bottom gate of the threshold compensation transistor T4, and overlaps with the second scan signal line S2-2 to form the top gate of the threshold compensation transistor T4; the active layer of the initialization transistor T5 overlaps with the first scan signal line S1-1 to form the bottom gate of the initialization transistor T5, and overlaps with the first scan signal line S1-2 to form the top gate of the initialization transistor T5. Among them, the active layer of the driving transistor T3 and the active layer of the threshold compensation transistor T4 are located in different film layers, and the active layers of the two need to be connected by punching. Therefore, the connecting portion 101 can be located in the first semiconductor layer POLY and / or the second semiconductor layer IGZO. The figure shows that the connecting portion 101 is located in the first semiconductor layer POLY, but it is not limited to this. The second data division 2012 can be formed in the fifth metal layer M2, and the fifth metal layer M2 can also be used to form a portion of the signal line extending along the second direction Y and a portion of the connecting line 61. The first data division 2011 can be formed in the sixth metal layer M3, and the sixth metal layer M3 can also be used to form a portion of the signal line extending along the first direction X, such as the first power supply voltage signal line PVDD, the data signal line Data, the fourth sub-initialization signal line Vref22, and the second sub-bias signal line DVH2 extending along the first direction X. The fourth sub-initialization signal line Vref22 and the second sub-bias signal line DVH2 can be arranged alternately along the second direction Y. The third sub-initialization signal line Vref21 and the fourth sub-initialization signal line Vref22 are connected to form a grid-like routing, and the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are connected to form a grid-like routing.

[0092] When the connection part 101 is located in the first semiconductor layer POLY, the first functional structure part 501 can be set in any conductive film layer between the first semiconductor layer POLY and the sixth metal layer M3, for example, the first functional structure part 501 can be formed in at least one of the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO and the third metal layer MG. It should be noted that if the first functional structure part 501 is prepared in the second semiconductor layer IGZO, the second semiconductor layer IGZO in the target area needs to be conductorized, and the target area refers to the area overlapping with the connection part 101. When the connection part 101 is located in the second semiconductor layer IGZO, the first functional structure part 501 can be set in any conductive film layer between the first semiconductor layer POLY and the sixth metal layer M3, except the second semiconductor layer IGZO, for example, the first functional structure part 501 can be formed in the third metal layer MG. Fig.24 and Fig.26 exemplarily shows that the connection part 101 is located in the first semiconductor layer POLY, and the first functional structure part 501 is located in the second metal layer MC, but it is not limited thereto. In other embodiments not shown, the connection part 101 is located in Fig. 27 In the second semiconductor layer IGZO shown, the first functional structure portion 501 is located in the third metal layer MG, which is not shown in the drawings.

[0093] Optional, you can continue to refer to Figure 7 to Figure 30 The signal line also includes a scanning signal line and a light-emitting control signal line EM, and the scanning signal line and the light-emitting control signal line EM are both located in the first metal layer M1; the first functional structure portion 501 is located in the second metal layer MC, and along the thickness direction Z of the display panel, the first functional structure portion 501 does not overlap with the scanning signal line and the light-emitting control signal line EM.

[0094] The scan signal line may include at least one of the first scan signal line S1, the second scan signal line S2, the third scan signal line SP, and the fourth scan signal line SP* described above. Figure 7 to Figure 30 As shown, the scanning signal line and the light-emitting control signal line EM are both formed in the first metal layer M1, and the second functional structure part 502 can be formed in the second metal layer MC, that is, the first functional structure part 501 and the scanning signal line and the light-emitting control signal line EM are all arranged in different layers; and the first functional structure part 501 and the scanning signal line and the light-emitting control signal line EM do not overlap in the display panel thickness direction Z. In this way, parasitic capacitance between the first functional structure part 501 and the scanning signal line (light-emitting control signal line EM) can be avoided, and the first functional structure part 501 can be avoided from affecting the signal in the scanning signal line (light-emitting control signal line EM).

[0095] Fig.31A schematic diagram of the structure of a first metal layer and a second metal layer provided in an embodiment of the present invention, taking the first functional structure part 501 located in the second metal layer MC as an example, can be referred to Fig.31 In a possible embodiment, the minimum spacing between the orthographic projection of the first functional structure part 501 on the plane where the first metal layer M1 is located and the scanning signal line in the first direction X is d1, and the minimum spacing between the orthographic projection of the first functional structure part 501 and the light emitting control signal line EM in the first direction X is d2; wherein, 0≤d1≤2*a; 0≤d2≤2*a; a represents the minimum alignment error between different film layers in the display panel manufacturing process.

[0096] like Fig.31 As shown, the film layer where the first functional structure part 501 is located is different from the first metal layer M1, and the scanning signal line and the light-emitting control signal line EM are formed before the first functional structure part 501. In this embodiment, the minimum spacing between the first functional structure part 501 and the scanning signal line (light-emitting control signal line EM) is controlled within the above-mentioned numerical range to meet the requirements of process error. Among them, the specific value of a is not limited and can be set by those skilled in the art according to actual conditions. Fig.31 In the illustrated embodiment, the second scanning signal line S2 is the scanning signal line closest to the first functional structure portion 501 along the first direction X, and the minimum distance between the first functional structure portion 501 and the second scanning signal line S2 in the first direction X can be set to d1.

[0097] Optional, you can continue to refer to Fig.18 , Fig.26 and Fig.31 , the first functional structure portion 501 is connected to the second electrode plate C2; ​​along the first direction X, the width of the first functional structure portion 501 is greater than or equal to the width of the second electrode plate C2.

[0098] like Fig.18 , Fig.26 and Fig.31As shown, as an optional solution, when the first functional structure part 501 is located in the second metal layer MC, the first functional structure part 501 can be further connected to the second plate C2 of the storage capacitor Cst, and the first functional structure part 501 and the second plate C2 can be formed in the same mask process. In addition, as described above, the second plate C2 of the storage capacitor Cst is connected to the first power supply voltage signal line PVDD, receives the first power supply voltage signal, and the first power supply voltage signal is a fixed potential signal. The first functional structure part 501 is connected to the storage capacitor Cst, and the first power supply voltage signal line PVDD can be used to provide a fixed potential signal to the first functional structure part 501, thereby eliminating the need to prepare an additional fixed potential signal line; in addition, the resistance on the first power supply voltage signal line PVDD can be reduced, thereby reducing the impedance of the first power supply voltage signal line PVDD. The figure shows that the width of the first functional structure part 501 is equal to the width of the second plate C2, but it is not limited to this.

[0099] refer to Fig.18 , Fig.26 and Fig.31 Along the thickness direction of the display panel, the overlapping area between the first data division 2011 and the connecting portion 101 overlaps with the gap area between the two adjacent second electrodes C2 set in a mirror image. Therefore, the first functional structure portion 501 can be set to connect the second electrodes C2 of the storage capacitors Cst in the two pixel circuits 10 adjacent to each other along the second direction Y, and the width of the first functional structure portion 501 along the first direction X is set to be greater than or equal to the width of the second electrode C2 along the first direction X. In this way, the shielding effect of the first functional structure portion 501 on the overlapping area can be guaranteed, and the coupling capacitance between the first data division 2011 and the connecting portion 101 can be reduced.

[0100] Optionally, in some other embodiments of the present invention, in the LTPO display panel, the first functional structure portion 501 may be located in the third metal layer MG.

[0101] The third metal layer MG is the metal layer closest to the second semiconductor layer IGZO on the side of the second semiconductor layer IGZO away from the substrate 40. The third metal layer MG includes structures such as the top gate of the second type transistor. There are fewer wirings in the metal layer, so that the first functional structure part 501 is formed in the third metal layer MG, which can reduce the difficulty of arranging the first functional structure part 501. In addition, in this embodiment, the first power supply voltage signal line can be arranged in the fifth metal layer M2 on the side of the third metal layer MG away from the second semiconductor layer IGZO, and the first functional structure part 501 can be connected to the first power supply voltage signal line PVDD in the fifth metal layer M2, thereby providing a fixed potential signal to the first functional structure part 501 and reducing the resistance of the first power supply voltage signal line PVDD.

[0102] Of course, in some other embodiments of the present invention, the first functional structure portion 501 may be located in both the third metal layer MG and the second metal layer MC, and connected to the second electrode plate C2 (first power supply voltage signal line) of the storage capacitor Cst. The portion of the first functional structure portion 501 located in the second metal layer MC is connected to the portion located in the third metal layer MG through a via, thereby further reducing the resistance of the first power supply voltage signal line PVDD.

[0103] Optional, Fig.32 A schematic diagram of a film layer structure of another pixel circuit provided in an embodiment of the present invention, Fig.33 for Fig.32 The schematic diagram of the structure of the membrane layer where the second functional structure is located, Fig.34 for Fig.32 The enlarged structural diagram can be combined with reference Figure 32 to Figure 34 In another possible embodiment, the functional structure portion 50 may include a second functional structure portion 502, and the film layer where the second functional structure portion 502 is located is located on the side of the film layer where the connecting portion 101 is located, away from the film layer where the first data portion 2011 is located; along the thickness direction of the display panel, the second functional structure portion 502 covers the connecting portion 101, and the coverage area of ​​the second functional structure portion 502 is greater than the area of ​​the connecting portion 101.

[0104] Fig.32 The figure shows the film layer where the connection part 101 is located, the film layer where the first data division part 2011 is located, and the film layer where the second functional structure part 502 is located, wherein the film layer where the connection part 101 is located can be the above-mentioned Figure 7 and Fig.16 The first semiconductor layer POLY shown in FIG. 1 , the film layer where the first data division 2011 is located may be Figure 7 and Fig. 20 The sixth metal layer M3 is shown in FIG. Fig.34 The first data division 2011 is not shown in the enlarged structure diagram, and only the connection part 101 and the second functional structure part 502 are shown. Figure 32 to Figure 34 As shown, the second functional structure portion 502 is formed in the conductive film layer on the side of the film layer where the connection portion 101 is located facing the substrate 40, that is, along the thickness direction of the display panel, the connection portion 101 is located between the second functional structure portion 502 and the first data portion 2011. The orthographic projection graphic area of ​​the second functional structure portion 502 on the substrate 40 is larger than the orthographic projection graphic area of ​​the connection portion 101 on the substrate 40, so that the second functional structure portion 502 completely covers the connection portion 101, and along the thickness direction of the display panel, the edge of the second functional structure portion 502 exceeds the connection portion 101.

[0105] Fig.35 A schematic diagram of an electric field provided in an embodiment of the present invention, wherein the curved arrows in the figure indicate the electric field distribution, Fig.35If the second functional structure part 502 is arranged in the film layer on the side of the connecting part 101 away from the first data division 2011, the coverage area of ​​the second functional structure part 502 can be appropriately increased, thereby ensuring that an electric field can be formed between the second functional structure part 502 and the first data division 2011, so that the second functional structure part 502 effectively weakens the parasitic capacitance between the first data division 2011 and the connecting part 101.

[0106] Fig.36 A schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present invention can be combined with reference to Figure 32 to Figure 36 The display panel also includes a fourth metal layer M0, which is located on a side of the film layer where the connecting portion 101 is located, away from the film layer where the first data portion 2011 is located; the fourth metal layer M0 includes a plurality of shading portions BSM, and along the thickness direction Z of the display panel, the shading portion BSM overlaps with the channel region of the transistor in the pixel circuit 10; the second functional structure portion 502 is located in the fourth metal layer M0.

[0107] Fig.36 The display panel shown is Figure 7 A fourth metal layer M0 is added to the display panel as shown. Figure 32 to Figure 36 As shown, taking the example that the connection portion 101 is located in the first semiconductor layer POLY and the first data portion 2011 is located in the sixth metal layer M3, the fourth metal layer M0 can be located between the substrate 40 and the first semiconductor layer POLY, for example, can be arranged between the substrate 40 and the buffer layer 601. The fourth metal layer M0 includes a plurality of light shielding portions BSM, and the light shielding portions BSM are used to shield the channel region of at least part of the transistor to avoid the generation of photogenerated carriers and improve the stability of the transistor. In this embodiment, the second functional structure portion 502 can be formed in the fourth metal layer M0, and the second functional structure portion 502 and the light shielding portion BSM can be formed in the same mask process.

[0108] The second functional structure part 502 and the light shielding part BSM can also be connected to the first power supply voltage signal with a fixed potential to ensure the stability of the electric field between the second functional structure part 502 and the first data part 2011, and also avoid the signals in the functional structure part 50 and the light shielding part BSM from affecting the channel current.

[0109] Optionally, in some other possible embodiments, the functional structure portion includes a third functional structure portion, and the film layer where the third functional structure portion is located is located on a side of the film layer where the first data portion is located away from the film layer where the connection portion is located.

[0110] Taking the example that the connection part is located in the first semiconductor layer and / or the second semiconductor layer, and the first data division is located in the sixth metal layer, the third functional structure part (not shown in the figure) can be formed in the conductive film layer on the side of the sixth metal layer away from the first semiconductor layer. In this arrangement, the electric field between the third functional structure part and the first data division is formed on the side of the film layer where the first data division is located away from the film layer where the connection part is located, which can also play a role in reducing the parasitic capacitance between the first data division and the connection part.

[0111] You can continue to refer to Figure 3 In some embodiments, the signal line 20 may further include a virtual connection line 202, the virtual connection line 202 includes a first virtual division 2021 located in the second display area AA2, the first virtual division 2021 extends along the first direction X and is insulated from the first data division 2011; the display panel also includes a virtual functional structure portion (not shown in the figure), and the virtual functional structure portion overlaps with the first virtual division 2021 along the thickness direction of the display panel.

[0112] like Figure 3 As shown, the virtual connection line 202 includes a first virtual sub-section 2021 and a second virtual sub-section 2022, wherein the first virtual sub-section 2021 extends along the first direction X, and the second virtual sub-section 2022 extends along the second direction Y, wherein the first virtual sub-section 2021 can be arranged on the same layer as the first data sub-section 2011, and the two can be insulated from each other; the second virtual sub-section 2022 can be arranged on the same layer as the second data sub-section 2012, and the two can be insulated from each other. The distribution mode of the first virtual sub-section 2021 in the second display area AA2 is similar to the distribution mode of the first data sub-section 2011 in the first display area AA1, and by setting the virtual connection line 202, the balance of the wiring layout can be ensured as a whole, and the stability of the display surface signal transmission can be ensured.

[0113] Correspondingly, the display panel may further include a virtual functional structure portion (not shown in the drawings), which may be located in the second display area and in a different layer from and insulated from the first virtual portion. The virtual functional structure portion is arranged in the same layer as the functional structure portion, and the distribution of the virtual functional structure portion in the second display area is similar to the distribution of the functional structure portion in the first display area. By providing the virtual functional structure portion, the distribution uniformity of the guide structure (including the functional structure portion and the virtual functional structure portion) in the entire display area can be improved, which is conducive to ensuring that the overall light transmittance and flatness of the display panel are better.

[0114] Among them, the virtual functional structure part and the first virtual part overlap in the thickness direction of the display panel, and the electric field formed between the virtual functional structure part and the first virtual part can be used to weaken the parasitic capacitance between the first virtual part and the connecting part, thereby eliminating the influence of the first virtual part on the third node potential of the pixel circuit in the second display area.

[0115] Furthermore, the first virtual sub-portion may be electrically connected to the fixed potential signal line; and the virtual functional structure portion may be electrically connected to the fixed potential signal line.

[0116] Specifically, the first virtual division and the virtual functional structure can be connected to the fixed potential signal line. The first virtual division and the virtual functional structure will not interfere with other signals, and can also reduce the resistance of the fixed potential signal line, reduce impedance, and improve the signal transmission effect in the display panel.

[0117] The first virtual sub-portion and the virtual functional structure portion may be connected to the same or different fixed potential signal lines, which is not limited in the embodiment of the present invention.

[0118] Optional, Fig.37 A schematic diagram of the structure of an anode layer in a display panel provided by an embodiment of the present invention, referring to Fig.37 The display panel further includes a light-emitting element D, which is electrically connected to the pixel circuit; the light-emitting element D includes a first color light-emitting element D1, a second color light-emitting element D2, a third color light-emitting element D3 and a fourth color light-emitting element D4, and the first color light-emitting element D1, the second color light-emitting element D2, the third color light-emitting element D3 and the fourth color light-emitting element D4 are one or more of a red light-emitting element, a blue light-emitting element, a green light-emitting element and a white light-emitting element; a plurality of first color light-emitting elements D1 and a second color light-emitting element D2 form a first virtual quadrilateral 71, and the first color light-emitting element D1 is in the first virtual quadrilateral 7 1, the center of the second color light emitting element D2 is at the second vertex of the first virtual quadrilateral 71, the first vertex and the second vertex are alternate and spaced apart, and the third color light emitting element D3 or the fourth color light emitting element D4 is inside the first virtual quadrilateral 71; a plurality of third color light emitting elements D3 and / or fourth color light emitting elements D4 constitute a second virtual quadrilateral 72, the centers of the plurality of third color light emitting elements D3 and / or fourth color light emitting elements D4 are respectively at the vertices of the second virtual quadrilateral 72, and the first color light emitting element D1 or the second color light emitting element D2 is inside the second virtual quadrilateral 72.

[0119] For details, see Fig.37 , a plurality of first color light emitting elements D1 and second color light emitting elements D2 form a first virtual quadrilateral 71, two first color light emitting elements D1 are located at opposite corners of the first virtual quadrilateral 71, and two second color light emitting elements D2 are located at the other two opposite corners of the first virtual quadrilateral 71. And the third color light emitting element D3 or the fourth color light emitting element D4 is placed at the center of the first virtual quadrilateral 71.

[0120] Further, a plurality of third color light emitting elements D3 and / or fourth color light emitting elements D4 may also form a second virtual quadrilateral 72, and the third color light emitting elements D3 and / or fourth color light emitting elements D4 are located at the vertices of the second virtual quadrilateral 72. In the second virtual quadrilateral 72, the first color light emitting element D1 may be located at the center, or the second color light emitting element D2 may be located at the center.

[0121] The first color, the second color, the third color and the fourth color correspond to one of red, blue, green and white respectively. Through the above-mentioned arrangement of the light-emitting elements D, the rendering effect of the light-emitting elements D can be ensured to be better, further ensuring the color display effect of the display panel.

[0122] It should be noted that Fig.37 Only the anode corresponding to the light-emitting element D is shown, and the anode is used to represent the light-emitting elements D of different colors.

[0123] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.38 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present invention. Fig.38 As shown, the display device includes the display panel 100 provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a car display device, which is not limited by the embodiment of the present invention.

[0124] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: including a plurality of pixel circuits and a plurality of signal lines; The pixel circuit includes a driving transistor and a threshold compensation transistor; the signal line includes a plurality of data signal lines, and the plurality of data signal lines extend along a first direction and are arranged along a second direction; The display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least on one side of the first display area along the second direction; the first display area and the second display area both comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located on one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out routing lines; the signal lines further comprise a data connection line, the data signal lines located in the second display area are electrically connected to the fan-out routing lines through the data connection line; The pixel circuit further includes a connection portion, the connection portion connecting the active layer of the driving transistor and the active layer of the threshold compensation transistor; the data connection line includes a first data portion, the first data portion extending along the first direction; the display panel further includes a substrate, and a minimum distance between an orthographic projection of the first data portion on a plane where the substrate is located and an orthographic projection of the connection portion on the plane where the substrate is located in the second direction is less than a preset distance; The display panel further includes a functional structure portion, which is insulated from the first data portion; along a thickness direction of the display panel, the functional structure portion overlaps with the first data portion.

2. The display panel according to claim 1, characterized in that: The functional structure portion is electrically connected to the fixed potential signal line.

3. The display panel according to claim 1, characterized in that: The functional structure part includes a first functional structure part, and the film layer where the first functional structure part is located is located between the film layer where the connecting part is located and the film layer where the first data division part is located; The orthographic projection of the first data portion on the plane where the substrate is located and the orthographic projection of the connecting portion on the plane where the substrate is located have an overlapping area; The orthographic projection of the first functional structure portion on the plane where the substrate is located covers at least a portion of the overlapping area.

4. The display panel according to claim 3, characterized in that: The pixel circuit further includes at least one first type transistor, the first type transistor including the driving transistor and the threshold compensation transistor; The pixel circuit further includes a storage capacitor, wherein the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other; The display panel further comprises a first semiconductor layer, a first metal layer and a second metal layer which are stacked, wherein the second metal layer is located on a side of the first metal layer away from the substrate; the active layer of the driving transistor, the active layer of the threshold compensation transistor and the connecting portion are all located on the first semiconductor layer; The first electrode plate is located at the first metal layer; The second electrode plate is located at the second metal layer; the first data portion is located at a side of the second metal layer away from the substrate; The first functional structure portion is located in the first metal layer and / or the second metal layer.

5. The display panel according to claim 3, characterized in that: The pixel circuit further includes at least one first type transistor and at least one second type transistor; the first type transistor includes the driving transistor, and the second type transistor includes the threshold compensation transistor; The pixel circuit further includes a storage capacitor, wherein the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer and a third metal layer which are stacked, the third metal layer being located on a side of the second semiconductor layer away from the substrate; the active layer of the driving transistor is located on the first semiconductor layer, the first electrode is located on the first metal layer, the second electrode is located on the second metal layer, the active layer of the threshold compensation transistor is located on the second semiconductor layer, the connecting portion is located on the first semiconductor layer and / or the second semiconductor layer, and the top gate of the second type transistor is located on the third metal layer; the first data portion is located on a side of the third metal layer away from the substrate; The connecting portion is located in the first semiconductor layer, and the first functional structure portion is located in at least one of the first metal layer, the second metal layer, the second semiconductor layer or the third metal layer; The connecting portion is located in the second semiconductor layer, and the first functional structure portion is located in the third metal layer.

6. The display panel according to claim 4 or 5, characterized in that: The signal lines further include scanning signal lines and light-emitting control signal lines, and the scanning signal lines and the light-emitting control signal lines are both located in the first metal layer; The first functional structure portion is located in the second metal layer, and along the thickness direction of the display panel, the first functional structure portion does not overlap with the scanning signal line and the light emitting control signal line.

7. The display panel according to claim 6, characterized in that: The minimum distance between the orthographic projection of the first functional structure on the plane where the first metal layer is located and the scanning signal line in the first direction is d1, and the minimum distance between the orthographic projection of the first functional structure and the light emitting control signal line in the first direction is d2; Among them, 0≤d1≤2*a; 0≤d2≤2*a; a represents the minimum alignment error between different film layers in the display panel manufacturing process.

8. The display panel according to claim 6, characterized in that: The first functional structure part is connected to the second electrode plate; Along the first direction, the width of the first functional structure portion is greater than or equal to the width of the second electrode plate.

9. The display panel according to claim 5, characterized in that: The first functional structure portion is located in the third metal layer.

10. The display panel according to claim 1, characterized in that: The functional structure part includes a second functional structure part, and the film layer where the second functional structure part is located is located on a side of the film layer where the connection part is located away from the film layer where the first data division part is located; Along the thickness direction of the display panel, the second functional structure portion covers the connecting portion, and a covering area of ​​the second functional structure portion is larger than an area of ​​the connecting portion.

11. The display panel according to claim 10, characterized in that: The display panel further includes a fourth metal layer, and the fourth metal layer is located on a side of the film layer where the connection portion is located away from the film layer where the first data portion is located; The fourth metal layer includes a plurality of light shielding sections, and along the thickness direction of the display panel, the light shielding sections overlap with the channel regions of the transistors in the pixel circuit; The second functional structure portion is located in the fourth metal layer.

12. The display panel according to claim 1, characterized in that: The functional structure portion includes a third functional structure portion, and the film layer where the third functional structure portion is located is located on a side of the film layer where the first data portion is located away from the film layer where the connection portion is located.

13. The display panel according to claim 1, characterized in that: The signal line further includes a virtual connection line, wherein the virtual connection line includes a first virtual sub-portion located in the second display area, the first virtual sub-portion extends along the first direction and is insulated from the first data sub-portion; The display panel further includes a dummy functional structure portion, and along a thickness direction of the display panel, the dummy functional structure portion overlaps with the first dummy sub-portion.

14. The display panel according to claim 13, characterized in that: The first virtual subdivision is electrically connected to the fixed potential signal line; The dummy functional structure portion is electrically connected to the fixed potential signal line.

15. The display panel according to claim 1, characterized in that: The display panel further comprises a light emitting element, wherein the light emitting element is electrically connected to the pixel circuit; The light-emitting elements include a first color light-emitting element, a second color light-emitting element, a third color light-emitting element and a fourth color light-emitting element, wherein the first color light-emitting element, the second color light-emitting element, the third color light-emitting element and the fourth color light-emitting element are one or more of a red light-emitting element, a blue light-emitting element, a green light-emitting element and a white light-emitting element; A plurality of the first color light emitting elements and the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements are located at first vertices of the first virtual quadrilateral, the centers of the second color light emitting elements are located at second vertices of the first virtual quadrilateral, the first vertices and the second vertices are alternately and spaced apart, and the third color light emitting element or the fourth color light emitting element is located inside the first virtual quadrilateral; The plurality of third color light emitting elements and / or fourth color light emitting elements constitute a second virtual quadrilateral, the centers of the plurality of third color light emitting elements and / or fourth color light emitting elements are respectively located at the vertices of the second virtual quadrilateral, and the first color light emitting element or the second color light emitting element is located inside the second virtual quadrilateral.

16. A display device, characterized in that: A display panel comprising any one of claims 1-15.

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