Planar low-operating-voltage photoelectric synaptic memristor and preparation method thereof

Abstract

The invention belongs to the technical field of organic electronics and information, and particularly relates to a low-operating-voltage photoelectric synaptic memristor based on a plane type and a preparation method of the low-operating-voltage photoelectric synaptic memristor. The memristor comprises a bottom substrate, and an insulating layer, a functional layer and a top electrode which are sequentially arranged on the bottom substrate; wherein the bottom substrate is made of silicon, the insulating layer is made of silicon dioxide, the functional layer is made of copper phthalocyanine, and the top electrode is made of silver; the preparation method of the memristor comprises the following steps: S1, growing a silicon dioxide insulating layer on a silicon substrate, and cleaning and drying the silicon dioxide insulating layer; s2, a copper phthalocyanine functional layer is formed on the sample treated in the step S1 through vacuum evaporation; and S3, performing vacuum evaporation on a silver electrode on the sample treated in the S2, and cooling to room temperature to obtain the planar low-operation-voltage photoelectric synaptic memristor. The device is simple in structure and good in repeatability, and provides more possibilities for simulating visual perception and machine learning.

Description

Technical Field

[0001] The invention belongs to the field of organic electronics and information technology, and in particular relates to a planar low-operating-voltage photoelectric synaptic memristor and a preparation method thereof. Background Art

[0002] With the continuous and rapid development of modern information technology, computing systems require fast information processing and massive data storage. Compared with the traditional von Neumann computing system with separate computing units and storage, the biological brain has the advantages of high efficiency, low power consumption, integrated storage and computing, and autonomous cognition. Inspired by the biological brain, neuromorphic computing has become a competitor for the next generation of computing systems. The biological brain is an extremely complex biological system consisting of hundreds of billions of neurons. Neurons are the basic structural and functional units of the nervous system. Neurons are connected by nerve fibers to form complex neural networks and neural circuits that dominate various brain functions. The function of the brain depends on the interaction and information transmission between neurons. The connection point between neurons is called synapse, which is a key structure for information transmission. Since synapses are necessary in connecting neurons and realizing brain functions, efficient artificial synapses are an important cornerstone of neuromorphic computing. Memristors, due to their unique physical properties, are considered to have great potential in simulating and realizing the functions of biological synapses, and are one of the key technologies for the development of neuromorphic computing and intelligent systems. In order to better cooperate with the progress of algorithms, especially optoelectronic synaptic devices, significant progress has been made in simulating the functions of biological synapses in the brain in recent years. Among many different types of artificial synaptic devices, optoelectronic artificial synapses that can mimic or even surpass the functions of the human eye are the most important. The human eye is a window to the world; about 80% of external information is received by the human visual system. The light signal is then converted into neural pulses and transmitted to the brain through the optic nerve and synapses. Therefore, mimicking the visual perception function will be a key step in machine vision and artificial intelligence. Among the simulated artificial synaptic devices, the optoelectronic synaptic memristor is a new type of electronic device that combines the characteristics of optoelectronics and memristors, which mimics the synaptic function in biological nervous systems. This device is able to convert between electrical and optical signals and has a memory function, that is, it can adjust its response based on the history of the input signal. Compared with traditional electrical synaptic memristors, optoelectronic synaptic memristors can be stimulated by photoelectric co-stimulation, and have the advantages of high bandwidth, low crosstalk, low power consumption, and no resistance and capacitance delay. Therefore, in the process of simulating the visual system, optoelectronic memristors have become a strong competitor.

[0003] Among the current photoelectric synaptic memristors, most simulate photoelectric synapses stimulated by a single wavelength, and there are few simulations of synapses using multiple wavelengths, especially those combining the conductivity range of multiple wavelengths. In addition, there is no good regulation of linearity under single-wavelength stimulation, which poses a great challenge to simulating visual systems. In summary, it is necessary to regulate different light parameters and simulate synapses under multiple wavelengths.

[0004] Therefore, it is of great significance to develop a planar-based low-operating-voltage photosynaptic memristor and optimize its preparation method. Summary of the invention

[0005] Purpose of the invention: The technical problem to be solved by the present invention is to provide a planar low operating voltage photoelectric synaptic memristor in view of the deficiencies in the prior art. The device structure of the memristor is a planar structure.

[0006] In order to solve the above technical problems, the present invention discloses a planar low operating voltage photoelectric synaptic memristor, comprising a bottom substrate and an insulating layer, a functional layer and a top electrode sequentially arranged on the bottom substrate; wherein the bottom substrate is silicon, the insulating layer is silicon dioxide, the functional layer is phthalocyanine copper, and the top electrode is silver.

[0007] Wherein, the thickness of the insulating layer is 40 to 60 nm;

[0008] Preferably, the thickness of the insulating layer is 50 nm.

[0009] Wherein, the thickness of the functional layer is 30 to 50 nm;

[0010] Preferably, the thickness of the functional layer is 40 nm.

[0011] Wherein, the thickness of the top electrode is 30-40nm.

[0012] The memristor is a planar structure, and the width of the middle channel of the memristor is 5 μm.

[0013] The present invention also discloses a method for preparing a planar low-operating-voltage photoelectric synaptic memristor, comprising the following steps:

[0014] S1. Growing a silicon dioxide insulating layer on a silicon substrate, cleaning and drying;

[0015] S2. Cover the sample treated in S1 with a planar mask and evacuate the chamber until the pressure inside the chamber is less than 5×10 -4 Pa, vacuum-deposit a phthalocyanine copper functional layer, and cool to room temperature while maintaining the vacuum state;

[0016] S3. After the sample treated in S2 is cooled, vacuum the chamber until the pressure is less than 5×10 -4 Pa, and then vacuum evaporate silver electrodes, and keep the vacuum state and cool to room temperature to obtain the planar-based low operating voltage photoelectric synaptic memristor.

[0017] Among them, in S1, the cleaning process is ultrasonic cleaning with acetone, ethanol and deionized water in sequence, and the time is 30 minutes; the drying process is drying with nitrogen and then drying at 120°C for 60 minutes.

[0018] Among them, in said S2, the specific conditions of vacuum evaporation are that the evaporation rate is The evaporation thickness is 30 to 50 nm.

[0019] Beneficial effects: 1. The present invention adopts a small channel planar structure, which has the advantage of maximizing the light receiving area;

[0020] 2. The present invention can have different responses to light of different wavelengths and different light intensities, and simulate synaptic plasticity at different wavelengths;

[0021] 3. The present invention regulates the linearity at a single wavelength by adjusting the pulse interval, pulse width and light intensity. This effectively solves the problem of poor linearity at a single wavelength;

[0022] 4. The present invention has the characteristics of low operating voltage and high stability. The prepared photoelectric synaptic memristor has a low operating voltage (as low as 0.5V) and more than 300 stable read-write-erase cycles;

[0023] 5. The present invention has a simple structure and good repeatability, and provides more possibilities for simulating visual perception and machine learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0025] Figure 1 A schematic diagram of the structure of a planar low-operating-voltage photoelectric synaptic memristor prepared by the present invention;

[0026] Figure 2 The current-voltage characteristic curve of the memristor based on the SiO2 / Cupc / Ag structure prepared in Example 1 under dark and light conditions when a forward voltage of 1.5V is applied;

[0027] Figure 3 The current-voltage characteristic curve of the memristor based on the SiO2 / Cupc / Ag structure prepared in Example 1 under dark and light conditions when a forward voltage of 0.6V is applied;

[0028] Figure 4 The current-voltage characteristic curve of the memristor based on the SiO2 / Cupc / Ag structure prepared in Example 1 under dark and light conditions when a forward voltage of 0.2V is applied;

[0029] Figure 5 The long-term enhancement-long-term inhibition characteristic curve of the memristor based on the SiO2 / Cupc / Ag structure prepared in Example 1 under dark conditions by applying forward voltages of 1.5V and 0.2V;

[0030] Figure 6 The short-term plasticity-long-term plasticity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 by changing the number of pulses under white light conditions;

[0031] Figure 7 The short-term plasticity-long-term plasticity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 by changing the light intensity under white light conditions;

[0032] Figure 8 The characteristic curve of synaptic plasticity of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 by changing the pulse interval and pulse width under white light conditions;

[0033] Fig. 9 The learning-forgetting-relearning characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under white light conditions;

[0034] Fig.10 The short-term plasticity-long-term plasticity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under ultraviolet light conditions;

[0035] Fig.11 The short-term plasticity-long-term plasticity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under green light conditions;

[0036] Fig.12 The short-term plasticity-long-term plasticity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under orange light conditions;

[0037] Fig.13 This is a linearity modulation characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under orange light conditions;

[0038] Fig.14This is a linearity characteristic curve of the memristor based on SiO2 / Cupc / Ag structure prepared in Example 1 under orange light conditions;

[0039] Fig.15 This is a linearity modulation characteristic curve of the SiO2 / Cupc / Ag structure-based memristor prepared in Example 1 under orange light conditions. DETAILED DESCRIPTION

[0040] The experimental methods described in the following examples are conventional methods unless otherwise specified; the reagents and materials described are commercially available unless otherwise specified.

[0041] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0042] The present invention provides a planar low-operating-voltage photoelectric synaptic memristor, the structure of which is Figure 1 As shown, it includes: a bottom substrate, an insulating layer, a functional layer and a top electrode, and the overall structure adopts a planar structure with a 5μm channel. The functional layer is a p-type material titanium copper cyanide with a thickness of 40nm.

[0043] Embodiment 1:

[0044] (1) A silicon wafer was selected as a substrate, and a layer of silicon dioxide with a thickness of 50 nm was formed on the silicon wafer. The silicon wafer was washed with acetone, ethanol, and deionized water for 30 min in sequence, and then dried with nitrogen and placed in an oven at 120° C. for 60 min for drying;

[0045] (2) Cover the silicon wafer with a planar mask with a channel width of 5 μm, take out copper phthalocyanine from the medicine bottle and put it into a crucible, put the crucible and the covered silicon wafer into a vacuum evaporation equipment, and control the pressure in the vacuum chamber to be less than 5×10 -4 Pa, start evaporating copper phthalocyanine, the evaporation rate is The thickness of copper phthalocyanine is 40nm;

[0046] (3) Place the deposited silicon wafer into the vacuum deposition equipment and control the pressure in the vacuum chamber to be less than 5×10 -4 Pa, start evaporating the metal silver electrode, the evaporation rate is The silver thickness is 30-40 nm; the film thickness is measured using a step profiler and further confirmed by a scanning electron microscope;

[0047] (4) After the evaporation experiment is completed, the metal electrode is cooled to room temperature in a vacuum chamber to obtain a slow-changing memristor. The chamber is then opened to take out the sample and conduct relevant tests on the electrical properties of the memristor sample.

[0048] Performance Testing

[0049] See also Figure 2 , Figure 3 , Figure 4 , respectively, are the current-voltage curves of the planar photoelectric synaptic memristor prepared in Example 1 under different voltages. The device can gradually increase the current level under 1.5V voltage scanning, and gradually decrease the current level under 0.2V voltage scanning. The current level can gradually increase under 0.6V voltage scanning, and can achieve excellent memristor performance under a relatively low voltage. Under white light conditions, the current level gradually increases, reflecting the performance of light enhancement, and Figure 2 It measures 80 circles in medium darkness and 60 circles in bright light, demonstrating excellent stability.

[0050] See also Figure 5 , which is the long-term potentiation-long-term depression of the planar photoelectric synaptic memristor prepared in Example 1. The conductance increases at a voltage of 1.5 V and decreases at a voltage of 0.5 V, reflecting the performance of the device's single-stage regulation.

[0051] See also Figure 6 , Figure 7 , respectively, are the changes in relaxation current of the planar photoelectric synaptic memristor prepared in Example 1 under different light intensities and pulse numbers. By changing the light intensity and the number of pulses, the relaxation current of the device can be significantly improved, which means that the device realizes the process from short-term memory to long-term memory.

[0052] See also Figure 8 , is the change of current level of the planar photoelectric synaptic memristor prepared in Example 1 under different pulse numbers and pulse intervals. With the increase of light intensity, the change of current level under the same number of pulses is more obvious, and with the increase of pulse interval, the change of current level under the same light intensity gradually decreases. The device can simulate excellent synaptic plasticity.

[0053] See also Fig. 9 , which is the learning-forgetting-relearning of the planar photoelectric synaptic memristor prepared in Example 1, after a period of forgetting after the first stimulation, only 6 pulses are needed to restore the first current level, reflecting that the device can simulate the learning and memory ability of the human brain.

[0054] See also Fig.10 , 11 12. The conductivity change of the planar photoelectric synaptic memristor prepared in Example 1 at different wavelengths. By changing the number and duration of pulses, the device can switch from short-term plasticity to long-term plasticity, and the change of device current value at different wavelengths is different, indicating that the device can achieve different conductivity ranges at different wavelengths.

[0055] See also Fig.13 , 1415, are different linearities of the planar photoelectric synaptic memristor prepared in Example 1. By changing the light intensity, the linearity of the device will change differently. By changing the pulse interval, the conductivity range of the device linearity will decrease as the interval increases. This shows that the device can be regulated to obtain a linearity of a different conductivity range, providing a higher accuracy for neural network learning.

[0056] In summary, the present invention provides a planar low-operating-voltage photoelectric synaptic memristor and a preparation method thereof. The basic characteristics of the photosynapse can be simulated at a relatively low operating voltage, different conductance ranges can be achieved through different wavelengths, and better linearity can be achieved by adjusting the light intensity and pulse interval at a specific wavelength. The planar structure of the device is easy to design, the process operation is simple, and the light receiving area can be maximized, which has universal applicability.

[0057] The present invention provides a planar low-operating-voltage photoelectric synaptic memristor and a method for preparing the same. There are many methods and approaches to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be considered as the scope of protection of the present invention. All components not specified in this embodiment can be implemented using existing technologies.

Claims

1. A planar low operating voltage opto-synaptic memristor, characterized in that: It comprises a bottom substrate and an insulating layer, a functional layer and a top electrode which are sequentially arranged on the bottom substrate; wherein the bottom substrate is silicon, the insulating layer is silicon dioxide, the functional layer is phthalocyanine copper, and the top electrode is silver.

2. The memristor according to claim 1, characterized in that The thickness of the insulating layer is 40-60 nm.

3. The memristor according to claim 1, characterized in that The thickness of the functional layer is 30-50 nm.

4. The memristor according to claim 1, characterized in that The thickness of the top electrode is 30-40 nm.

5. The memristor according to claim 1, characterized in that: The memristor is a planar structure, and the width of the middle channel of the memristor is 5 μm.

6. A method for preparing a planar low operating voltage photoelectric synaptic memristor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. Growing a silicon dioxide insulating layer on a silicon substrate, cleaning and drying; S2. Cover the sample treated in S1 with a planar mask and evacuate the chamber until the pressure inside the chamber is less than 5×10 -4 Pa, vacuum-deposit a phthalocyanine copper functional layer, and cool to room temperature while maintaining the vacuum state; S3. After the sample treated in S2 is cooled, vacuum the chamber until the pressure inside the chamber is less than 5×10 -4 Pa, and then vacuum evaporate silver electrodes, and keep the vacuum state and cool to room temperature to obtain the planar-based low operating voltage photoelectric synaptic memristor.

7. The preparation method according to claim 6, characterized in that: In S1, the cleaning process is ultrasonic cleaning with acetone, ethanol and deionized water in sequence for 30 minutes; the drying process is drying with nitrogen and then keeping warm at 120° C. for 60 minutes.

8. The preparation method according to claim 6, characterized in that: In S2, the specific conditions of vacuum evaporation are as follows: The evaporation thickness is 30 to 50 nm.

9. The preparation method according to claim 6, characterized in that: In S3, the specific conditions of vacuum evaporation are as follows: The evaporation thickness is 30 to 40 nm.

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