Phase change material structure thin film, phase change storage unit and preparation method of phase change material structure thin film

Abstract

The invention discloses a phase change material structure film, a phase change storage unit and a preparation method thereof, and relates to the technical field of semiconductor devices. The phase variation substance structure thin film comprises n information storage layers and n synergistic stable layers which are alternately stacked, and n is a positive integer; the information storage layer comprises A < 100-x > Tex, A is one of B, C, Si and Sc, and x is larger than or equal to 75 and smaller than 100; the synergistic stable layer comprises crystalline MTe2, and M is one of Mo, W and Pt. According to the invention, the synergistic stable layer has a relatively large band gap width and relatively high resistance, so that the power consumption of the phase change memory unit can be reduced; the information storage layer can realize nonvolatile information storage and has more than five times of high-low resistance value difference; a phase variation structure formed by the synergistic stable layer and the information storage layer can limit three-dimensional phase change into two-dimensional phase change, component segregation can be restrained, resistance drift and resistance value noise are reduced, the cycle service life of the device is prolonged, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a phase change structure film, a phase change storage unit and a preparation method thereof. Background Art

[0002] Non-volatile memory stands out in the memory field due to its advantages of keeping data intact after power failure and quickly erasing and writing data. Among them, phase change memory (PCM) is one of the more mature non-volatile memories. Phase change memory can achieve reversible transformation between the Set state (low resistance) and the Reset state (high resistance) under the action of external pulses, and the high and low resistance values ​​store "0" and "1" respectively.

[0003] Although phase change memory has the advantages of high speed and non-volatility, its power consumption has always been a key factor limiting its widespread application. During the reset process, the phase change material requires a large amount of energy for melting and quenching, resulting in high power consumption of the device. Researchers have been exploring ways to reduce the power consumption of phase change memory. On the one hand, the heating efficiency of the device is improved by using a flexible substrate with low thermal conductivity, but this has certain limitations in practical applications; on the other hand, the power consumption of the device is reduced by reducing the contact area between the bottom electrode and the phase change heterostructure, but too small a process node will increase the difficulty of preparation and increase the cost.

[0004] In addition, although phase-change memory is expected to achieve storage and computing integration and has great potential in brain-like computing, the phase-change memory based on the traditional phase-change material Ge2Sb2Te5 (GST for short) has considerable resistance noise and resistance drift, which affects the consistency of the device, and the large differences within and between device units pose challenges to its application in neurons. Summary of the invention

[0005] Based on the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a phase change heterogeneous structure film, a phase change memory unit and a preparation method thereof, aiming to solve the problem that the existing phase change materials require high energy to achieve reversible transformation, which in turn leads to high power consumption of phase change memory or phase change memory unit.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect of the present invention, a phase-variable structure film is provided, wherein the phase-variable structure film comprises n information storage layers and n synergistic stabilization layers, wherein the n information storage layers and the n synergistic stabilization layers are alternately stacked, and n is a positive integer;

[0008] The information storage layer includes A 100-x Te x, wherein A is one of B, C, Si and Sc, 75≤x<100;

[0009] The synergistic stabilization layer includes crystalline MTe2, wherein M is one of Mo, W and Pt.

[0010] Optionally, 1≤n≤8.

[0011] Optionally, 4≤n≤8, and the total thickness of the phase-variant structure film is greater than or equal to 20 nm and less than or equal to 40 nm.

[0012] Optionally, the information storage layer has a thickness of 4-9 nm.

[0013] A second aspect of the present invention provides a phase change memory unit, wherein the phase change memory unit comprises a bottom electrode, a phase change structure film and a top electrode stacked in sequence, wherein the phase change structure film is the phase change structure film of the present invention as described above.

[0014] Optionally, the phase change memory unit further comprises a dielectric coating layer, wherein the dielectric coating layer is coated on the side surface of the whole structure composed of the phase change heterostructure film and the top electrode stacked in sequence;

[0015] In the phase-variant structure film, the first information storage layer is arranged in contact with the bottom electrode, and the nth synergistic stabilization layer is arranged in contact with the top electrode.

[0016] Optionally, the material of the top electrode includes at least one of Al, W and TiN, and the thickness of the top electrode is 100-200 nm; the material of the bottom electrode includes at least one of Al, W and TiN, and the thickness of the bottom electrode is 100-200 nm.

[0017] Optionally, the material of the dielectric coating layer includes at least one of SiO2 and Si3N4.

[0018] A third aspect of the present invention provides a method for preparing a phase change memory unit, comprising the following steps:

[0019] providing a bottom electrode;

[0020] forming a phase-variable structure film on the bottom electrode, wherein the phase-variable structure film is the phase-variable structure film described above in the present invention;

[0021] After forming a top electrode on the phase change structure film, the phase change memory unit is obtained.

[0022] Optionally, the step of forming a phase-variant structure thin film on the bottom electrode specifically includes:

[0023] N information storage layers and n synergistic stabilization layers are alternately deposited on the bottom electrode to obtain the phase-variant structure film.

[0024] Beneficial effect: The synergistic stabilization layer of the present invention includes crystalline MTe2, which has a large band gap width and thus has a high resistance, thereby being able to reduce the power consumption of the phase change memory unit; the information storage layer includes A 100-x Te x It can realize non-volatile information storage under the action of appropriate electric pulses, and has a high and low resistance difference of more than 5 times, effectively storing logical information "0" and "1"; the phase change structure composed of the synergistic stabilization layer and the information storage layer can limit the three-dimensional phase change to a two-dimensional phase change, which helps to inhibit component segregation, thereby reducing resistance drift and resistance value noise, and improving the cycle life and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the structure of a T-type phase change memory unit in an embodiment.

[0026] Figure 2 Schematic diagram of the structure of a confined structure phase change memory unit in an embodiment of the present invention.

[0027] Figure 3 This is a resistance-voltage performance curve of the phase change memory cell in comparative example 1.

[0028] Figure 4 This is a resistance-voltage performance curve of the phase change memory cell in Example 1.

[0029] Figure 5 This is a resistance-voltage performance curve of the phase change memory cell in Example 2.

[0030] Figure 6 This is a resistance-voltage performance curve of the phase change memory cell in Example 3.

[0031] Figure 7 This is a resistance-voltage performance curve of the phase change memory cell in Example 4. DETAILED DESCRIPTION

[0032] The present invention provides a phase change structure film, a phase change memory unit and a preparation method thereof. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0033] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0034] An embodiment of the present invention provides a phase-variable structure film, wherein the phase-variable structure film comprises n information storage layers and n synergistic stabilization layers, wherein the n information storage layers and the n synergistic stabilization layers are alternately stacked, and n is a positive integer;

[0035] The information storage layer includes A 100-x Te x , wherein A is one of B (boron), C (carbon), Si (silicon) and Sc (scandium), 75≤x<100 (for example, x is 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98 or 99, etc.);

[0036] The synergistic stabilization layer includes crystalline MTe2 (specifically, crystalline MTe2 with a 1T or 2H structure), wherein M is one of Mo (molybdenum), W (tungsten) and Pt (platinum).

[0037] In the embodiment of the present invention, the phase-variation structure film comprises an information storage layer and a synergistic stabilization layer, wherein the information storage layer comprises A 100-x Te x It can realize non-volatile reversible transformation, realize non-volatile information storage under the action of appropriate electric pulses, effectively store logical information "0" and "1", and improve storage speed, and has a high and low resistance difference of more than 5 times. The energy required for the low-resistance information storage layer to transform into a high-resistance state is small, which is conducive to reducing the power consumption of the phase change storage unit. Specifically, although the information storage layer also realizes the transformation of high and low resistance under the action of external electrical signals, its internal structure is different from that of the traditional material GST. Specifically, when the information storage layer is in a high-resistance state, the phase change active area is mainly amorphous, but there are still some nano-scale grains inside. These nano-scale grains help to induce crystallization of the amorphous area, increase the crystallization speed and thus increase the storage speed; on the other hand, when the low-resistance information storage layer is transformed into a high-resistance state, only part of the crystalline area needs to be transformed into an amorphous state, so the required energy is small, which is conducive to reducing the power consumption of the phase change storage unit.

[0038] The synergistic stabilization layer in the embodiment of the present invention includes crystalline MTe2 of 1T or 2H structure, which maintains structural stability during information storage, and crystalline MTe2 has a large band gap width, so the resistance is high, which helps to improve the overall film resistance, and the required external supply current is small, which helps to reduce the power consumption of the device. In addition, the synergistic stabilization layer also helps the device to obtain excellent performance in terms of drift, noise, fatigue life, etc.

[0039] In addition, the phase heterogeneous structure formed by the synergistic stabilization layer and the information storage layer can limit the three-dimensional phase change to a two-dimensional phase change, which helps to suppress component segregation, thereby reducing resistance drift and resistance value noise, improving the cycle life, reliability, consistency and accuracy of the device, and providing the possibility for realizing neuron computing. In an embodiment of the present invention, the synergistic stabilization layer combined with the information storage layer can obtain a universal non-volatile storage unit.

[0040] In some embodiments, 1≤n≤8, for example, n is 1, 2, 3, 4, 5, 6, 7 or 8, etc. In some specific embodiments, 4≤n≤8.

[0041] In some embodiments, the total thickness of the phase-variant structure thin film is greater than or equal to 20 nm and less than or equal to 40 nm, for example, it may be 20 nm, 25 nm, 30 nm, 35 nm or 40 nm.

[0042] In some embodiments, the information storage layer has a thickness of 4 to 9 nm, for example, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm or 9 nm.

[0043] In some embodiments, the thickness of the synergistic stabilization layer is 0.5-0.8 nm. In some specific embodiments, the synergistic stabilization layer is a single layer of crystalline MTe2 with a 1T or 2H structure (crystalline MTe2 is a two-dimensional material, and a single layer of crystalline MTe2 is a Te-M-Te three-layer atomic structure, and the thickness is the thinnest at this time). In this way, the synergistic stabilization layer has a higher resistance.

[0044] An embodiment of the present invention further provides a phase change memory unit, wherein: Figure 1 and Figure 2 As shown, the phase change memory unit comprises a bottom electrode 11, a phase change structure film 12 and a top electrode 13 which are sequentially stacked, wherein the phase change structure film 12 comprises n information storage layers 121 and n synergistic stabilization layers 122 which are alternately stacked, the first information storage layer is arranged in contact with the bottom electrode 11, and the nth synergistic stabilization layer is arranged in contact with the top electrode 13;

[0045] The phase change memory unit further comprises a dielectric coating layer 14 , which is coated on the side surface of the whole composed of the phase change structure thin film 12 and the top electrode 13 which are stacked in sequence.

[0046] In this embodiment, the phase change memory unit has the advantages of high speed, low power consumption, high precision, and high fatigue cycle life. On the one hand, the information storage layer has a high and low resistance difference of more than 50 times, and can clearly store data; on the other hand, the crystalline MTe2 has a large band gap, exhibits semiconductor characteristics, has a high resistance, can effectively reduce the current passing through the device, and reduce power consumption. In addition, the use of phase change heterostructure film can effectively limit resistance drift and resistance value noise, improve the consistency of the device, and provide the possibility of realizing neuron computing.

[0047] In this embodiment, the phase change memory cell includes two structures, one is a T-type structure (such as Figure 1 ), and the other is a restricted structure (such as Figure 2 As shown). In the T-type structure, the area of ​​the phase-variable structure film and the top electrode is larger than the area of ​​the bottom electrode, that is, the horizontal projection of the phase-variable structure film and the top electrode covers the horizontal projection of the bottom electrode. In the restricted structure, the area of ​​the phase-variable structure film and the top electrode is equal to the area of ​​the bottom electrode, that is, the horizontal projection of the phase-variable structure film and the top electrode coincides with the horizontal projection of the bottom electrode.

[0048] In some embodiments, the total thickness of the phase-variant structure thin film is greater than or equal to 20 nm and less than or equal to 40 nm, and the thickness of the information storage layer is 4 to 9 nm.

[0049] The bottom electrode of the phase change memory unit selected in this embodiment can be prepared based on the 28nm semiconductor process node, and its maximum diameter is about 40nm. When the phase change structure film is reversibly transformed, a mushroom-shaped hemispherical region is usually formed above the bottom electrode. The radius of this region is about twice the radius of the bottom electrode, so the maximum height of this region is about 40nm. When the phase change structure film exceeds 40nm, the excess part does not participate in the phase change process. In order to save costs, the total thickness of the phase change structure film is less than or equal to 40nm. Furthermore, the total thickness of the phase change structure film is less than or equal to 40nm and greater than or equal to 20nm.

[0050] In some embodiments, the material of the top electrode includes at least one of Al, W and TiN, but is not limited thereto; the thickness of the top electrode is 100 to 200 nm, for example, it can be 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm, etc.

[0051] In some embodiments, the material of the bottom electrode includes at least one of Al, W and TiN, but is not limited thereto; the thickness of the bottom electrode is 100 to 200 nm, for example, it can be 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm, etc.

[0052] In some embodiments, the material of the dielectric coating layer includes at least one of SiO2 and Si3N4, but is not limited thereto.

[0053] The embodiment of the present invention further provides a method for preparing a phase change memory unit, which comprises the steps of:

[0054] S1, providing a bottom electrode;

[0055] S2, forming a phase-change structure film on the bottom electrode, wherein the phase-change structure film is the phase-change structure film as described above in the embodiment of the present invention;

[0056] S3, after forming a top electrode on the phase change structure film, forming a phase change structure film to obtain the phase change memory unit.

[0057] In step S1, the material of the bottom electrode is as described above and will not be described again here.

[0058] In step S2, in some embodiments, the steps on the bottom electrode specifically include:

[0059] N information storage layers and n synergistic stabilization layers are alternately deposited on the bottom electrode to obtain the phase-variant structure film.

[0060] In some embodiments, the deposition method includes one of physical vapor deposition and chemical vapor deposition.

[0061] Taking the sputtering method as an example, the step of forming a phase-variant structure thin film on the bottom electrode specifically includes:

[0062] S21, co-sputtering target A (specifically one of target B, target C, Si target and Sc target) and target Te to form an information storage layer on the bottom electrode;

[0063] S22, co-sputtering an M target (specifically one of a Mo target, a W target and a Pt target) and a Te target to form a synergistic stabilization layer on the information storage layer;

[0064] S23, repeating step S21 to step S22 several times (ie, n times) until n information storage layers and n synergistic stabilization layers are obtained.

[0065] In step S3, before forming the top electrode, a TiN adhesion electrode may be first grown on the phase-shifting structure film to increase adhesion between the top electrode and the phase-shifting structure film.

[0066] An embodiment of the present invention further provides a phase change memory, which includes a plurality of phase change memory units as described above in the embodiment of the present invention.

[0067] The present invention will be further described below by means of specific examples.

[0068] Example 1

[0069] This embodiment provides a T-type phase change memory cell, such as Figure 1 As shown, it includes a substrate 10 with a through hole and a bottom electrode 11 arranged in the through hole; it also includes a phase change structure film 12, a TiN adhesion electrode ( Figure 1 The invention also includes a dielectric coating layer 14, which is coated on the side of the whole composed of the phase-variable structure film 12, the TiN adhesion electrode and the top electrode 13. The area of ​​the bottom electrode is smaller than that of the phase-variable structure film, and the projection of the bottom electrode on the phase-variable structure film is located at the center of the phase-variable structure film, and the projection of the top electrode on the phase-variable structure film coincides with the phase-variable structure film.

[0070] Among them, the material of the bottom electrode is W, the bottom electrode is cylindrical, the diameter is 40nm, and the thickness is 100nm; the material of the top electrode is Al, the top electrode is cylindrical, the diameter is 200nm, and the thickness is 100nm; the TiN adhesion electrode is cylindrical, the diameter is 200nm, and the thickness is 10nm;

[0071] The phase-variant structure film 12 is cylindrical, with a diameter of 200 nm, and is composed of four information storage layers 121 and four synergistic stabilization layers 122 alternately stacked, the first information storage layer 121 is arranged in contact with the bottom electrode 11, and the fourth synergistic stabilization layer 122 is arranged in contact with the top electrode 13; the material of each information storage layer is C 10 Te 90 , with a thickness of 9nm; the material of each synergistic stabilization layer is crystalline WTe2, with a thickness of 0.7nm;

[0072] The material of the dielectric coating layer 14 is Si3N4, and the thickness thereof is the sum of the thickness of the phase heterostructure film, the TiN adhesion electrode and the top electrode.

[0073] This embodiment also provides a method for preparing the above-mentioned T-shaped phase change memory unit, comprising the following steps:

[0074] (1) A substrate 10 having a bottom electrode 11 is provided (the substrate has a through hole, the bottom electrode is arranged in the through hole, and the substrate is a silicon oxide substrate). Before the subsequent process, the silicon oxide substrate is first cleaned to remove organic matter, metal ions, oxides and other impurities on the surface of the silicon oxide substrate, which is beneficial to improve the stability of the device. The bottom electrode 11 is a tungsten electrode, which is cylindrical, has a diameter of 40nm and a thickness of 100nm.

[0075] (2) A Si3N4 layer with a thickness of 148.8 nm is deposited on the surface of the silicon oxide substrate. Then, the Si3N4 layer is etched by an exposure-etching process until a deposition hole exposing the bottom electrode 11 is formed in the Si3N4 layer, thereby forming a dielectric coating layer 14 with a deposition hole. The exposure method used in the exposure-etching process is electron beam exposure, and the etching method is reactive ion etching; the deposition hole is coaxial with the bottom electrode 11, and the aperture of the deposition hole is 200 nm.

[0076] (3) Through magnetron sputtering, the background vacuum of magnetron sputtering is 3×10 -4 Pa, a C target (power of 40 W) and a Te target (power of 10 W) are co-sputtered on the bottom electrode 11 at a temperature of 300°C to form a C layer with a thickness of 9 nm. 10 Te 90 layer, namely the information storage layer 121; then, a W target (power is 60 W) and a Te target (power is 10 W) are used simultaneously on the information storage layer to perform co-sputtering to form a WTe2 layer with a thickness of 0.7 nm, namely the synergistic stabilization layer 122.

[0077] (4) Repeat step (3) to alternately sputter to form information storage layers and synergistic stabilization layers until four information storage layers and four synergistic stabilization layers are formed.

[0078] (5) After cooling, a TiN adhesion electrode (with a thickness of 10 nm) is first grown on the phase change heterostructure film, and then a 100 nm thick Al layer is deposited on the TiN adhesion electrode and in the deposition holes of the dielectric coating layer by chemical vapor deposition to form a top electrode 13, thereby obtaining the phase change memory unit.

[0079] Example 2

[0080] This embodiment provides a phase change memory cell with a restricted structure, such as Figure 2 As shown, it includes a substrate 10 with a through hole and a bottom electrode 11 arranged in the through hole; and also includes a phase change structure film 12 and a TiN adhesion electrode ( Figure 2The invention also includes a dielectric coating layer 14, which is coated on the side of the whole composed of the phase-variable structure film 12, the TiN adhesion electrode and the top electrode 13. The area of ​​the bottom electrode is equal to the area of ​​the phase-variable structure film, the area of ​​the top electrode is equal to the area of ​​the top electrode, and the projection of the bottom electrode on the phase-variable structure film coincides with the phase-variable structure film, and the projection of the top electrode on the phase-variable structure film coincides with the phase-variable structure film.

[0081] Among them, the material of the bottom electrode is W, the bottom electrode is cylindrical, the diameter is 40nm, and the thickness is 100nm; the material of the top electrode is Al, the top electrode is cylindrical, the diameter is 40nm, and the thickness is 100nm; the TiN adhesion electrode is cylindrical, the diameter is 200nm, and the thickness is 10nm;

[0082] The phase-variation structure film 12 is cylindrical, with a diameter of 40 nm, and is composed of four information storage layers 121 and four synergistic stabilization layers 122 alternately stacked, the first information storage layer 121 is arranged in contact with the bottom electrode 11, and the fourth synergistic stabilization layer 122 is arranged in contact with the top electrode 13; the material of each information storage layer is B 15 Te 85 , with a thickness of 9nm; the material of each synergistic stabilization layer is crystalline WTe2, with a thickness of 0.7nm.

[0083] The material of the dielectric coating layer 14 is Si3N4, and the thickness thereof is the sum of the thickness of the phase heterostructure film, the TiN adhesion electrode and the top electrode.

[0084] This embodiment also provides a method for preparing the above-mentioned phase change memory unit with a restricted structure, comprising the following steps:

[0085] (1) A substrate 10 having a bottom electrode 11 is provided (the substrate has a through hole, the bottom electrode is arranged in the through hole, and the substrate is a silicon oxide substrate). Before the subsequent process, the silicon oxide substrate is first cleaned to remove organic matter, metal ions, oxides and other impurities on the surface of the silicon oxide substrate, which is beneficial to improve the stability of the device. The bottom electrode 11 is a tungsten electrode, which is cylindrical, has a diameter of 40nm and a thickness of 100nm.

[0086] (2) A Si3N4 layer with a thickness of 148.8 nm is deposited on the surface of the silicon oxide substrate. Then, the Si3N4 layer is etched by an exposure-etching process until a deposition hole exposing the bottom electrode 11 is formed in the Si3N4 layer, thereby forming a dielectric coating layer 14 with a deposition hole. The exposure method used in the exposure-etching process is electron beam exposure, and the etching method is reactive ion etching; the deposition hole is coaxial with the bottom electrode 11, and the aperture of the deposition hole is 40 nm.

[0087] (3) Through magnetron sputtering, the background vacuum of magnetron sputtering is 3×10 -4 Pa, at a temperature of 300°C, a B target (power of 50W) and a Te target (power of 10W) ​​are co-sputtered on the bottom electrode 11 to form a B layer with a thickness of 9nm. 15 Te 85 layer, namely the information storage layer 121; then, a W target (power is 60 W) and a Te target (power is 10 W) are used simultaneously on the information storage layer to perform co-sputtering to form WTe2 with a thickness of 0.7 nm, namely the synergistic stabilization layer 122.

[0088] (4) Repeat step (3) to alternately sputter to form information storage layers and synergistic stabilization layers until four information storage layers and four synergistic stabilization layers are formed.

[0089] (5) After cooling, a TiN adhesion electrode (with a thickness of 10 nm) is first grown on the phase change heterostructure film, and then a 100 nm thick Al layer is deposited on the TiN adhesion electrode and in the deposition holes of the dielectric coating layer by chemical vapor deposition to form a top electrode 13, thereby obtaining the phase change memory unit.

[0090] Example 3

[0091] This embodiment provides a T-type phase change memory cell, which is different from the first embodiment only in that the material of each information storage layer is Si 20 Te 80 The materials of the synergistic stabilization layer are all crystalline MoTe2.

[0092] This embodiment also provides a method for preparing the T-type phase change memory cell, which differs from the embodiment 1 only in that:

[0093] In step (3), the magnetron sputtering method is used, and the background vacuum of the magnetron sputtering is 3×10 -4 Pa, at a temperature of 300°C, a Si target (power of 40W) and a Te target (power of 10W) ​​are co-sputtered on the bottom electrode 11 to form a Si layer with a thickness of 9nm. 20 Te 80 layer, namely the information storage layer 121; then, a Mo target (power is 60 W) and a Te target (power is 10 W) are used simultaneously on the information storage layer to perform co-sputtering to form a MoTe2 layer with a thickness of 0.7 nm, namely the synergistic stabilization layer 122.

[0094] Example 4

[0095] This embodiment provides a T-type phase change memory cell, which is different from the first embodiment only in that the material of each information storage layer is Sc 25 Te75 The material of the synergistic stabilization layer is crystalline PtTe2.

[0096] This embodiment also provides a method for preparing the T-type phase change memory unit, which differs from the first embodiment only in that:

[0097] In step (2), a Si3N4 layer with a thickness of 148 nm is deposited on the surface of the silicon oxide substrate.

[0098] In step (3), the magnetron sputtering method is used, and the background vacuum of the magnetron sputtering is 3×10 -4 Pa, at a temperature of 300°C, a Sc target (power of 40 W) and a Te target (power of 10 W) are co-sputtered on the bottom electrode 11 to form a Sc layer with a thickness of 9 nm. 25 Te 75 layer, namely the information storage layer 121; then a Pt target (power is 60 W) and a Te target (power is 10 W) are used simultaneously on the information storage layer to perform co-sputtering to form a PtTe2 layer with a thickness of 0.5 nm, namely the synergistic stabilization layer 122.

[0099] Comparative Example 1

[0100] This comparative example provides a T-shaped phase change memory unit and a preparation method thereof, which is different from Example 1 only in that the phase change structure thin film layer in Example 1 is replaced by a GST material layer.

[0101] The phase change memory cells in Examples 1 to 4 and Comparative Example 1 were tested for resistance-voltage characteristics.

[0102] The resistance-voltage characteristic curves of the phase change memory unit in comparative example 1 under the action of pulses with different pulse widths are as follows: Figure 3 As shown. The device is initially in a high-resistance state. When a pulse that can achieve a reversible phase transition is applied, as the pulse amplitude increases, the SET (set) operation is first implemented, that is, the resistance changes from a high-resistance state to a low-resistance state. As the pulse amplitude further increases, the device implements a RESET (reset) operation, that is, the resistance changes from a low-resistance state to a high-resistance state. Generally speaking, as the pulse width decreases, the SET and RESET voltages of the device increase. However, if the pulse width is too small, the device will not be able to achieve SET / RESET reversible operations. Figure 3 It can be seen that the resistance value of the phase change memory cell in Comparative Example 1 is 10 4 ~10 6 A reversible transformation occurs between Ω.

[0103] The resistance-voltage characteristic curves of the phase change memory unit in Example 1 under the action of pulses with different pulse widths are shown in FIG. Figure 4 As shown. Figure 4It can be seen that the resistance of the phase change memory cell in Example 1 is 10 8 ~10 9 A reversible transformation occurs between Ω. Figure 3 It can be inferred that the phase change memory unit in Example 1 has higher high and low resistance values ​​under the action of pulses with the same pulse width, which can reduce the power consumption of the phase change memory unit.

[0104] The resistance-voltage characteristic curves of the phase change memory unit in Example 2 under the action of pulses with different pulse widths are as follows: Figure 5 As shown by Figure 5 It can be seen that the resistance of the phase change memory cell in Example 2 is 10 8 ~10 9 A reversible transformation occurs between Ω. Figure 3 It can be inferred that the phase change memory unit in Example 2 has higher high and low resistance values ​​under the action of pulses with the same pulse width, which can reduce the power consumption of the phase change memory unit.

[0105] The resistance-voltage characteristic curves of the phase change memory unit in Example 3 under the action of pulses with different pulse widths are shown in FIG. Figure 6 As shown by Figure 6 It can be seen that the resistance of the phase change memory cell in Example 3 is 10 7 ~10 9 A reversible transformation occurs between Ω. Figure 3 It can be inferred that the phase change memory unit in Example 3 has higher high and low resistance values ​​under the action of pulses with the same pulse width, which can reduce the power consumption of the phase change memory unit.

[0106] The resistance-voltage characteristic curves of the phase change memory unit in Example 4 under the action of pulses with different pulse widths are shown in FIG. Figure 7 As shown by Figure 7 It can be seen that the resistance of the phase change memory cell in Example 4 is 10 7 ~10 8 A reversible transformation occurs between Ω. Figure 3 It can be inferred that the phase change memory unit in Example 4 has higher high and low resistance values ​​under the action of pulses with the same pulse width, which can reduce the power consumption of the phase change memory unit.

[0107] In summary, the present invention provides a phase change heterogeneous structure film, a phase change memory unit and a preparation method thereof. The phase change heterogeneous structure film can clearly store data while reducing the power consumption required for phase change of the device, reducing resistance value noise, reducing resistance drift, and improving device consistency, thereby ensuring that the phase change memory unit obtains the excellent performance of high speed, low power consumption, high precision, and high fatigue cycle life, and also provides a possibility for the realization of neuron computing.

[0108] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A phase-change structure thin film, characterized in that: The phase-variant structure film comprises n information storage layers and n synergistic stabilization layers, wherein the n information storage layers and the n synergistic stabilization layers are alternately stacked, and n is a positive integer; The information storage layer includes A 100-x Te x , wherein A is one of B, C, Si and Sc, 75≤x<100; The synergistic stabilization layer includes crystalline MTe2, wherein M is one of Mo, W and Pt.

2. The phase-variant structure thin film according to claim 1, characterized in that: 1≤n≤8。 3. The phase-variant structure thin film according to claim 2, characterized in that: 4≤n≤8, the total thickness of the phase-variant structure film is greater than or equal to 20 nm and less than or equal to 40 nm.

4. The phase-variant structure thin film according to claim 3, characterized in that: The information storage layer has a thickness of 4-9 nm.

5. A phase change memory cell, characterized in that: The phase change memory unit comprises a bottom electrode, a phase change structure film and a top electrode which are stacked in sequence, wherein the phase change structure film is the phase change structure film according to any one of claims 1 to 4.

6. The phase change memory cell according to claim 5, characterized in that: The phase change memory unit further comprises a dielectric coating layer, wherein the dielectric coating layer is coated on the side surface of the whole body composed of the phase change heterostructure film and the top electrode stacked in sequence; In the phase-variant structure film, the first information storage layer is arranged in contact with the bottom electrode, and the nth synergistic stabilization layer is arranged in contact with the top electrode.

7. The phase change memory cell according to claim 5, characterized in that: The material of the top electrode includes at least one of Al, W and TiN, and the thickness of the top electrode is 100-200 nm; the material of the bottom electrode includes at least one of Al, W and TiN, and the thickness of the bottom electrode is 100-200 nm.

8. The phase change memory cell according to claim 6, characterized in that: The material of the dielectric coating layer includes at least one of SiO2 and Si3N4.

9. A method for preparing a phase change memory unit, characterized in that: The steps include: providing a bottom electrode; forming a phase change structure film on the bottom electrode, wherein the phase change structure film is the phase change structure film according to any one of claims 1 to 4; After forming a top electrode on the phase change structure film, the phase change memory unit is obtained.

10. The preparation method according to claim 9, characterized in that: The step of forming a phase-variable structure thin film on the bottom electrode specifically includes: N information storage layers and n synergistic stabilization layers are alternately deposited on the bottom electrode to obtain the phase-variant structure film.

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