Network-on-chip architecture for handling different data sizes

Abstract

An integrated circuit (IC) includes a network-on-chip (NoC). The NoC comprises a plurality of NoC master circuits, a plurality of NoC slave circuits and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different modes of operation for forwarding the data based on the different widths.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits (ICs), and more particularly to a network-on-chip (NoC) architecture within an IC that is capable of handling different data sizes. Background Art

[0002] A network on chip (NoC) refers to a network-based communication subsystem implemented in an integrated circuit (IC). The NoC is capable of transmitting data between different data producer circuits and data consumer circuits implemented within the IC. The NoC is typically implemented in an IC using multiple interconnected router circuits (e.g., switches), each of which is capable of performing packet switching operations to move data between the data producer circuits and the data consumer circuits. Summary of the invention

[0003] In one or more exemplary implementations, an integrated circuit (IC) includes a network on chip (NoC). The NoC includes a plurality of NoC masters, a plurality of NoC slaves, and a plurality of switches. The plurality of switches interconnect and communicatively link the plurality of NoC masters with the plurality of NoC slaves. The plurality of switches are configured to receive data of different widths during operation and implement different operation modes for forwarding the data based on the different widths.

[0004] In one or more exemplary implementations, a method includes receiving data in a switch of the NoC. The method includes determining a width of the data using the switch. The method includes implementing a selected operating mode for processing the data based on the width using the switch. The selected operating mode is selected from a plurality of different operating modes. The method includes transmitting the data via the switch using the selected operating mode.

[0005] This summary is provided only to introduce certain concepts and is not intended to identify any key or essential features of the claimed subject matter. Other features of the arrangements of the present invention will be apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The arrangement of the present invention is shown by way of example in the accompanying drawings. However, the accompanying drawings should not be interpreted as limiting the arrangement of the present invention to only the specific implementation shown. Various aspects and advantages will become apparent when viewing the following detailed description and when referring to the accompanying drawings.

[0007] Figure 1 An example of a network on chip (NoC) that may be implemented within an integrated circuit (IC) is illustrated.

[0008] Figure 2 Examples of deadlock conditions that may occur in conventional NoCs are illustrated.

[0009] Figure 3 An exemplary implementation of a switch of a NoC arranged in accordance with the invention described herein is illustrated.

[0010] Figure 4 Another exemplary implementation of a switch of a NoC arranged in accordance with the invention described herein is illustrated.

[0011] Figure 5 Another exemplary implementation of a switch of a NoC arranged in accordance with the invention described herein is illustrated.

[0012] Figure 6 Certain operational features of a mask circuit included in a switch of a NoC arranged in accordance with the invention described herein are illustrated.

[0013] Figure 7 An example of connectivity of a mask circuit arranged in accordance with the invention described herein relative to an arbiter in a switch of a NoC is illustrated.

[0014] Figure 8 Another exemplary implementation of a switch of a NoC arranged in accordance with the invention described herein is illustrated.

[0015] Fig. 9 Another exemplary implementation of a NoC is illustrated.

[0016] Fig.10 Another exemplary implementation of a NoC is illustrated.

[0017] Fig.11 An exemplary method of processing data using a switch of a NoC as described within this disclosure is illustrated.

[0018] Fig.12 An exemplary architecture of an IC including a NoC arranged in accordance with the invention described herein is illustrated. DETAILED DESCRIPTION

[0019] The present disclosure relates to integrated circuits (ICs), and more particularly to network-on-chip (NoC) architectures within ICs that are capable of handling different data sizes. In one aspect, different data micro-slice sizes can be dynamically scaled during operation of the NoC. That is, the NoC is capable of concurrently handling and routing data of different sizes during operation (e.g., in real time). A "micro-slice" of data refers to a flow control unit, which is a link-level atomic piece of information. For example, a packet is formed of multiple micro-slices. Data micro-slices are typically transmitted as multiple parallel (e.g., synchronous) bits.

[0020] A NoC is capable of transmitting data between data producer circuits and data consumer circuits in an IC. Within the present disclosure, the term "endpoint circuit" may be used to refer to a data producer circuit and / or a data consumer circuit. A NoC may be communicatively linked to various endpoint circuits through certain interface circuits through which data enters and leaves the NoC. These interface circuits are connected to a plurality of switch circuits. Generally speaking, data enters the NoC from a data producer circuit through a first interface circuit, is routed to a second interface (through which the data leaves the NoC) using a switch circuit, and is delivered from the second interface circuit to a data consumer circuit. In a conventional NoC, the connections between the interface circuits and the switch circuits and between the switch circuits themselves are typically fixed in width and therefore operate with a single predetermined data width.

[0021] As an example, a conventional NoC can be implemented with a data width of 128 bits. In this example, each interface circuit and switch circuit is configured to transport a portion of data called a "microchip". In order to traverse the NoC, each microchip is created to be the same size. That is, if the NoC is configured to operate with a width of 128 bits, the width of each microchip must be 128 bits. The NoC cannot transmit data microchips of different sizes. In the case where the width of the data microchip is different from the width supported by the NoC, the width of such microchip is converted to the width supported by the NoC through the interface circuit. For example, a 256-bit microchip will be converted into two 128-bit microchips. These two 128-bit microchips will traverse the NoC independently as two unrelated 128-bit microchips.

[0022] Some conventional NoCs are capable of transporting data microslices of two different widths. However, in such cases, the NoC bifurcates into different partitions, each of which is configured to transport data microslices of a specific width only. This means that data microslices of a first width stay within a first partition of the NoC that is configured to transport microslices of the first width, while data microslices of a second width stay within a second partition of the NoC that is configured to transport microslices of the second width. The only way that microslices can cross from one partition of the NoC to another is if the NoC includes data width conversion circuitry disposed between the two bifurcated partitions. In order for a microslice to move from one partition of the NoC to another, the microslice must be width converted.

[0023] According to the inventive configuration described herein, a NoC is disclosed that is capable of transmitting data including microchips of different widths. That is, the NoC includes a circuit node that is capable of automatically determining the width of a received microchip. In certain aspects, in response to determining the width of the microchip, the NoC circuit node is capable of dynamically adjusting to the detected width by implementing a specific operating mode suitable for the determined width of the microchip. The NoC circuit node is capable of forwarding the microchip forward to the next circuit node of the NoC. The NoC circuit node can dynamically change between different operating modes on a per-microchip basis, so that microchips of different sizes can be handled concurrently by the NoC without using width conversion circuits and / or bifurcations of the NoC. Therefore, any given open switch circuit of the NoC can handle data microchips of different sizes (e.g., widths).

[0024] In one or more other exemplary implementations, a switch of the NoC may include a configuration register that can be programmed to place certain ports of the switch into different operating modes. The particular operating mode in which a given port of the switch is located depends on the value programmed into the configuration register that controls the port and the width of the data to be processed or handled by the port. Whether the width of the microchip is determined by a tag or indicator included in the microchip itself or determined using a configuration register, it should be understood that the arrangement of the present invention contemplates a switch circuit having one or more ports that operate in a first operating mode for conveying microchips of a first size, while having one or more other ports of the switch that operate in a second operating mode for conveying microchips of a second and different size. Further aspects of the arrangement of the present invention are described below with reference to the accompanying drawings.

[0025] Figure 1 An example of a NoC 100 that can be implemented within an IC is illustrated. NoC 100 can convey data between endpoint circuits 102 (e.g., 102-1, 102-2, 102-3, and / or 102-4) and endpoint circuits 104 (e.g., 104-1, 104-2, 104-3, and / or 104-4). In this example, for purposes of illustration, endpoint circuit 102 may represent a data producer circuit, and endpoint circuit 104 may represent a data consumer circuit.

[0026] NoC 100 includes a plurality of NoC master circuits (NMCs) 106 (e.g., 106-1, 106-2, 106-3, and 106-4), a plurality of NoC slave circuits (NSCs) 108 (e.g., 108-1, 108-2, 108-3, and 108-4), and a plurality of switches 110 (e.g., 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, 110-9, 110-10, 110-11, and 110-12). In this example, NMCs 106 and NSCs 108 are examples of interface circuits through which data may enter and / or leave NoC 100. It will be apparent that each NMC 106 and each NSC 108 may be implemented as a bidirectional interface that allows data to enter and leave the NoC 100. In general, the NMC 106 is an example of an interface that can receive data from the endpoint circuit 102, while the NSC 108 is an example of an interface that can output data to the endpoint circuit 104. It will be apparent that each NMC 106 and each NSC 108 may be implemented as a bidirectional interface, thereby allowing the endpoint circuit 104 to respond to the endpoint circuit 102 (e.g., such that data can enter and leave the NoC 100 via each NMC 106 and / or NSC 108).

[0027] In this example, each switch 110 may be connected to adjacent circuits of the NoC 100 in the upper (north), left (west), right (east), and lower (south) directions, as long as such adjacent circuits exist in the NoC 100. For example, the switch 110-3 may receive data via any of the illustrated directions (e.g., from the NMC 106-2, the switch 110-2, the switch 110-9, and / or the switch 110-4) and route or forward the received data to a circuit in any of the other three directions.

[0028] In this example, each NMC 106, NSC 108, and switch 110 is capable of receiving data having a first width and data having a second, different width. In the case of switch 110, data of different widths may be received serially or concurrently by different ports of the switch. In other cases, data of a first width may be received by a given port of switch 110, followed by data of a second and different width being delivered to the same port and / or a different port of switch 110.

[0029] Generally, the NMC 106, NSC 108, and switch 110 are capable of operating in different operating modes. The operating mode implemented may be selected based on the size of the data received or to be processed. Figure 1In the example of , each different operating mode that can be implemented by NMC 106, NSC 108, and switch 110 can be associated with a specific data width. In one aspect, each switch 110 can dynamically (e.g., in real time) switch between these different operating modes during operation based on the size of the data slivers received by the corresponding circuit at any given time. This allows the architecture of NoC 100 to dynamically scale the sliver width of the channels of NoC 100 based on the requested data width and / or the bandwidth of the requesting circuit (e.g., endpoint circuit 102). Therefore, NoC 100 can support a variety of different sliver widths at full bandwidth.

[0030] Figure 1 The example of illustrates a specific implementation that supports multiple (e.g., two or more) different data widths conveyed concurrently at full bandwidth through the NoC 100. A given switch 110, for example, can convey data of a first width from a selected port of the switch while conveying data of a different width from a different port of the switch. Similarly, a given switch 110, for example, can convey data of a first width from a selected port of the switch and subsequently convey data of a different width from the same port of the switch. The NoC 100 can route mixed-mode data traffic (e.g., mixed in width) at full bandwidth.

[0031] In conventional NoC architectures that support data with fixed flits width, interfaces such as NMC and NSC width perform width conversion on any received data to ensure that the resulting data fits the fixed width of the NoC. In other conventional NoC architectures, a larger data flits may be forwarded concurrently as two smaller and independent data flits (e.g., a 256-bit flits is transmitted as two independent 128-bit flits). This means that two 128-bit flits (which are considered independent within a conventional NoC, as if from different packets) may not travel together through the NoC as a unified portion of data despite being part of the same data packet. This can lead to a deadlock condition where half of the data arrives before the other half.

[0032] Figure 2 An example of a deadlock condition that may occur in a conventional NoC that is capable of transmitting a larger data flit as two smaller data flit concurrently is illustrated. Figure 2In the example of FIG. 2 , NMC 206-1 forwards data microslices 222, 224, and 226 to NSC 208 through switch 210. Each of microslices 222, 224, and 226 is forwarded to NSC 208 as two smaller and independent data microslices corresponding to first portion A1 and second portion A2. That is, with respect to microslice 222, portion 222-A1 is forwarded as a first microslice that is half the size of microslice 222, and portion 222-A2 is forwarded as a second and independent microslice that is half the size of microslice 222. The same is true for each of microslices 224 and 226. NMC 206-2 forwards data microslices 228, 230, and 232 to NSC 208 through switch 210. Each of the flits 228, 230, and 232 is forwarded to the NSC 208 in the same manner as the NSC 206 as two smaller and separate data flits corresponding to the first portion B1 and the second portion B2. That is, with respect to the flits 228, the portion 228-B1 is forwarded as a first flits half the size of the flits 228, and the portion 228-B2 is forwarded as a second and separate flits half the size of the flits 228. The same is true for each of the flits 230, 232.

[0033] As shown, in some cases, due to the data routing priorities observed by switch 210, only the first portion A1 of flits 222, 224, and 226 arrives and the first portion B1 of flits 228, 230, and 232 arrives in NSC 208, thereby filling two available buffers. Since the first-in-first-out (FIFO) storage buffer of NSC 208 is full, a deadlock condition occurs because there is no room to receive the second portion A2 of flits 222, 224, and 226 or the first portion B1 of flits 228, 230, and 232 to be able to output a complete flits (formed of A1 and A2, or formed of B1 and B2). The operation of NSC 208 is effectively frozen and cannot process further data.

[0034] Figure 3 Illustrated Figure 1 For the purpose of illustration, the switch 110 has been simplified. Figure 3 The view illustrated in . Figure 3In the example of FIG. 1 , switch 110 includes sub-switch 302 and sub-switch 304. Sub-switch 302 includes ports 0, 1, 2, 3, and 4. Sub-switch 304 includes ports 5, 6, 7, 8, and 9. As shown, port 4 of sub-switch 302 is connected to port 9 of sub-switch 304. In this example, the channel formed by ports 4 and 9 is capable of conveying data micro-slices of the same size as the data micro-slices conveyed by any of ports 0 to 3 or 5 to 9. Sub-switches 302 and 304 are also connected via a synchronization channel 308, and sub-switches 302 and 304 communicate on the synchronization channel to operate in coordination with each other. The connectivity between sub-switches 302 and 304 via ports 4 and 9 allows data micro-slices to cross from one sub-switch to another sub-switch. It should be understood that each of sub-switches 302 and 304 may have fewer ports or more ports than shown. In some examples, each sub-switch 302 and 304 includes one or more additional ports. Such additional ports may be one or more 3-dimensional ports that may connect to other layers and / or circuitry above and / or below the particular layer of the IC in which the sub-switches 302, 304 are implemented.

[0035] In general, the switch 110 can operate in a plurality of different operating modes. In a first operating mode of the different operating modes, the switch 110 processes data of a first width. In the first operating mode, selected ports of the sub-switches 302 and 304 can operate independently of each other. In a second operating mode of the different operating modes, the switch 110 processes data having a second width greater than the first width. In the second operating mode, selected ports of the sub-switches 302 and 304 can operate in a coordinated manner (e.g., as a pair).

[0036] As discussed, the first operating mode and the second operating mode are employed to process data flakes of different widths. Generally speaking, the first operating mode processes flakes of a first width, where the first width corresponds to or is equal to the width of sub-switch 302 (e.g., or sub-switch 304). That is, the first width can be the width of port 0, 1, 2, 3, or 4. The second operating mode processes flakes of a second and different width. The second width corresponds to or is equal to the combination of the width of sub-switch 302 and the width of sub-switch 304. That is, the second width can be the combined width of ports 0 and 5, the combined width of ports 1 and 6, etc.

[0037] Although Figure 310 is generally described with respect to the switch 110 operating in a particular mode of operation, but it should be understood that the mode of operation may be implemented for selected groups of ports. In describing the operation of the switch 110, a complementary port group is formed by a port of the sub-switch 302 and a port of the sub-switch 304. For example, the complementary port groups present in the switch 110 include the following pairs (0,5), (1,6), (2,7), and (3,8). As defined herein, the term "complementary port group" refers to a plurality of ports, wherein the plurality of ports includes one port for each sub-switch of the switch, wherein each of the plurality of ports is configured to transmit data to a same destination external to the switch and to receive data from a same source external to the switch. For example, referring to the complementary port group 0,5, both ports are capable of receiving data flits from a same source external to the north switch 110 and are capable of transmitting data flits to a same destination external to the north switch 110. Similarly, referring to the complementary port group 2 , 7 , both ports are capable of receiving data flits from the same source external to the south switch 110 , and transmitting data flits to the same destination external to the south switch 110 .

[0038] It should be understood that although the examples described herein depict 2 sub-switches, the present arrangements are not intended to be so limited. In one or more other exemplary implementations, each switch 110 may include more than 2 sub-switches. For example, each switch 110 may include 4 sub-switches. In another example, each switch 110 may include 8 sub-switches. Thus, each complementary port group will include one port from each sub-switch, rather than 1 port from each sub-switch. Figure 3 Each complementary port group includes only one pair of ports as in the example of . The complementary port group in the 4-subswitch example will include 4 ports, where one port in the complementary group is taken from each subswitch. The complementary port group in the 8-subswitch example will include 8 ports, where one port in the complementary group is taken from each subswitch.

[0039] When forming complementary ports, ports 4 and 9 are excluded. Figure 3 In the example of FIG. 4 , ports 4 and 9 may be used to carry data flits of a first or smaller size between sub-switches 302, 304. Ports 4 and 9 are not used to carry data flits of a larger size.

[0040] For purposes of illustration, consider an example where each of ports 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 is a 128-bit port. Each of these ports may include additional signals for conveying control data, quality of service (QoS) data, bit width, etc. However, for ease of discussion, the width of the data portion of each data flit is used to refer to the width of the ports of the sub-switches 302, 304. In the first mode of operation, each of ports 0, 1, 2, 3, 4, 5, 6, 7, and 9 is capable of conveying 128-bit data flit.

[0041] In one or more examples, in the first mode of operation, for the selected complementary port groups of sub-switch 302 and sub-switch 304, only one port in the selected complementary port group is capable of passing a single data flits at a time. For example, given the selected complementary port group (2, 7), only port 2 or port 7 will output a 128-bit flits at a given time. Port 7 may pass the 128-bit data flits in a subsequent or next clock cycle.

[0042] In one or more other examples, in the first operating mode, each port in the selected complementary port group can pass a single data flits as described or concurrently for the selected complementary port groups of the first sub-switch 302 and the sub-switch 304. For example, given the selected complementary port group (2, 7), both port 2 and port 7 can output 128-bit flits simultaneously. In the first operating mode, the flits output from ports 2 and 7 can be independent because the flits belong to different data packets.

[0043] Figure 4 Illustrated Figure 1 Another exemplary implementation of the switch 110 of FIG. For the purpose of illustration, the Figure 4 The view illustrated in . Figure 4 The example of illustrates a switch 110 with ports operating in a second mode of operation. In the second mode of operation, the sub-switches 302, 304 operate in a coordinated manner. Continuing with the example where each of ports 0, 1, 2, 3, 5, 6, 7, and 8 is implemented as a 128-bit port, the switch 110 is operable to carry flits with a width of 256 bits by treating the complementary port group as a single larger port.

[0044] exist Figure 4In the example of FIG. 1 , in the case where a 256-bit microslice is presented to port 0, 1, 2, or 3 of sub-switch 304, the microslice occupies the port to which the microslice is presented and the complementary port of sub-switch 302. For example, when a 256-bit microslice is presented at port 0, the 256-bit microslice will occupy ports 0 and 5, for example, as a complementary port group that appears as a single larger port. In this case, port 5 acts or operates as a data buffer. For purposes of illustration, consider an example where a 256-bit microslice is directed south to ports 2 and 7. This means that arbitration involving the 256-bit microslice may only occur between ports of sub-switch 302, and excludes ports of sub-switch 304 because, for example, ports 5 and 7 will act as data buffers. Therefore, in order to handle the larger microslice size, when a 256-bit microslice is received and routed to the south, port 7 does not participate in arbitration. As a corollary, switch 110 will only route the 256-bit microslice to one of ports 0, 1, 2, or 3. To maintain ordering consistency, 256-bit read request and / or 256-bit write response flits are only routed on ports 0, 1, 2, or 3. 256-bit flits are never routed on ports 4 or 9.

[0045] In one aspect, when operating in the second operating mode, for the selected complementary port groups of sub-switch 302 and sub-switch 304, each port of the selected group is configured to concurrently pass a portion of a single microchip data. For example, consider an example in which a 256-bit microchip is received by port 0 and routed to port 2. In this example, the selected complementary port group (2, 7) corresponds to the destination port. In this case, port 2 will concurrently pass a first portion (e.g., 128 bits) of the 256-bit microchip while port 7 simultaneously passes a second portion (e.g., 128 bits) of the 256-bit microchip. Because the two portions of the 256-bit microchip are routed together as a single larger microchip, these portions of the 256-bit microchip travel together from switch 110 to switch 110 through NoC 100, thereby avoiding Figure 2 The deadlock condition illustrated in .

[0046] On the other hand, when operating in the second operating mode, selected ports from sub-switch 304 are excluded from arbitration for selected complementary port groups of sub-switch 302 and sub-switch 304. Referring to the previous example where a 256-bit flit is received at port 0 and is to be routed to port 2, port 7 does not participate in arbitration. That is, arbitration is performed only between ports 0, 1, 2, and 3 of sub-switch 302.

[0047] On the other hand, in the second operating mode, for the selected complementary port groups of sub-switch 302 and sub-switch 304, in response to a first port in the selected group winning arbitration for a data flits corresponding to a second width (e.g., 256 bits) (e.g., port 0), the first port (e.g., port 0) passes the data flits only in response to determining that a second port in the selected group (e.g., port 7) has sufficient credits for transmitting the data.

[0048] In one or more exemplary implementations, each received data flit may include a specific bit (e.g., a tag bit). The tag bit indicates whether the flit corresponds to a first width or a second and greater width (e.g., 128 bits and 256 bits in this example). That is, the tag bit indicates the width of the data flit. The tag bit may be included in the payload portion of the flit. In response to any port on the sub-switch 302, referred to as a receiving port, receiving a 256-bit flit, as determined by checking the state of the tag bit (e.g., where the set tag bit indicates the second and greater width of the flit), the complementary port of the receiving port operates in a data buffering mode and does not participate in arbitration. In the case of a 256-bit flit, for purposes of illustration, both the receiving port and the destination port refer to ports of the sub-switch 302. The destination port of the sub-switch 304 of the 256-bit flit can win arbitration only when the complementary port in the sub-switch 302 of the destination port in the sub-switch 302 has sufficient credits for data transmission.

[0049] In the illustration, referring to the previous example where a 256-bit microchip is received on port 0 and is to be routed to port 2, the receiving port is port 0 and the destination port is port 2. The complementary port of receiving port 0 is port 5. In order to handle the 256-bit microchip, port 5 will operate in buffer mode and will not participate in arbitration. In addition, as noted, destination port 2 will only win arbitration for the 256-bit microchip if the destination port's complementary port 7 has sufficient credits to perform the data transfer. In addition, when the destination port wins arbitration for the 256-bit microchip, the complementary port of the winning destination port may not win arbitration for the 128-bit microchip. Therefore, in the case where destination port 2 wins arbitration for the 256-bit microchip data, complementary port 7 will not win arbitration for the 128-bit microchip data.

[0050] Figure 5 Illustrated Figure 1 Another exemplary implementation of switch 110 is shown in FIG. In this example, sub-switches 302 and 304 are shown in more detail. In this example, each of ports 0, 1, 2, 3, 5, 6, 7, and 8 includes an arbitrator and a FIFO memory (shown as "FIFO mem"), through which data is output from the sub-switch and through which data is received into the sub-switch. Figure 5 In the example of , each FIFO memory has an output connected to each arbiter with a different port number in the same sub-switch. That is, FIFO memory 0 is connected to arbiters 1, 2, and 3. FIFO memory 1 is connected to arbiters 0, 2, and 3, and so on.

[0051] In some respects, the Figure 5 . For example, in some exemplary implementations, each port may support multiple virtual channels, where each virtual channel is connected to its own FIFO memory. Thus, for example, if port 0 supports 4 virtual channels, port 0 will include 4 FIFO memories 0, such as one FIFO memory for each virtual channel. In addition, for the purpose of illustration, ports 4 and 9 are not shown. However, it should be understood that ports 4 and 9 can be implemented as other ports, where each of ports 4 and 9 includes an arbitrator for transmitting data and a FIFO memory for receiving data.

[0052] For valid requests received by a port, each FIFO memory is capable of presenting a request to one arbiter at a time. For example, if a FIFO memory has a valid request at the head of the queue (e.g., each FIFO memory will have at most one valid request at the head of the queue), the FIFO memory presents the request to the specific arbiter (e.g., one arbiter) to which the request is directed. A request to forward data from FIFO memory 0 to port 2 will result in FIFO memory 0 presenting a request only to arbiter 2 (e.g., FIFO memory 0 does not submit any requests to arbiters 0, 1, 3, or 4).

[0053] In this example, connections between sub-switches 302 are shown through mask circuits 502 (e.g., 502-0, 502-1, 502-2, and 502-3). In one aspect, the synchronization channel 308 between sub-switches 302 and 304 described previously can be implemented through the connections shown by the various mask circuits 502. Figure 5 In the example of , the arbiters for each complementary port group are communicatively linked via mask circuit 502. For example, arbiter 0 is communicatively linked to arbiter 5 via mask circuit 502-0. Arbiter 1 is communicatively linked to arbiter 6 via mask circuit 502-1, and so on.

[0054] When operating in the first operating mode or the second operating mode, each mask circuit 502 can ensure that the ports in the complementary port group operate as described. For example, referring to the example where a 256-bit flits are to be output on port 2, mask circuit 502-2 can ensure that a 128-bit flits are not output on port 7 concurrently with the 256-bit flits from port 2. In one or more exemplary implementations, each mask circuit 502 can be implemented as a 2-port arbiter, where mask circuit 502 assumes that both ports have valid transactions. In the event that both ports win arbitration, each mask circuit 502 can decide which port in the complementary port group is selected.

[0055] exist Figure 5 In the example of , each mask circuit 502 may also be communicatively linked to the data output of each arbitrator to which the mask circuit is coupled via control signals. For example, mask circuit 502-0 is coupled to arbiters 0 and 5 via control signals (shown using dashed lines) that are used to select which of these arbitrators wins the arbitration if arbiters 0, 5 win when arbiter 0 is to deliver a 256-bit flit. Mask circuit 502-0 is also coupled to the data output from each of arbiters 0, 5 in order to monitor the state of the outputs of arbiters 0, 5 and update any state machine circuitry that may be included in mask circuit 502-0 that tracks the arbitration winning port, the port's token and / or credit, etc.

[0056] Figure 6 Certain aspects of the operation of mask circuit 502 are illustrated. In this example, mask circuit 502-2 is illustrated. As shown, mask circuit 502-2 can provide control signals (e.g., one or more mask bits) to each of arbitrators 2 and 7. In this example, mask circuit 502-2 is coupled to each of arbitrators 2 and 7 via register 602. In this example, the inclusion of register 602 (e.g., clock control circuit components) illustrates that mask circuit 502 does not have to be in the same clock cycle as the arbitrator being controlled by the mask circuit. In other words, the calculations performed by mask circuit 502 to perform arbitration between the arbitrators of each complementary port group can be separate calculations.

[0057] In one or more examples, the mask circuit 502 can perform calculations using data from the previous clock cycle to determine the action to be taken on the next clock cycle. The addition of the clock control register 602 facilitates the mask circuit 502 to perform a large number of calculations. This also results in a one clock cycle delay in routing data through the switch 110.

[0058] In an example where port 2 is to output 256-bit flits and port 7 is to output 128-bit flits, mask circuit 502-2 can select port 2. For example, mask circuit 502-2 can output a 0 value via a control signal to arbitrate or select port 2, or a 1 value via a control signal to arbitrate or select port 7. Referring again to this example, the control signal (e.g., mask bit) from mask circuit 502-2 can be used as follows:

[0059] If port 2 is not the winner of arbitration for a 256-bit flit, the mask bits are ignored.

[0060] Otherwise, if port 7 is not the winner, the mask bits are ignored.

[0061] Otherwise, if the mask bit is set to 1, the grant is sent to port 7, otherwise the grant is sent to port 2.

[0062] In one or more examples, each mask circuit 502 can operate as a registered late select. In the fall-through case (when the port arbiter is bypassed), the overhead is limited to the overhead of the two-to-one multiplexer. For example, to ensure that the user circuit design can operate at a high clock rate, the mask circuit system is designed to utilize the entire clock cycle. Therefore, the output of the mask circuit 502 is fed to the register 602 and read in the next clock cycle. In some cases, in the case where the switch has one data flow in a given clock cycle, the switch does not require any arbitration. In such cases, the overhead generated by routing data using the mask circuit 502 corresponds to the overhead of the multiplexer (e.g., clock cycle).

[0063] As illustrated, mask circuit 502-2 may receive input signals specifying token and / or transaction credit (TC) usage for each of the ports being arbitrated (eg, ports 2 and 7 in this example). Figure 7 An example of connectivity of mask circuit 502-2 to each data output of arbiters 2 and 7 is illustrated. In one aspect, each mask circuit 502 may implement a state machine capable of tracking token and credit usage of ports arbitrated by mask circuit 502. In this example, mask circuit 502-2 implements a state machine capable of tracking token and transaction credit usage of ports 2 and 7 based on data and / or other information (e.g., traffic class, virtual channel, other control signal information) output from each of arbiters 2 and 7.

[0064] For example, in response to selecting a winner from port 2 or port 7, the state machine of mask circuit 502-2 is updated. The above information (eg, data, traffic class, virtual channel, and / or other control signal information) may be transmitted via Figure 6 and 7The inputs illustrated in the figure feed into mask circuit 502-2. Mask circuit 502-2 can maintain tokens for ports 2 and 7 and track the availability of tokens (e.g., transaction credits) for each of the two ports. Thus, mask circuit 502-2 can perform tokenization of QoS to select the next arbitration winner.

[0065] In one aspect, mask circuit 502 can be configured to perform a relatively simple arbitration that rotates between arbitrators of a complementary port group on each clock cycle. In other examples, arbitration may be more complex, where mask circuit 502 collects tokens from each port in a complementary port group and continues to select one of the ports as the arbitration winner until the tokens for that port are exhausted, at which point mask circuit 502 begins selecting another port in the complementary port group until the tokens for that port are exhausted, and so on.

[0066] However, the exemplary arbitration schemes presented herein are provided for illustrative purposes and are not intended as limitations on the described inventive arrangements.More or less complex arbitration schemes may be used, which may or may not utilize tokenization of transaction credits and / or QoS.

[0067] Figure 7 Illustrated Figure 1 Another exemplary implementation of the switch 110. Figure 7 In the example of , arbiters 0, 1, 3, 5, 6 and 8 and FIFO memories 2 and 7 have been removed for ease of illustration. Figure 7 An exemplary implementation is illustrated in which the FIFO memory in each sub-switch is coupled to an arbiter in the same sub-switch (e.g., each arbiter has a different port number than the FIFO memory), as previously described, and is also coupled to an arbiter of a complementary port in another sub-switch.

[0068] Figure 7 The example of is intended to illustrate connectivity only for arbiters 2 and 7. That is, FIFO memories 0, 1, 3, 5, 6, and 8 are coupled to arbiter 2 and arbiter 7. Figure 7 In a full view of switch 110, although not shown, FIFO memory 0 and FIFO memory 5 will each be connected to arbiters 1, 2, 3, 6, 7, and 8. FIFO memory 1 and FIFO memory 6 will each be connected to arbiters 0, 2, 3, 5, 7, and 8, and so on. Neither FIFO memory 0 nor FIFO memory 5 is coupled to arbiter 0 or arbiter 5 (where port 5 is the complementary port of port 0). Similarly, neither FIFO memory 1 nor FIFO memory 6 is coupled to arbiter 1 or arbiter 6 (where port 6 is the complementary port of port 1), and so on.

[0069] refer to Figure 7 The described connectivity allows a 128-bit slice of data to be received into one sub-switch of switch 110 and output via another sub-switch of switch 110 . Figure 7 The example of can be used to transmit data micro slices from one sub-switch to another sub-switch in the same switch. Also as described, ports 4 and 9 can be used to transmit data micro slices from one sub-switch to another sub-switch. Figure 7 The example also illustrates a case where the mask circuit 502 may provide a control signal to a corresponding arbiter through a register 602 .

[0070] In one or more exemplary implementations, in terms of QoS, for each 256-bit micro-slice, the corresponding token value can be updated by two (e.g., as opposed to updating the corresponding token value by one in the case of a 128-bit micro-slice) so that 128 bits and 256 bits have the same QoS token definition.

[0071] In one aspect, each 128-bit flits is implemented the same as a conventional 128-bit NoC implementation, except that an additional flag bit is added to indicate whether the width of the flits is 128 or 256 bits, as previously discussed. Table 1 illustrates an example of a data structure that may be used to implement a 256-bit flits for write transactions.

[0072] Table 1

[0073] Blank (42 bits) Data (256 bits) Control (8 bits) Strobe (32 bits) Tag (1 bit) Control (26 bits)

[0074] Table 2 illustrates an example of a data structure that may be used to implement a 256-bit flits for a read transaction (eg, a read response).

[0075] Table 2

[0076] Blank (42 bits) Data (256 bits) Control (40 bits) Tag (1 bit) Control (26 bits)

[0077] Referring to the example of Tables 1 and 2, for a 256-bit microchip, the NoC packet protocol can utilize two 128-bit ports to provide a total of 365 available bits (wherein this example considers 256 bits of data and additional control bits). In this example, only 323 bits are available. The remaining 42 bits can remain blank or reserved. The exemplary data structures of Tables 1 and 2 also illustrate that a tag bit can be included in the payload portion of the microchip. For a 128-bit microchip, the tag bit can also be included in the payload portion of the microchip.

[0078] Figure 8 Another exemplary implementation of the switch 110 is illustrated. Figure 8In the example of FIG. 3 , the sub-switch 302 includes configuration registers 802 corresponding to ports 0, 1, 2, and 3 (e.g., 802-0, 802-1, 802-2, and 802-3). Each control register 802 can control a corresponding port. For example, control register 802-0 can control port 0. Figure 8 In the example of , the value written to each control register 802 determines whether the port will handle 128-bit flits or 256-bit flits. Figure 8 The example does not need to include a flag bit within the flit itself to indicate the width of the flit. Instead, the controller can be used to program a value into the configuration register 802 to specify whether a given port will operate in the first operating mode or the second operating mode.

[0079] For example, programming configuration register 802-0 for a first operating mode allows ports 0 and 5 to operate independently, each capable of delivering 128-bit flits independently of the other. Programming configuration register 802-0 for a second operating mode enables ports 0 and 5 to operate cooperatively to transmit / receive 256-bit flits.

[0080] In one aspect, the configuration register 802 can be programmed prior to run-time of the NoC 100, wherein different sets of ports of the sub-switches 302, 304 are programmed to operate in selected modes. As discussed, some ports of the sub-switches 302 can be programmed to operate in a first operating mode, while other ports are programmed to operate in a second operating mode. In another aspect, the controller 804 can continuously program the configuration register 802 during operation to change the operating mode used by the ports of the sub-switches 302, 304 during run-time or operation of the NoC 100.

[0081] Fig. 9 Another exemplary implementation of the NoC 100 is illustrated. In this example, the NoC 100 includes one or more NMCs 106 implemented as 128-bit NMCs with a single 128-bit port and one or more NMCs 106 implemented as 256-bit NMCs with two 128-bit ports. Figure 8 In the example of , NMC 106-1 is a 256-bit NMC, and NMCs 106-2, 106-3, and 106-4 are 128-bit NMCs. NoC 100 includes one or more NSCs 108 implemented as 128-bit NSCs with a single 128-bit port and one or more NSCs 108 implemented as 256-bit NSCs with two 128-bit ports. Fig. 9 In the example of , NSC 108 - 1 is implemented as a 128-bit NSC, and NSC 108 - 2 is implemented as a 256-bit NSC.

[0082] The 256-bit NMC 106 is capable of receiving a transaction specifying a destination identifier (ID) from an endpoint circuit 102 (not shown). The destination ID indicates whether the destination (e.g., the NSC 108 to which the transaction is to be directed) is a 256-bit NSC or a 128-bit NSC. In response to determining that the destination is a 128-bit NSC 108, the 256-bit NMC creates 128-bit data flits formatted according to a packet protocol used by the NoC (e.g., the NoC Packet Protocol or NPP). For a given data packet, the 128-bit flits are forwarded from the NMC to the same port of a switch to which it is connected. The 128-bit flits may be transmitted to the switch sequentially. That is, the NMC may forward 128-bit flits of the same packet to the same port of a switch to which it is connected, thereby avoiding Figure 2 A potential deadlock condition is illustrated in .

[0083] In response to determining that the target is a 256-bit NSC 108, the 256-bit NMC 106 can create 256-bit data flits. The 256-bit NMC 106 can be updated so that the number of flits transmitted depends on whether the flits transmitted are 256 bits wide or 128 bits wide. That is, the number of 256-bit flits transmitted by the 128-bit NMC 106 will be twice the number of 256-bit flits transmitted.

[0084] It should be understood that the 256-bit NMC is capable of transmitting two 128-bit flits concurrently if the two 128-bit flits correspond to different packets. Each of the concurrently transmitted 128-bit flits may be transmitted to a different port of the switch 110 to which it is connected (e.g., the 128-bit flits are transmitted to each of the complementary ports). Therefore, the 256-bit NMC 106 does not require any special arbiter to handle the two concurrent flits.

[0085] exist Fig. 9 In the example of , a 256-bit NSC 108 can receive data specifying a source ID from an endpoint circuit 104 (not shown). The source ID indicates whether the target (e.g., the NMC 106 to which the response is to be directed) is a 256-bit NMC or a 128-bit NMC. In response to determining that the target is a 128-bit NMC, the 256-bit NSC 108 can create a 128-bit data microchip. In response to determining that the target is a 256-bit NMC, the 256-bit NSC can create a 256-bit data microchip. The 256-bit NSC 108 can be updated so that the number of microchips transmitted depends on whether the microchip is 256 bits wide or 128 bits wide. That is, the 256-bit NSC 108 can transmit two 128-bit microchips or one 256-bit microchip.

[0086] The 256-bit NSC 108 may include two ports, each capable of processing 128-bit data. The 256-bit NSC 108 may be capable of accepting a single 256-bit flits or two 128-bit flits concurrently (e.g., where the two concurrent 128-bit flits are different groups). Fig. 9 In the example of FIG. 1 , when two 128-bit flits are present, any flits received through ports 0, 1, 2, or 3 of the connected switch 110 are routed to the first port of the 256-bit NSC 108, while any flits received from ports 5, 6, 7, or 8 of the connected switch 110 are routed to the second port of the 256-bit NSC 108. As a result, the 256-bit NSC 108 does not require any special arbiter to handle two concurrent flits.

[0087] The 256-bit NSC 108 is also capable of transmitting data to an NMC and generating a flits size based on the size of the receiving NMC. That is, in response to determining that the data is destined for a 128-bit NMC, the 256-bit NSC 108 generates 128-bit flits (e.g., for a given packet) that are output to the same port of the switch to which it is connected. The flits may be output to the ports sequentially. In response to determining that the data is destined for a 256-bit NMC, the 256-bit NSC 108 generates 256-bit flits.

[0088] Fig. 9 The example of illustrates that the NoC 100 can concurrently route both 128-bit flits and 256-bit flits therein. The example illustrates the state of the NoC 100 when both types of flits are routed from one switch 110 to another switch. The source of each flits is indicated, e.g., the specific NMC 106 from which the flits entered the NoC 100. Figure 8 In the example of , each 128-bit microchip traverses a single port corresponding to a single sub-switch of each switch 110. Each 256-bit microchip concurrently traverses a complementary port pair (or a complementary port group) of two sub-switches of each switch 110, where each complementary port group appears as a single larger port.

[0089] Fig.10 Another exemplary implementation of NoC 100 is illustrated. Fig.10 Examples with Fig. 9 The examples are substantially similar, although the locations and routing of the corresponding 128-bit microslices and 256-bit microslices contained therein are shown to be different.

[0090] Fig.11 An exemplary method 1100 of processing data using the switch 110 of the NoC 100 as described within this disclosure is illustrated.

[0091] In block 1102, a switch 110 of the NoC 100 receives data. In block 1104, the switch 110 determines the width of the data. In block 1106, the switch implements a selected operating mode for processing the data based on the width. The selected operating mode is selected from a plurality of different operating modes. In block 1108, the switch 110 transmits the data using the selected operating mode.

[0092] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. Some exemplary implementations include all of the following features in combination.

[0093] In one aspect, each operating mode may correspond to one of the possible widths of the data. As discussed, different operating modes may be independently applied to different complementary port groups of the switch 110. That is, complementary ports 2 and 7 may implement a first operating mode, while complementary ports 1 and 6 implement a second operating mode.

[0094] As described above, data may include one or more flits, or may be formed from one or more flits. The switch 110 can implement a selected mode of operation based on the width of the one or more flits on a per-flit basis.

[0095] In another aspect, determining the width of the data includes determining a state of a tag included in each of the one or more flits. For example, a particular sub-switch 302, 304 receiving data (e.g., a data flits) can evaluate a tag bit of a flits to determine whether the flits have a first width or a second width. For purposes of illustration, the first width may be 128 bits and the second width may be 256 bits. The state of the tag bit indicates the width of the data.

[0096] In another aspect, determining the width of the data includes programming one or more registers included in the switch. The state of the one or more registers when programmed indicates the width of the data and specifies a selected operating mode for one or more ports of the switch.

[0097] In one aspect, the switch 110 includes a sub-switch 302 and a sub-switch 304 coupled to the sub-switch 302 via a synchronous channel. In this case, the switch is capable of processing data flit by operating in a first operating mode among a plurality of operating modes, in which ports in one or more complementary port groups of the first sub-switch and the second sub-switch operate independently.

[0098] On the other hand, the first data flit has a first width corresponding to the width of the sub-switch 302 or the width of the sub-switch 304 .

[0099] In another aspect, in the first operating mode, for the selected complementary group of ports, each port in the selected complementary group of ports is configured to pass data flits.

[0100] In one example, in the first operating mode, for the selected complementary port groups of sub-switch 302 and sub-switch 304, only one port in the selected group passes a first data flit, while another port in the selected group does not concurrently pass another data flit.

[0101] In another example, in the first operation mode, for the selected complementary port groups of the sub-switch 302 and the sub-switch 304, the first port in the selected group is configured to pass a first data sliver, and the second port in the selected group is configured to pass another data sliver concurrently with the first data sliver. The two slivers passed concurrently may be different packets.

[0102] In another aspect, the method includes processing additional data flits by operating in a second operating mode of the plurality of operating modes in which ports in one or more complementary port groups of the first sub-switch and the second sub-switch cooperatively operate to transmit the flits.

[0103] In another aspect, the method includes, for the selected complementary groups of ports of sub-switch 302 and sub-switch 304, excluding ports from the selected group of the second sub-switch from participating in arbitration.

[0104] On the other hand, in the second mode of operation, for the selected complementary port groups of sub-switch 302 and sub-switch 304, each port in the selected complementary port groups is configured to concurrently pass a portion of the same data flit.

[0105] On the other hand, the second data flit has a width corresponding to a combination of the width of sub-switch 302 and the width of sub-switch 304 .

[0106] Fig.12 An exemplary architecture 1200 of an IC including a NoC arranged in accordance with the present invention described herein is illustrated. The architecture 1200 may be used to implement a programmable IC, an adaptive system, and / or a system on a chip (SoC). Fig.12 In the example of FIG. 1 , architecture 1200 is implemented on a single die provided in a single package. In other examples, architecture 1200 may be implemented using multiple interconnected dies in a single package, wherein Fig.12 Various resources of the architecture 1200 (eg, circuitry) illustrated in FIG. 1 are implemented across different interconnect dies.

[0107] In the example, the architecture 1200 includes a plurality of different subsystems including a data processing array 1202, a programmable logic (PL) 1204, a processor system (PS) 1206, a network on chip (NoC) 1208, a platform management controller (PMC) 1210, and one or more hardwired circuit blocks 1212. In addition to the NoC 1208, Fig.12 The various subsystems illustrated in the are provided for illustrative purposes. One or more of the different subsystems may be omitted and / or other subsystems may be added.

[0108] The data processing array 1202 is implemented as a plurality of interconnected and programmable computing slices. The computing slices may be arranged in an array and are hardwired. Each computing slice may include one or more cores and a data memory. In an exemplary implementation, the core of a computing slice may be implemented as a custom circuit that does not execute program code. In another exemplary implementation, the core of a computing slice is capable of executing program code stored in a core-specific program memory contained in each corresponding core.

[0109] Each computing slice also includes a dedicated multi-bit data movement channel connecting the computing slices. Each computing slice may also include support for direct memory access (DMA) operations and locks for moving data to and from the data storage of other computing slices. In one or more other exemplary implementations, the data processing array 1202 may include one or more memory slices that replace one or more of the computing slices.

[0110] The data processing array 1202 includes an interface block 1222 that connects a compute slice or a memory slice to other resources of the architecture 1200. Fig.12 In an example of , interface block 1222 includes a plurality of interconnected interface slices organized into rows. In one example, each of the interface slices may have the same architecture. In another example, the interface slices may be implemented with different architectures, wherein each different interface slice architecture supports communication with different types of resources of architecture 1200. Interface slices 1224 are connected so that data can be propagated from one slice to another in both directions. Each interface slice can operate as an interface for a column of a computing slice and / or a memory slice directly above the computing slice.

[0111] PL 1204 is a circuit system that can be programmed to perform a specified function. For example, PL 1204 can be implemented as a field programmable gate array type circuit system. PL 1204 may include an array of programmable circuit blocks. As defined herein, the term "programmable logic" means a circuit system for building a reconfigurable digital circuit. Programmable logic is formed by many programmable circuit blocks that provide basic functionality. Unlike hard-wired circuit systems, the topology of PL 1204 is highly configurable. In one aspect, each programmable circuit block of PL 1204 includes a programmable element 1226 (e.g., a functional element) and a programmable interconnect 1242. Programmable interconnect 1242 provides a highly configurable topology of PL 1204. Programmable interconnect 1242 can be configured on a per-wire basis to provide connectivity between programmable elements 1226 of programmable circuit blocks of PL 1204, and can be configured on a per-bit basis (e.g., where each wire conveys a single bit of information), which is different from, for example, connectivity between computing slices and / or memory slices in data processing array 1202.

[0112] Examples of programmable circuit blocks of PL 1204 include configurable logic blocks with lookup tables and registers. Unlike the hardwired circuitry described below and sometimes referred to as hardwired circuit blocks, these programmable circuit blocks have undefined functionality at the time of manufacture. PL 1204 may include other types of programmable circuit blocks that also provide basic and defined functionality with more limited programmability. Examples of these circuit blocks may include digital signal processing blocks (DSPs), phase-locked loops (PLLs), and block random access memories (BRAMs). These types of programmable circuit blocks (similar to other programmable circuit blocks in PL 1204) are numerous and intermixed with other programmable circuit blocks of PL 1204. These circuit blocks may also have an architecture that generally includes programmable interconnects 1242 and programmable elements 1226, and are therefore part of the highly configurable topology of PL 1204.

[0113] PS1206 is implemented as a hard-wired circuit system that is manufactured as a part of architecture 1200. PS1206 can be implemented as or include any processor type in a variety of different processor types that can execute program code separately. For example, PS1206 can be implemented as an individual processor, for example, a single core that can execute program code. In another example, PS1206 can be implemented as a multi-core processor. In another example, PS1206 can include one or more cores, modules, coprocessors, I / O interfaces and / or other resources. PS1206 can use any type of architecture in a variety of different types of architectures to implement. The exemplary architecture that can be used to implement PS1206 may include but is not limited to ARM processor architecture, x86 processor architecture, graphics processing unit (GPU) architecture, mobile processor architecture, DSP architecture, a combination of the aforementioned architectures or other suitable architectures that can execute computer-readable instructions or program code.

[0114] NoC 1208 is a programmable interconnect network for sharing data between endpoint circuits in architecture 1200. The endpoint circuits may be disposed in DP array 1202, PL 1204, PS 1206, and / or selected hardwired circuit blocks 1212. NoC 1208 may include high-speed data paths with dedicated switching. In an example, NoC 1208 includes one or more horizontal paths, one or more vertical paths, or both horizontal and vertical paths. Fig.12 The arrangement and number of regions shown in are examples only. NoC 1208 is an example of a common infrastructure that can be used within architecture 1200 to connect selected components and / or subsystems.

[0115] exist Fig.12 In the example of , the networks to be routed through the NoC 1208 are unknown until a design is created for implementation within the architecture 1200. The NoC 1208 can be programmed by loading configuration data into internal configuration registers that define how elements within the NoC 1208, such as switches and interfaces, are configured and operated to pass data from switch to switch and between NoC interfaces used to connect endpoint circuits.

[0116] In one aspect, NoC 1208 is manufactured as part of architecture 1200 (e.g., is hardwired), and while physically unmodifiable, can be programmed to establish connectivity between different master circuits and different slave circuits of a user circuit design. NoC 1208 does not implement any data paths or routes therein when powered on. However, once configured by a master circuit such as PMC 1210, NoC 1208 implements data paths or routes between endpoint circuits. In one or more exemplary implementations, NoC 1208 can be implemented as described herein in conjunction with NoC 100.

[0117] The PMC 1210 is responsible for managing the architecture 1200. The PMC 1210 is a subsystem within the architecture 1200 that is capable of managing other programmable circuit resources across the entire architecture 1200. The PMC 1210 is capable of maintaining a safe and secure environment, booting the architecture 1200, and managing the architecture 1200 during normal operation. For example, the PMC 1210 is capable of providing unified and programmable control of power-up, boot / configuration, security, power management, safety monitoring, debugging, and / or error handling for different subsystems of the architecture 1200 (e.g., DP array 1202, PL 1204, PS 1206, and NoC 1208). The PMC 1210 operates as a dedicated platform manager that decouples the PS 1206 from the PL 1204. Therefore, the PS 1206 and the PL 1204 can be managed, configured, and / or powered on and / or off independently of each other.

[0118] In one aspect, PMC 1210 can operate as a root of trust for the entire architecture 1200. As an example, PMC 1210 is responsible for authenticating and / or validating a device image containing configuration data that can be loaded into architecture 1200 for any programmable resource of architecture 1200. PMC 1210 can also protect architecture 1200 from tampering during operation. By operating as a root of trust for architecture 1200, PMC 1210 can monitor the operation of PL 1204, PS 1206, and / or any other programmable circuit resources that may be included in architecture 1200. The root of trust capabilities as performed by PMC 1210 are distinct and separate from PS 1206 and PL 1204 and / or any operations performed by PS 1206 and / or PL 1204.

[0119] Hardwired circuit blocks 1212 are dedicated circuit blocks that are manufactured as part of architecture 1200. Although hardwired, hardwired circuit blocks 1212 can be configured by loading configuration data into control registers to implement one or more different operating modes. Examples of hardwired circuit blocks 1212 may include input / output (I / O) blocks, transceivers for transmitting and receiving signals to and from circuits and / or systems, memory controllers, etc. outside architecture 1200. Examples of different I / O blocks may include single-ended and pseudo-differential I / O. Examples of transceivers may include high-speed differential clock transceivers. Other examples of hardwired circuit blocks 1212 include, but are not limited to, cryptographic engines, digital to analog converters (DACs), analog to digital converters (ADCs), etc. In general, hardwired circuit blocks 1212 are dedicated circuit blocks.

[0120] Fig.12The various programmable circuit resources illustrated in the example may be initially programmed as part of a boot process for the architecture 1200. During operation, the programmable circuit resources may be reconfigured. In one aspect, the PMC 1210 is capable of initially configuring the DP array 1202, the PL 1204, the PS 1206, and the NoC 1208. At any point during operation, the PMC 1210 may reconfigure all or a portion of the architecture 1200. In some cases, once initially configured by the PMC 1210, the PS 1206 may configure and / or reconfigure the PL 1204 and / or the NoC 1208. The PMC 1210, the PS 1206, the hardwired circuit blocks 1212, and / or circuits implemented within the PL 1204 are examples of a controller (such as the controller 804) that is capable of controlling the state of the control registers 802 of the switch 110.

[0121] Although the present disclosure ends with claims defining novel features, it is believed that the various features described in this disclosure will be better understood by considering the description in conjunction with the accompanying drawings. The processes, machines, manufactures, and any variations thereof described herein are provided for illustrative purposes. The specific structural and functional details described in this disclosure should not be construed as limiting, but merely as a basis for the claims, and as a representative basis for teaching those skilled in the art to variously employ the features described in virtually any appropriately detailed structure. Furthermore, the terms and phrases used in this disclosure are not intended to be limiting, but rather to provide an understandable description of the features described.

[0122] For the purpose of simplicity and clear illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the size of some of the elements may be enlarged relative to other elements. In addition, reference numerals are repeated in the drawings to indicate corresponding, similar or analogous features where deemed appropriate.

[0123] As defined herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0124] As defined herein, the terms "at least one," "one or more," and "and / or" are open-ended expressions that are both conjunctions and transitional conjunctions in operation unless expressly stated otherwise. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0125] As defined herein, the term "automatically" means without human intervention. As defined herein, the term "user" means a human being.

[0126] As defined herein, the term “if” means “when” or “at” or “in response to” or “responsive to”, depending on the context. Thus, the phrase “if it is determined” or “if [a specified condition or event] is detected” may be understood to mean “upon determination” or “in response to determination” or “upon detection of [a specified condition or event]” or “in response to detection of [a specified condition or event]” or “responsive to detection of [a specified condition or event]”, depending on the context.

[0127] As defined herein, the term "in response to" and similar language as described above (e.g., "if," "when," or "upon") means to be susceptible to a response or reaction to an action or event. The response or reaction is automatically performed. Thus, if a second action is performed "in response to" a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. The term "in response to" indicates a causal relationship.

[0128] As defined herein, the term "real time" refers to a level of processing responsiveness sensed by a user or system that is sufficiently immediate for a particular process or determination to be made, or that enables the processor to keep up with some external process.

[0129] As defined herein, the term "substantially" means that the characteristics, parameters or values ​​described need not be achieved precisely, but deviations or variations (including, for example, tolerances, measurement errors, measurement precision limitations and other factors known to those skilled in the art) may occur in amounts that do not interfere with the effect that the characteristics are intended to provide.

[0130] The terms first, second, etc. may be used herein to describe various elements. These elements should not be limited by these terms, as these terms are only used to distinguish one element from another element, unless otherwise stated or the context clearly indicates otherwise.

[0131] Flow chart and block diagram in the figure illustrate the possible concrete implementation architecture, functionality and operation of the system and method of various aspects of the arrangement according to the present invention.In some alternative concrete implementations, the operation pointed out in the frame may not occur in the order pointed out in the figure.For example, depending on the function involved, two frames shown in succession can be performed substantially simultaneously, or these frames can sometimes be performed in reverse order.In other examples, the frame can be usually performed in increasing numerical order, and in other examples, one or more frames can be performed in a changing order, and the result is stored and used in subsequent frames or frames that do not follow immediately thereafter.

Claims

1. An integrated circuit, comprising: A network on chip (NoC), the NoC comprising: Multiple NoC masters; a plurality of NoC slave circuits; and a plurality of switches, wherein the plurality of switches interconnect and communicatively link the plurality of NoC masters with the plurality of NoC slaves; The plurality of switches are configured to receive data of different widths during operation and implement different operation modes for forwarding the data based on the different widths.

2. The integrated circuit of claim 1 , wherein: The data received by the plurality of switches is organized into flits; and Each switch of the plurality of switches is configured to determine a width of the data based on a tag included in each flit and implement a selected operating mode selected from the different operating modes based on a state of the tag on a per flit basis.

3. An integrated circuit according to claim 1, wherein A first operating mode of the different operating modes processes data of a first width; and A second one of the different operating modes processes data having a second width greater than the first width.

4. The integrated circuit of claims 1 to 2, wherein each switch of the plurality of switches comprises: a first sub-switch; and a second sub-switch, the second sub-switch being coupled to the first sub-switch via a synchronous channel; One or more complementary port groups of the first sub-switch and the second sub-switch operate independently in a first operating mode and operate cooperatively as a group in a second operating mode.

5. An integrated circuit as claimed in claims 3 to 4, wherein: In the first operating mode, for a selected set of complementary ports, each port in the selected set of complementary ports is configured to pass a data flits; and In the second mode of operation, for a selected complementary group of ports, each port in the selected group is configured to concurrently pass a portion of the same data flit.

6. An integrated circuit as claimed in claims 3 to 5, wherein each of the one or more complementary port groups is configured to operate in the first operating mode or the second operating mode based on a value stored in a programmable register controlling the complementary port group.

7. The integrated circuit of claim 4, wherein: The first width corresponds to a width of the first sub-switch, and the second width corresponds to a combination of a width of the first sub-switch and a width of the second sub-switch; and In the second mode of operation, for a selected complementary group of ports, the ports in the selected group from the second sub-switch are excluded from arbitration.

8. The integrated circuit of claim 7, wherein In the second operating mode, for a selected complementary port group, in response to a first port in the selected complementary port group winning arbitration for a data flits, the first port passes the data flits only in response to determining that a second port in the selected complementary port group has sufficient credits for transmitting data.

9. A method for routing data in a network on chip (NoC), the method comprising: Receiving data in a switch of the NoC; determining the width of the data using the switch; implementing a selected operating mode for processing the data based on the width using the switch, wherein The selected operating mode is selected from a plurality of different operating modes; as well as The data is communicated via the switch using the selected operating mode.

10. The method of claim 9, wherein the data comprises one or more flits, and the switch implements the selected operating mode on a per-flit basis based on a width of the one or more flits.

11. The method according to claims 9 to 10, wherein said determining the width of said data comprises: One or more registers included in the switch are programmed, wherein states of the one or more registers when programmed indicate the width of the data and specify the selected operating mode for one or more ports of the switch.

12. The method according to claims 9 to 11, wherein the switch comprises a first sub-switch and a second sub-switch coupled to the first sub-switch via a synchronous channel, the method further comprising: processing data flits by operating in a first operating mode of the plurality of operating modes, in which ports in one or more complementary port groups of the first sub-switch and the second sub-switch operate independently; as well as Additional data flits are processed by operating in a second operating mode of the plurality of operating modes, in which ports in the one or more complementary port groups of the first and second sub-switch operate cooperatively to transmit flits.

13. The method of claim 12, wherein in the first operating mode, for a selected complementary group of ports, each port in the selected complementary group of ports is configured to pass a data flits.

14. The method according to claim 12, further comprising: In the second operation mode, for a selected complementary port group, the ports in the selected group from the second sub-switch are excluded from participating in arbitration.

15. The method of claim 12, wherein in the second mode of operation, for a selected complementary group of ports, each port in the selected group is configured to concurrently pass a portion of the same data flit.

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