Electronic structure and method of manufacturing an electronic structure

Abstract

An electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps are deposited on the first UBM region. A bottom stop formed on the second UBM region is wider, shallower, and more rigid than any one of the solder bumps formed on the first UBM region. The second substrate is connected to the first substrate by one or more solder bumps on the first UBM region, and the height of the bottom dead center limits a distance between at least one of the first substrate and the second substrate, or a distance between an object and at least one of the first substrate and the second substrate.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to flip chip bonding, and more particularly to bonding that can support qubit devices.

[0002] Description of Related Technology

[0003] Flip chip bonding is commonly used in the assembly of electronic devices. According to various methods, a bump bond is placed on one of the two chips, and then the chips are connected together by cold pressing or by reflow bonding. The gap between the chips is determined by the bonding force, the geometry of the bumps, and the underlying metallization layer (metallurgy), or by the use of a rigid downstop. The rigid downstop is generally manufactured by a separate step, for example, by depositing some other material, or by etching into a substrate to produce a step with a precise height. When two chips are connected by a rigid downstop, the chips are kept separated from each other by the downstop. However, the manufacture of the downstop may be incompatible with other operating processes used in the chip manufacturing process, especially in the case of a qubit structure device. It is also desirable to reduce the complexity of the downstop manufacturing. Summary of the invention

[0004] According to one embodiment, an electronic structure includes a first substrate having a first under-bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps are provided on the first UBM region. A lower stop formed on the second UBM region is wider, shallower and more rigid than any of the solder bumps formed on the first UBM region. The second substrate is connected to the first substrate by one or more solder bumps located on the first UBM region, and the height of the lower stop limits the distance between at least one of the first substrate and the second substrate, or the distance between an object and at least one of the first substrate and the second substrate. Due to the presence of the lower stop, it provides a predetermined distance between the first and second substrate heights to enhance the reliability of operation, so the electronic structure is less complicated to assemble.

[0005] In an embodiment, the object may be an interposer arranged at a predetermined distance from at least one of the first substrate and the second substrate. The first UBM region is a contact region and the second UBM region is a bottom stop region, and wherein the area of ​​the second UBM region is greater than the area of ​​the first UBM region. The larger area of ​​the second UBM may improve reflow of solder to form the bottom stop. The first UBM area is smaller to enhance the formation of a truncated sphere as a bump bonding portion.

[0006] In an embodiment, the second substrate comprises a third UBM region arranged to contact one or more solder bumps. The third UBM region enhances the connection of the second substrate to an upper surface of a bump bond deposited on the first substrate.

[0007] In an embodiment, the solder on the first and second UBM regions is formed by one of evaporation or electroplating.Each type of deposition has advantages when using deposition to form the solder on the first and second UBM regions.

[0008] In an embodiment, the first UBM region and the second UBM region include pads. The pads provide enhanced connection to the substrate.

[0009] In an embodiment, the first UBM region and the second UBM region include pads etched from metal.The use of etching may enhance the formation and patterning of the UBM metallization layer on the substrate.

[0010] In an embodiment, the height of the bottom stop and the one or more solder bumps is determined by the volume of solder deposited on the first UBM region and the second UBM region and by the area of ​​the under bump metallization layer of each of the first UBM region and the second UBM region. A precisely defined space can be created to control the pitch of a third semiconductor chip (which may or may not be part of another pair of bonded chips) without the need to perform multiple calibrations without using a bottom stop.

[0011] According to one embodiment, a method of manufacturing an electronic structure includes applying a first under-bump metallization (UBM) region and a second UBM region on a first substrate. Solder is deposited on the first UBM region and the second UBM region, and the solder is reflowed to form one or more solder bumps on the first UBM region and a bottom stop on the second UBM region; the second substrate is connected to the first substrate via the one or more solder bumps located on the first UBM region. The height of the bottom stop limits the distance between at least one of the first substrate and the second substrate, or the distance between an object and at least one of the first substrate and the second substrate. A simpler construction with a more precisely defined distance between the first and second substrates is achieved. The simultaneous construction of the bottom stop and the bump bonding portion provides a simpler construction than the construction known to date.

[0012] In an embodiment, one or more solder bumps in the first UBM region and the bottom stop in the second UBM region are formed substantially simultaneously. The result is a more efficient construction and reduced manufacturing time.

[0013] In an embodiment, the area of ​​the second UBM region is larger than the area of ​​the first UBM region. The area of ​​the second UBM is larger to facilitate the formation of the bottom stop, while the first UBM region has a smaller area to facilitate the formation of a truncated sphere as a bump bonding portion. The bottom stop is wider, shallower and more rigid than the bump. Due to the relative incompressibility of the bottom stop compared to the solder bump, it acts as a mechanical bottom stop.

[0014] In an embodiment, before connecting the second substrate to the first substrate, a third UBM region is formed on the second substrate, and the third UBM region is arranged to contact one or more solder bumps on the first substrate. The addition of the third UBM region facilitates the connection of the second substrate with the upper half of the bump bonding portion arranged on the first substrate.

[0015] In an embodiment, the solder is deposited onto the first UBM region and the second UBM region by one or more of evaporation, electroplating, and / or injection molding techniques.Each technique has advantages in construction.

[0016] In an embodiment, the height of the bottom stop and the height of one or more solder bumps are determined based on the volume of solder deposited in the first UBM region and the second UBM region and the area of ​​the under bump metallization layer through each of the first UBM region and the second UBM region. Through the use of the bottom stop, an accurate distance is obtained between the first substrate and the second substrate. The use of the bottom stop can avoid the precise calibration associated with connecting the second substrate to the solder bumps of the first substrate. In the case where a third object (e.g., a third substrate, a chip, an interposer) is included in the structure, the bottom stop also provides a precise spacing between the third object of the device and the first and second substrates without the need for precise calibration.

[0017] In an embodiment, one or more solder bumps have the same size. With this configuration, electrical connection can be enhanced.

[0018] In an embodiment, some solder bumps have different sizes. The connection to the substrate can be enhanced.

[0019] In an embodiment, the deposition of solder bumps in the first UBM region and the second UBM region includes forming solder structures on the surface of the substrate by controlled deposition of solder volume through a removable mold. The removable mold may facilitate construction.

[0020] In an embodiment, the removable mold is a photoresist.The photoresist can enhance the structuring process.

[0021] In an embodiment, the solder bumps are confined to a confined area. This configuration can enhance the operation of the electronic structure by allowing more qubits to be arranged on the electronic structure.

[0022] In an embodiment, the solder bumps have the same size, and the pattern of the bumps is tailored to increase the reliable contact area. Reliability is improved by this embodiment.

[0023] In an embodiment, some solder bumps have different sizes, and the pattern of the bumps is customized to increase the reliable contact area. Reliability is improved by this embodiment.

[0024] According to one embodiment, an electronic structure includes a first substrate having a first under-bump metallization (UBM) region and a second UBM region, and one or more solder bumps are provided on the first UBM region. A lower stop is formed on the second UBM region, and the surface area of ​​the lower stop is greater than the surface area of ​​the one or more solder bumps. The second substrate is connected to the first substrate via one or more solder bumps located on the first UBM region. The height of the lower stop is configured to limit the distance between at least one of the first substrate and the second substrate, or the distance between an object and at least one of the first substrate and the second substrate. Due to the presence of the lower stop, a predetermined distance is provided between the first and second substrate heights to enhance the reliability of operation, so the electronic structure is less complicated to assemble. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are illustrative embodiments. They do not show all embodiments. In addition or as an alternative, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or for more effective examples. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0026] Figure 1A and 1B Substrate preparation including post-solder patterning and post-solder reflow, consistent with illustrative embodiments, is shown respectively.

[0027] Figure 2 An example application of using standoffs to control chip gap and form bump bonds consistent with the illustrative embodiments is shown.

[0028] Figure 3 is a flow chart illustrating a method of preparing a substrate with a UBM by forming and patterning a UBM mask and substantially simultaneously depositing solder bumps and solder spacers, consistent with an illustrative embodiment.

[0029] Figure 4 is a flow chart illustrating a method of preparing a substrate having a UBM by depositing a UBM metallization layer on the substrate through a patterning and etching process, consistent with an illustrative embodiment.

[0030] Figure 5 A specifically configured computing device is operable, consistent with the illustrative embodiments, to perform one or more functions described herein. DETAILED DESCRIPTION

[0031] Overview

[0032] In the following detailed description, many specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings can be practiced without these details. In other examples, relatively high-level descriptions of well-known methods, procedures, components and / or circuits are provided, but without detailed descriptions, to avoid unnecessarily obscuring the various aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the accompanying drawings, as there may be fewer or more elements than shown and described.

[0033] When discussing the present technology, it may be helpful to describe various significant terms. On the one hand, spatially related terms, such as "front", "back", "top", "bottom", "below", "below", "lower", "above", "upper", "side", "left", "right", etc., are used with reference to the direction of the accompanying drawings described. Since the components of the embodiments of the present disclosure can be placed in a plurality of different directions, the directional terms are used for the purpose of illustration and are by no means limiting. Therefore, it should be understood that the spatially relative terms are intended to cover the different directions of the device in use or operation except the direction depicted in the figure. For example, if the device in the figure is turned over, the elements described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, for example, the term "below" can cover the orientation of both above and below. The device can be oriented in other ways (rotated 90 degrees or observed or referenced in other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0034] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together. As used herein, the term "mechanical tolerance" relates to electrical properties that are not significantly affected by the mechanical alignment between the subject components.

[0035] As used herein, certain terms are used to indicate behavior that may be considered idealized, such as "lossless," "superconductor," "superconducting," "absolute zero," which are intended to cover functionality that may not be completely ideal but is within an acceptable range for a given application. For example, a certain level of loss or tolerance may be acceptable so that the resulting materials and structures may still be referred to by these "idealized" terms.

[0036] Although the terms first, second, third, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0037] Example embodiments are described herein with reference to schematic diagrams of idealized or simplified embodiments (and intermediate structures). Thus, variations from the shapes illustrated as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the regions shown in the figures are schematic in nature, and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.

[0038] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0039] The present disclosure generally relates to flip chip bonding, which can, for example, support connecting qubit devices. Superconducting quantum computing is an implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena in information processing and communication. There are various models of quantum computing, and the most popular models include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of the two states. A quantum gate is a generalization of a logic gate, however, a quantum gate describes the transformation that one or more qubits will undergo after a gate is applied to them, given the initial state of the qubit.

[0040] The ability to include more superconducting qubits is critical to being able to realize the potential of quantum computers. However, it is challenging to generate a quantum processor with desired qubit properties (such as frequency, fidelity, etc.) on a monolithic qubit chip. A modular architecture comprising interconnected smaller modular device units may make the realization of large-scale quantum processors more feasible. However, such a modular architecture may involve connections between qubits on separate physical chips and / or supporting circuits for the qubit chips. Various quantum phenomena such as superposition and entanglement have no analogues in the classical computing world, and therefore may involve special structures, techniques, and materials in order to assemble electronic devices that can operate in cryogenic environments.

[0041] On the one hand, the teachings herein are based on the inventor's insight that, because quantum circuits present unique challenges that are not presented in classical computing architectures, it may be ineffective to directly apply traditional integrated circuit technology for interacting with computing elements to superconducting quantum circuits. In fact, many of the systems and architectures discussed herein operate in cryogenic environments and may involve superconductivity. Therefore, the embodiments of the present disclosure are further based on the recognition that problems unique to quantum circuits have been considered when evaluating the suitability of traditional integrated circuit technology for building superconducting quantum circuits, and particularly when selecting methods and architectures for connecting components of quantum computers. The technology described herein can be implemented in a variety of ways. Example embodiments are provided below with reference to the following drawings.

[0042] Example Architecture

[0043] Figure 1A and 1B The substrate preparation including solder patterning 100A and solder reflow 100B consistent with the illustrative embodiment is shown respectively. The substrate 105 is prepared with an under-bump metallization layer (UBM) 120. The UBM provides an electrical connection from the substrate to the solder bump (or bumps). For example, the UBM 120 can provide a wetting surface for the solder. Two areas are defined - one for electrical contact 125 and the other for (one or more) spacer areas 130. The solder 115 is deposited on the wafer and defined by photolithography. The solder 115 is reflowed at a temperature higher than its solder melting temperature, and the reflowed solder wets the UBM surface 120. The UBM pattern in the (one or more) spacer area 130 is larger than the UBM pattern in the contact area 125.

[0044] like Figure 1BAs shown, reflow will cause the solder to form a truncated sphere in the contact area 130. Due to its size, the spacer area 130 causes a substantially flat area to be formed after the solder reflow. As discussed herein, the difference between "solder bumps" and "bottom stops" is the amount of solder deposited on each "solder bump" and "bottom stop" and the physical size (e.g., area) of the bottom stop UBM and the bump UBM. In contrast, the spacer is wider and shallower than the bump. On the other hand, the bump is higher than its width, leaving room for the solder material to seep out from the side. By the construction that the spacer is wider and shallower than the bump, they will not (or almost not) move when pressed, thereby maintaining a relatively constant height. Therefore, the height of the spacer is controllable (by the dimensions used, such as the dimensions discussed in this paragraph). Since the spacer is more rigid than the bump, the spacer can be used as a height controller. It should be understood that the spacer can be used not only as a height controller for the first and second substrates, but also can provide a precise separation distance from the first and second substrates for the third object. One such example of a third object may be an interposer that can provide connections to other chips.

[0045] After reflow, the solder on the reflow portion of the spacer region 130 is lower in height than the solder height in the contact region. Note that the amount of solder on both the contact region and the spacer region can be different according to the design, and the UBM dimension can also have different sizes (e.g., area). The relationship between the solder volume and the surface area of ​​the UBM can result in a defined profile, and therefore a certain height of the reflowed solder. When the second chip is placed in position on the bump, a defined gap is formed with the lower stop. Therefore, the height of the solder bump for bonding is controllable and can be completely different from the height of the lower stop. In one embodiment, due to its high aspect ratio, the fully reflowed spacer can be substantially incompressible. By not cleaning the lower stop after preparation, it may not be well bonded to anything. For example, if a non-bondable material such as bare silicon or silicon oxide is selected as the end face of the second chip surface, it can be maintained without bonding. More solder and less UBM area result in a more spherical bump higher than the lower stop. Less solder and / or a larger UBM results in a lower and flatter bottom stop.

[0046] Additional features of the methods and apparatus of the present disclosure are disclosed herein.

[0047] Example Embodiments

[0048] Figure 2 An example application 200 is shown for controlling chip gap and forming bump bonds using spacer regions consistent with the illustrative embodiments. A first substrate 205 having solder 215 thereon is formed after solder patterning on the UBM 220 and after reflow of a truncated sphere forming a bump bond 227. Figure 1A and 1B Same as shown.

[0049] The second substrate 255 having the UBM 260 to be connected to the bump bonding portion 227 is pressed onto the bump bonding portion 227. Although the bump bonding portion 227 is compressed by the second substrate 255, the lower stopper 217 disposed on the substrate 205 serves to separate the second substrate 255 from the first substrate 205 by a predetermined distance. This structure can prevent the bump bonding portion 227 from being compressed to the extent that it is damaged, or prevent the bump bonding portion 227 from causing a short circuit of the substrate 205.

[0050] The UBM pattern in the spacer region is larger than the UBM pattern in the contact region, and after reflow, the height of the solder on the reflow portion is lower than the height of the solder in the contact region. In other words, the solder area in the spacer region is wider and shallower than the solder area in the contact region. Note that the number of solders on both the contact region and the spacer region can be different according to the design, and the UBM dimensions can also have different sizes (areas). The relationship between the solder volume and the surface area of ​​the UBM will result in a defined profile and therefore the height of the solder. When the second chip is placed in contact with the lower stop, it can form a defined gap. Therefore, the height of the solder bump for bonding is controllable and can be completely different from the height of the spacer. Due to its high aspect ratio, the fully reflowed spacer will be substantially incompressible. In the case of not cleaning the lower stop after preparation, the lower stop cannot be bonded well to anything. If a non-bondable material including bare silicon or silicon oxide is selected as the end face of the second chip surface, the chip surface can be kept unbonded.

[0051] Another advantage of the bottom stop disposed at a predetermined distance between the first substrate 205 and the second substrate is to keep the distance between the substrates substantially uniform. Variations in the distance between the first substrate 205 and the second substrate 255 may adversely affect the performance of the operational parameters of the first substrate 205.

[0052] Additionally, the bottom stop may also control the spacing of a third substrate (eg, a chip) that may or may not be part of another pair of bonded chips.

[0053] Figure 2 The configuration in provides advantages over previous configurations in which the second substrate 255 is pressed downwardly to the first substrate 205 with a predetermined amount of force without using a bottom stop. For example, Figure 2 The illustrated configuration provides a more precise spacing between the first substrate 205 and the second substrate 255 without the need to perform complex alignment when connecting the substrates. Figure 2The illustrated construction also prevents possible damage caused by additional downward pressure that may be applied to the second substrate 255 by additional mechanical processing. For example, if a cover layer or heat sync is disposed on the upper surface of the second substrate 255, the lower stop will prevent changes in the gap that may occur based on additional mechanical processing to attach the cover layer or heat sync. In addition, it should be understood that although Figure 2 The bottom stop 217 shown appears to be arranged at one corner or one side of the space between the first substrate 205 and the second substrate 255, but there may be multiple bottom stops (e.g., at all four corners or other areas) between the first substrate 205 and the second substrate 255. The bottom stop (s) may be used to adjust for variations in planarity between the first substrate 205 and the second substrate 255.

[0054] Example Process

[0055] With the preceding overview of the example architecture, it may be helpful to now consider a high-level discussion of the example process. To this end, Figure 3 and Figure 4 3 are flow charts 300 , 400 illustrating methods of preparing a substrate consistent with various illustrative embodiments.

[0056] Figure 3 and 4 Shown as a collection of blocks in a logical order, it represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. In each process, the order in which the operations are described is not intended to be interpreted as a limitation, and any number of the described blocks can be combined in any order and / or executed in parallel to implement the process.

[0057] Figure 3 is a flow chart illustrating a method of preparing a substrate with a UBM by forming and patterning a UBM mask and substantially simultaneously depositing solder bumps and solder spacers, consistent with an illustrative embodiment.

[0058] At operation 302, a UBM mask is formed and patterned on a first substrate. For example, as shown in Figure 1, the UBM mask may have contact regions 130 and spacer regions 125. There may also be multiple spacer regions to create multiple bottom stops on the first substrate.

[0059] At operation 304, a UBM is deposited on the substrate. The UBM provides a metallization layer to connect the substrate to the bump keys. The UBM also provides a base for one or more bottom stops.

[0060] At operation 306, the UBM mask is removed, leaving the UBM pattern on the first substrate. Spacer regions 125 are arranged on the first substrate where the bottom stop will be created. Contact regions 130 are areas where bump keys are formed.

[0061] A patterned solder mask is deposited on the UBM at operation 308. Both the spacer area and the contact area may have solder deposited and reflowed to form the bottom stop and bump key simultaneously.

[0062] At operation 310, solder is deposited on both the spacer region and the bump (eg, contact) region, e.g. Figure 1A The solder mask is removed (operation 312) and the solder is reflowed (operation 314). The larger area of ​​the spacer helps create a lower stop with the reflowed solder, while the contact area causes the solder to form a truncated solder ball 127 (see Figure 1B ). The solder is reflowed above its solder melting temperature, and the reflowed solder wets the UBM surface. The UBM and solder patterning, followed by solder reflow, ends at operation 314. A second substrate (e.g., see Figure 2 ), the lower stop portion allows a space to exist between the first substrate and the second substrate. The second substrate may also have a UBM surface formed by a pattern matching the position of the bump bonding portion.

[0063] Figure 4 is a flow chart illustrating a method of preparing a substrate having a UBM by depositing a UBM metallization layer on the substrate through a patterning and etching process, consistent with an illustrative embodiment.

[0064] At operation 402, a UBM metallization layer is deposited on a substrate, and at operation 404, a UBM mask is formed and patterned on the substrate. The UBM mask is used to create spacer regions and contact regions for bump bonding.

[0065] At operation 406, the UBM metal is etched to form a pad. The pad may provide an electrical connection from the substrate to the bump bond.

[0066] At operation 408, the UBM mask is removed. At operation 410, a solder mask is patterned and deposited over the UBM. The solder provides material for both the bottom stop and the bump bonds, which can be created simultaneously.

[0067] At operation 412, solder is deposited on both the spacer region and the contact region. The area of ​​the spacer region may have a larger area than the area of ​​the contact region(s).

[0068] At operation 414, the solder mask is removed, and then the solder is reflowed to form one or more bottom stops in the spacer region and bump bonds in the contact region at operation 416. A second substrate having a UBM region can then be attached to the opposite portion of the bump bonds, with the bottom stops acting as spacers at a predetermined distance between the two substrates.

[0069] About the above Figure 3 and Figure 4 The method described in the flowchart of the embodiment is not exhaustive of the scope of the present disclosure. For example, the method may include other operations in addition to one or more operations, or replace one or more operations with other operations. For example, one or more solder bumps may have the same size, or some solder bumps may have different sizes. In addition, depositing solder bumps in the first UBM region and the second UBM region may include forming a solder structure on the surface of the substrate by depositing through a removable mold to control the solder volume. The removable mold may be a photosensitive resist. The solder bumps may be confined to a restricted area of ​​the substrate. The pattern of the bumps can be customized to increase a reliable contact area. The above operations are not exhaustive of the method operations that can be performed to manufacture the electronic structure shown and described herein.

[0070] Example Computer Platforms

[0071] As described above, one or more computing devices may be used to perform functions associated with controlling actions including creating a substrate including solder bumps and solder understops. Figure 5 A functional block diagram illustration of a computer hardware platform 500 that can be used to implement a specially configured computing device that can accommodate a welding engine 540 is provided. In particular, Figure 5 A network or host computer platform 500 is shown which may be used to implement a suitably configured server.

[0072] Computer platform 500 may include a central processing unit (CPU) 504 , a hard disk drive (HDD) 506 , random access memory (RAM) and / or read only memory (ROM) 508 , a keyboard 510 , a mouse 512 , a display 514 , and a communication interface 516 , which are connected to system bus 502 .

[0073] In one embodiment, the HDD 506 has the capability to include stored programs that can perform various operations in the manner described herein, such as a soldering engine 540. The soldering engine 540 can have various modules configured to perform different functions, such as those discussed in the context of the figures discussed herein. For example, the soldering engine 540 can include modules such as a plating control module 572, a vapor deposition control module 574, a pattern control module 576, some or all of which can be used to control the application of UBM regions to the substrate and the solder disposed on the UBM regions. The compression control module 578 can be configured to control the connection of the second substrate to the first substrate. Figure 5 The modules shown may be combined into several modules, and these modules are not exhaustive nor required to perform any particular operation.

[0074] Although modules 572 to 578 are Figure 5 506, but in some embodiments, one or more of these modules may be implemented in the hardware of the computing device 500. For example, the modules discussed herein may be implemented in the form of part hardware and part software. That is, Figure 5 One or more components of the welding engine 540 shown may be implemented in the form of electronic circuits having transistor(s), diode(s), capacitor(s), resistor(s), inductor(s), varactor(s), and / or memristor(s). In other words, the welding engine 540 may be implemented with one or more specially designed electronic circuits that perform the specific tasks and functions described herein. An artificial intelligence module for training and operating the process may also be included and participate in the preparation and operation of the manufacturing process.

[0075] in conclusion

[0076] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0077] Although the above has described what is considered to be the best state and / or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0078] The components, operations, steps, features, purposes, benefits, and advantages discussed herein are merely illustrative. None of them, or the discussion related to them, is intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise indicated, all measurements, values, rated values, positions, sizes, dimensions, and other performance specifications in this specification, including those set forth in the appended claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they are associated and the conventions of the field to which they belong.

[0079] Many other embodiments are also contemplated herein. These embodiments include embodiments with fewer, additional and / or different components, steps, features, purposes, benefits and advantages. These embodiments also include embodiments in which components are arranged and / or sequenced in different ways and / or steps are arranged and / or sequenced in different ways.

[0080] The flowcharts and diagrams in the figures herein illustrate the architecture, functionality, and operations of possible implementations according to various embodiments of the present disclosure.

[0081] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as immediately stated above, nothing stated or illustrated is intended or should be interpreted as causing any component, step, feature, object, benefit, advantage, or equivalent to be dedicated to the public, whether or not stated in the claims.

[0082] It should be understood that, unless specific meanings are elaborated in addition herein, the terms and expressions used herein have the common meanings consistent with these terms and expressions of respective investigation and research fields corresponding to them. Relational terms such as first and second etc. can be used only to distinguish one entity or action from another, without requiring or implying any such actual relationship or order between these entities or actions. The terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusions, so that the process, method, article or device comprising a series of elements not only include those elements, but also may include other elements that are not clearly listed or are inherent to such process, method, article or device. In the absence of further constraints, the element with "one" or "an" in front does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0083] The abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that it is not used to interpret or limit the scope or meaning of the claims. In addition, in the aforementioned detailed description, it can be seen that in order to make the present disclosure smooth, various features are grouped together in various embodiments. The method of the present disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than the features explicitly stated in each claim. On the contrary, as reflected in the attached claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are thereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

Claims

1. An electronic structure comprising: a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon; one or more solder bumps on the first UBM region; a bottom stop formed on the second UBM region, the bottom stop being wider, shallower and more rigid than any solder bump formed on the first UBM region; as well as a second substrate connected to the first substrate via the one or more solder bumps on the first UBM region, wherein a height of the bottom stop limits a distance between at least one of the first substrate and the second substrate, or a distance between an object and at least one of the first substrate and the second substrate.

2. The electronic structure according to claim 1, wherein: The object includes an interposer disposed at a predetermined distance from at least one of the first substrate and the second substrate; The first UBM region includes a contact region; The second UBM region includes a lower stop region; and An area of ​​the second UBM region is greater than an area of ​​the first UBM region.

3. An electronic structure according to any one of the preceding claims, wherein: a distance between the first substrate and the second substrate, or a distance between the object and at least one of the first substrate and the second substrate, based on a height of the second UBM region and limited by a height of the bottom stop; as well as The second substrate includes a third UBM region arranged to contact the one or more solder bumps.

4. The electronic structure according to claim 2, wherein: The solder on the first and second UBM regions is formed by at least one of evaporation or electroplating.

5. The electronic structure according to claim 2, wherein: The first UBM region and the second UBM region on the first substrate include pads.

6. The electronic structure according to claim 2, wherein: The first UBM region and the second UBM region include pads etched from metal.

7. The electronic structure of any one of the preceding claims, wherein the height of the bottom stop and the height of the one or more solder bumps are based on a volume of solder deposited in the first and second UBM regions and based on an area of ​​an under bump metallization layer in each of the first and second UBM regions.

8. The electronic structure of any one of the preceding claims, wherein the one or more solder bumps have the same size.

9. The electronic structure of any preceding claim, wherein at least some of the solder bumps comprise different sizes.

10. A method for preparing an electronic structure, comprising: applying a first under bump metallization (UBM) region and a second UBM region on the first substrate; depositing solder on the first UBM region and the second UBM region; reflowing the deposited solder and forming one or more solder bumps on the first UBM region and a bottom stop on the second UBM region; as well as A second substrate is connected to the first substrate via the one or more solder bumps located on the first UBM region, wherein a distance between at least one of the first substrate and the second substrate, or a distance between an object and at least one of the first substrate and the second substrate is based on a height of the second UBM region and is limited by a height of the bottom stop.

11. The method according to claim 10, wherein: The one or more solder bumps in the first UBM region and the bottom stop in the second UBM region are formed substantially simultaneously.

12. The method according to any one of the preceding claims 10 to 11, wherein: An area of ​​the second UBM region is greater than an area of ​​the first UBM region.

13. The method according to any one of the preceding claims 10 to 12, further comprising: Before connecting the second substrate to the first substrate, forming a third UBM region on the second substrate; as well as The third UBM region is arranged to contact the one or more solder bumps on the first substrate.

14. The method according to any one of the preceding claims 10 to 13, wherein: The solder of the solder bumps of the first UBM region and the second UBM region is deposited onto the first UBM region and the second UBM region by one or more of evaporation, electroplating and / or injection molding techniques.

15. The method according to any one of the preceding claims 10 to 14, wherein: The first UBM region and the second UBM region deposited on the first substrate each include a pad.

16. The method according to any one of the preceding claims 10 to 15, wherein: Applying the first UBM region and the second UBM region on the first substrate includes etching pads from metal.

17. The method according to any one of the preceding claims 10 to 16, further comprising determining a height of the bottom stop and a height of the one or more solder bumps based on a volume of solder deposited in the first UBM region and the second UBM region and an area of ​​an under bump metallization layer passing through each of the first UBM region and the second UBM region.

18. The method according to any one of the preceding claims 10 to 17, wherein: The one or more solder bumps located on the first UBM region have the same size.

19. The method according to any one of the preceding claims 10 to 18, wherein: Some of the solder bumps in the first UBM region have different sizes.

20. The method according to any one of the preceding claims 10 to 19, wherein: The deposition of solder bumps in the first UBM region and the second UBM region includes forming solder structures on the surface of the first substrate by controlled deposition of solder volume through a removable mold.

21. The method of claim 20, wherein the removable mold comprises a photoresist.

22. The method according to any one of the preceding claims 10 to 21, wherein: The solder bumps of the first UBM region are confined to a restricted area.

23. The method according to any one of the preceding claims 10 to 22, wherein: The solder bumps have the same size; and The pattern of the solder bumps is tailored to increase the reliable contact area.

24. The method according to any one of the preceding claims 10 to 23, wherein: Some of the solder bumps have different sizes, and wherein the pattern of the bumps is tailored to increase reliable contact area.

25. An electronic structure comprising: A first substrate having a first under bump metallization (UBM) region and a second UBM region, wherein the first UBM region has one or more solder bumps; a second substrate connected to the first substrate via the one or more solder bumps on the first UBM region; A lower stop is formed on the second UBM region, the lower stop having a surface area larger than a surface area of ​​the one or more solder bumps and a height configured to limit a distance between at least one of the first substrate and the second substrate or a distance between an object and at least one of the first substrate and the second substrate.

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