Laminated structure, method for manufacturing the same, and semiconductor device including the same

Abstract

A laminated structure (100) is provided with a buffer layer (106), a first semiconductor layer (108), and a second semiconductor layer (110). The buffer layer and the first semiconductor layer overlap each other in the vertical direction. The second semiconductor layer is in contact with a side surface of the first semiconductor layer, and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the vertical direction. Each of the first semiconductor layer and the second semiconductor layer contains a group III-V material or a group III nitride material. The crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

Description

Technical Field

[0001] One embodiment of the present invention relates to a stacked structure, a method for producing the stacked structure, and a semiconductor device including the stacked structure. Background Art

[0002] In recent years, the development of semiconductor devices using III-V materials or III-nitride materials as semiconductors has been actively carried out. In particular, inorganic materials containing gallium nitride (hereinafter referred to as gallium nitride materials) have a larger band gap than other semiconductor materials such as silicon and oxide semiconductors, and have higher insulation breakdown electric fields and saturation drift velocities. Therefore, by using gallium nitride materials in the active layer, it is possible to obtain semiconductor devices with excellent characteristics, and more attention has been paid to gallium nitride materials (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2017 / 155032 Summary of the invention

[0006] Problems to be solved by the invention

[0007] One of the technical solutions of the present invention is to provide a novel stacked structure comprising a III-V material or a III-nitride material, especially a gallium nitride material, and a method for making the same. Alternatively, one of the technical solutions of the present invention is to provide a stacked structure comprising a III-V material or a III-nitride material, especially a gallium nitride material, and a method for making the same, with a controlled structure. Alternatively, one of the technical solutions of the present invention is to provide a semiconductor device comprising the stacked structure.

[0008] Means used to solve problems

[0009] One of the technical solutions of the present invention is a stacked structure. The stacked structure includes a buffer layer, a first semiconductor layer and a second semiconductor layer. The buffer layer and the first semiconductor layer overlap each other in the vertical direction. The second semiconductor layer is in contact with the side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the vertical direction. The first semiconductor layer and the second semiconductor layer respectively contain a III-V material or a III-nitride material. The crystallinity of the first semiconductor layer is higher than that of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

[0010] One of the technical solutions of the present invention is a semiconductor device including a stacked structure. The stacked structure includes a buffer layer, a first semiconductor layer and a second semiconductor layer. The buffer layer and the first semiconductor layer overlap each other in the vertical direction. The second semiconductor layer is in contact with the side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the vertical direction. The first semiconductor layer and the second semiconductor layer each include a III-V material or a III-nitride material. The crystallinity of the first semiconductor layer is higher than that of the second semiconductor layer. The buffer layer is exposed from the second semiconductor layer in the vertical direction.

[0011] One of the technical solutions of the present invention is a method for manufacturing a stacked structure. The manufacturing method includes: forming a buffer layer on a substrate; forming a semiconductor layer including gallium nitride on the buffer layer in a manner that covers the buffer layer; and etching the semiconductor layer. The semiconductor layer is etched in a manner that a first portion overlapping with the buffer layer in the vertical direction and a second portion not overlapping with the buffer layer remain. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A It is a schematic plan view of a stacked structure according to an embodiment of the present invention.

[0013] Figure 1B This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0014] Figure 2A This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0015] Figure 2B This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0016] Figure 3A This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0017] Figure 3B This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0018] Figure 3C This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0019] Figure 4 This is a schematic end view of a stacked structure according to an embodiment of the present invention.

[0020] Figure 5A This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0021] Figure 5B This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0022] Figure 5C This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0023] Figure 5D This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0024] Fig. 6A This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0025] Figure 6B This is a schematic end view showing a method for producing a stacked structure according to an embodiment of the present invention.

[0026] Fig. 7A This is a schematic end view of a semiconductor device according to an embodiment of the present invention.

[0027] Figure 7B It is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0028] Fig. 8A This is a schematic end view of a semiconductor device according to an embodiment of the present invention.

[0029] Figure 8B This is a schematic end view of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from the gist of the present invention, and is not to be construed as being limited to the description of the embodiments illustrated below.

[0031] In order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared with the actual form, but this is only an example and does not limit the interpretation of the present invention. In this specification and each figure, for elements having the same function as the elements described in the previous drawings, there are cases where the same mark is given and repeated description is omitted. This mark is used when multiple identical or similar structures are generally represented, and a hyphen and a natural number are added after the mark when they are represented separately.

[0032] In the present specification and claims, when expressing a form in which another structure is arranged on top of a certain structure, when it is simply expressed as "above", unless otherwise stated, it includes both the case in which the other structure is arranged directly above the certain structure in a manner connected to the certain structure, and the case in which the other structure is arranged above the certain structure with another structure in between.

[0033] In this specification and claims, the expression "a certain structure is exposed from another structure" means a state where a part of a certain structure is not covered by another structure, and the part not covered by another structure also includes a state where it is covered by another structure. In addition, the state represented by this expression also includes a state where a certain structure is not in contact with another structure.

[0034] In the embodiment of the present invention, when a plurality of films are formed simultaneously in the same process, these films have the same layer structure, the same material, and the same composition, and therefore, are defined as being present in the same layer.

[0035] <First Embodiment>

[0036] In this embodiment, the structure of a stacked structure 100 and a method for producing the stacked structure 100 as one embodiment of the present invention will be described.

[0037] 1. Structure of the stacked structure

[0038] exist Figure 1A A schematic top view of the stacked structure 100 is shown in FIG. Figure 1B Indicates along Figure 1A Schematic diagram of the end face of the dotted line A-A'. As shown in these figures, the stacked structure 100 includes a buffer layer 106, a first semiconductor layer 108, and a second semiconductor layer 110 as a basic structure. The stacked structure 100 can be arranged on a substrate 102, and an undercoat 104 can be provided between the stacked structure 100 and the substrate 102 as an arbitrary structure. The first semiconductor layer 108 and the second semiconductor layer 110 include a III-V material or a III-nitride material, and the details will be described later. As an example of a III-V material or a III-nitride material, a gallium nitride-based material is used for illustration in this embodiment.

[0039] 1-1. Buffer layer

[0040] The buffer layer 106 is a layer having the function of promoting the crystallization of the first semiconductor layer formed thereon, and can include metals such as titanium, aluminum, silver, nickel, copper, strontium, rhodium, palladium, iridium, platinum, gold, metal nitrides such as titanium nitride, or metal oxides such as zinc oxide, etc. Since these elements or compounds have conductivity, the buffer layer 106 can also function as an electrode.

[0041] It is preferable to use a material including a crystal structure in which the c-axis is not orthogonal to the a-axis and the b-axis at 90°, i.e., a close-packed hexagonal structure or a structure similar thereto, as exemplified by titanium, zinc oxide, etc. When the buffer layer 106 is formed of such a material, the c-axis of the buffer layer 106 is oriented with respect to the surface on which the buffer layer 106 is provided (at Figure 1A and Figure 1B In the example shown, the first semiconductor layer 108 is oriented in a direction perpendicular or substantially perpendicular to the surface of the substrate 102. On the other hand, it is known that the gallium nitride material contained in the first semiconductor layer 108 adopts a hexagonal structure such as a wurtzite structure, and grows crystals in the c-axis direction to minimize its surface energy. Therefore, by forming the buffer layer 106 with a material having a close-packed hexagonal structure or a structure similar to them, and forming the first semiconductor layer 108 containing the gallium nitride material overlapping with the buffer layer 106, the first semiconductor layer 108 is affected by the crystal structure of the buffer layer 106 and grows crystals in the c-axis direction. As a result, the first semiconductor layer 108 can have a c-axis orientation with high crystallinity.

[0042] In order to more effectively grow the first semiconductor layer 108 in the c-axis direction, it is preferred that the surface flatness of the buffer layer 106 is higher. Specifically, the arithmetic mean roughness (Ra) of the surface of the buffer layer 106 is preferably less than 2.3 nm. In addition, the root mean square roughness (Rq) of the surface of the buffer layer 106 is preferably less than 2.9 nm. In order to obtain a higher flatness of the surface, the thickness of the buffer layer 106 is preferably 50 nm or less, for example, the buffer layer 106 is formed with a thickness of 10 nm or more and 50 nm or less.

[0043] 1-2. First semiconductor layer and second semiconductor layer

[0044] The first semiconductor layer 108 and the second semiconductor layer 110 both contain III-V materials or III-nitride materials, and in particular, gallium nitride materials are used for illustration. As gallium nitride materials, for example, semiconductors containing nitrogen and gallium such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN) can be cited. The composition ratio of nitrogen to gallium can deviate from the stoichiometric composition. The first semiconductor layer 108 and the second semiconductor layer 110 may also contain other elements. For example, the first semiconductor layer 108 and the second semiconductor layer 110 may contain one or more of silicon, germanium, magnesium, zinc, cadmium, beryllium, indium, aluminum, arsenic and the like. By adding these elements, the valence electrons of the first semiconductor layer 108 and the second semiconductor layer 110 can be controlled, which can not only maintain the intrinsic (i-type), but also achieve the control of the band gap, the provision of p-type or n-type conductivity, etc.

[0045] like Figure 1A , Figure 1BAs shown, the first semiconductor layer 108 is located above the buffer layer 106 and is in contact with the upper surface of the buffer layer 106. On the other hand, the second semiconductor layer 110 is not in contact with the upper surface of the buffer layer 106 and does not overlap with the buffer layer 106. That is, the buffer layer 106 is exposed from the second semiconductor layer 110 in the up-down direction. The second semiconductor layer 110 is in contact with the side surface of the buffer layer 106 and surrounds at least a portion or the entirety of the first semiconductor layer 108 in a plane perpendicular to the up-down direction. Therefore, as described above, the first semiconductor layer 108 is greatly affected by the crystal structure of the buffer layer 106, and crystal growth occurs preferentially in the c-axis direction during formation. However, compared with the first semiconductor layer 108, the second semiconductor layer 110 is less likely to be affected by the crystal structure of the buffer layer 106. Therefore, the crystallinity of the first semiconductor layer 108 is higher than that of the second semiconductor layer 110. For example, in electron beam analysis, the first semiconductor layer 108 has a sharper peak (a smaller half-value width) than the second semiconductor layer 110 .

[0046] The thickness of the first semiconductor layer 108 and the second semiconductor layer 110 is appropriately set according to the application of the stacked structure 100. However, as described later, the first semiconductor layer 108 and the second semiconductor layer 110 are formed simultaneously. Therefore, the composition and thickness of the first semiconductor layer 108 and the second semiconductor layer 110 can be made the same or substantially the same.

[0047] 1-3. Substrate and primer

[0048] There is no restriction on the material contained in the substrate 102. For example, an amorphous glass substrate, a quartz substrate, a sapphire substrate, a silicon substrate, or a substrate containing a polymer such as polyimide, polyamide, or acrylic resin can be used as the substrate 102. Alternatively, a metal substrate such as stainless steel can also be used. There is no restriction on the crystallinity of the substrate 102. Either a single crystal substrate or an amorphous substrate can be used. The substrate 102 can be flexible.

[0049] The undercoat layer 104 of any structure is an electrically insulating film, and can contain aluminum oxide, etc., in addition to silicon-containing inorganic compounds such as silicon nitride and silicon oxide. The undercoat layer 104 can have a single-layer structure, or can be composed of multiple layers of different components. For example, a laminate of a film containing silicon oxide and a film containing silicon nitride can be used as the undercoat layer 104.

[0050] 2. Modifications

[0051] The structure of the stacked structure 100 is not limited to the above structure. Figure 2A , Figure 2BAs shown in FIG. 1 , the second semiconductor layer 110 has a tapered shape. That is, the side surface of the second semiconductor layer 110 away from the first semiconductor layer 108 may be inclined from the vertical direction. In this case, the thickness of the second semiconductor layer 110 may decrease as the distance from the first semiconductor layer 108 increases in a plane perpendicular to the vertical direction ( Figure 2A ) or increase ( Figure 2B ). Alternatively, you can Figure 3A , Figure 3C As shown in FIG. 1 , a part or the entire side surface of the first semiconductor layer 108 is exposed from the second semiconductor layer 110. Alternatively, Figure 3B , Figure 3C As shown, a part or the whole of the side surface of the buffer layer 106 is exposed from the second semiconductor layer 110. The shape of the second semiconductor layer 110 can be controlled by appropriately adjusting the etching conditions.

[0052] In the stacked structure 100, the first semiconductor layer 108 and the second semiconductor layer 110 may both have a single-layer structure, or may have a plurality of layers. Figure 4 When a plurality of layers are stacked, there is no restriction on the number of layers, and the number of layers can be appropriately selected from a range of 2 to 10. Figure 4 In the example shown, the first semiconductor layer 108 is composed of semiconductor layers 108-1, 108-2, 108-3, and 108-4, and the second semiconductor layer 110 is also composed of semiconductor layers 110-1, 110-2, 110-3, and 110-4. When a plurality of layers are stacked, the composition of each layer can be appropriately changed so that the conductivity is different between the layers. For example, the first semiconductor layer 108 and the second semiconductor layer 110 can be appropriately formed using a semiconductor layer containing p-type gallium nitride, a semiconductor layer containing p-type aluminum gallium nitride, a semiconductor layer containing n-type gallium nitride, and a semiconductor layer containing n-type aluminum gallium nitride. As described above, the first semiconductor layer 108 and the second semiconductor layer 110 are formed simultaneously in the same process. Therefore, the stacked structures of the first semiconductor layer 108 and the second semiconductor layer 110 can also be made the same. For example, the number, structure, thickness, etc. of stacked layers can be made the same between the first semiconductor layer 108 and the second semiconductor layer 110 .

[0053] 3. Method for producing a laminated structure

[0054] Below, use FIG. 5A to FIG. 6B illustrate Figure 1A and Figure 1B An example of a method for producing the stacked structure 100 is shown.

[0055] First, a primer layer 104 ( Figure 5A). The base coat layer can be formed by chemical vapor deposition (CVD) or sputtering. Alternatively, in the case of using a silicon substrate or a metal substrate, an oxide layer formed by oxidizing the surface can be used as the base coat layer 104. In this case, a layer containing a silicon-containing inorganic compound or the like can also be stacked on the oxide layer. In addition, this process is not required when the base coat layer 104 is not provided.

[0056] Next, a buffer layer 106 is formed directly on the substrate 102 or through the base layer 104 ( Figure 5B The buffer layer 106 may be formed by sputtering using a target containing a metal contained therein. Alternatively, the buffer layer 106 may be formed by vapor deposition, CVD, or the like. The patterning of the buffer layer 106 is performed by applying known photolithography.

[0057] Next, the first semiconductor layer 108 and the second semiconductor layer 110 are formed simultaneously. Specifically, a sputtering method using a sintered body of gallium nitride as a sputtering target is applied to form a semiconductor layer 105 (5C) containing a gallium nitride-based material on the upper surface of the substrate 102. Examples of the sputtering method include bipolar sputtering, magnetron sputtering, dual magnetron sputtering, opposing target sputtering, ion beam sputtering, and inductively coupled plasma (ICP) sputtering. In the case where the substrate 102 is an amorphous glass substrate, the semiconductor layer 105 that becomes the first semiconductor layer 108 and the second semiconductor layer 110 can be formed on the buffer layer 106 by sputtering at a temperature below 600°C. As a result, the semiconductor device described later including the stacked structure 100 can be formed at low cost on a large amorphous glass substrate.

[0058] At this time, the semiconductor layer 105 is formed in a manner covering the buffer layer 106. That is, the semiconductor layer 105 is formed so that the entire upper surface of the buffer layer 106 overlaps with the semiconductor layer 105 so that the buffer layer 106 is not exposed from the semiconductor layer 105. As described above, the c-axis of the buffer layer 106 is oriented in a direction vertical or substantially vertical to the surface on which the buffer layer 106 is provided (here, the surface of the substrate 102 or the undercoat layer 104). Therefore, the crystal structure of the buffer layer 106 promotes the crystal growth of the semiconductor layer 105 formed thereon. As a result, during the film formation process of the semiconductor layer 105, in the portion of the semiconductor layer 105 that overlaps with the buffer layer 106, the crystal growth in the c-axis direction is promoted. On the other hand, with respect to the portion of the semiconductor layer 105 that does not overlap with the buffer layer 106, the influence of the crystal structure of the buffer layer 106 is small, and the degree of crystal growth is smaller than that of the portion that overlaps with the buffer layer 106. Due to the crystal growth promotion function of the buffer layer 106, the first semiconductor layer 108 with high crystallinity and the second semiconductor layer 110 with lower crystallinity than the first semiconductor layer 108 are formed simultaneously. Figure 5D). Therefore, the first semiconductor layer 108 and the second semiconductor layer 110 can exist in the same layer and have the same composition and structure.

[0059] Then, patterning is performed by etching. Specifically, Fig. 6A As shown, a resist mask 112 is formed on the first semiconductor layer 108 and the second semiconductor layer 110. The formation of the resist mask 112 can be carried out by applying a known method. At this time, the shape of the resist mask 112 is determined according to the characteristics required for the stacked structure 100, and is set to cover the first semiconductor layer 108 and cover a portion of the second semiconductor layer 110. More specifically, the resist mask 112 is set so that the first semiconductor layer 108 is not exposed from the resist mask 112, the entire upper surface of the first semiconductor layer 108 overlaps with the resist mask 112, and the portion in contact with the second semiconductor layer 110 surrounds the first semiconductor layer 108 when viewed from above. In other words, the resist mask 112 is set to cover the buffer layer 106, overlap with the entire upper surface of the buffer layer 106, and the portion in contact with the second semiconductor layer 110 surrounds the buffer layer 106 when viewed from above.

[0060] Then, the second semiconductor layer 110 is etched through the resist mask 112. Etching can be either dry etching or wet etching. Chlorine-based dry etching can be applied to dry etching. By etching, the portion not covered by the resist mask 112 is removed. As a result, a portion of the second semiconductor layer 110 with relatively low crystallinity and not overlapping the buffer layer 106 remains, and in a plane perpendicular to the up-down direction, the remaining portion is formed into a shape that surrounds at least a portion or the entirety of the first semiconductor layer 108 ( Figure 6B ). Then, by removing the resist mask 112, a Figure 1A , Figure 1B The stacked structure 100 is shown.

[0061] As described above, the first semiconductor layer 108 has higher crystallinity than the second semiconductor layer 110 and therefore has higher etching tolerance than the second semiconductor layer 110. Therefore, when the resist mask 112 is formed so as to expose a portion of the first semiconductor layer 108 and the first semiconductor layer 108 is also etched, more severe etching conditions and longer etching time are required, and damage such as side etching may occur in the first semiconductor layer 108.

[0062] In contrast, according to the method for manufacturing the stacked structure 100 of one embodiment of the present invention, etching is performed through the resist mask 112 that covers not only the first semiconductor layer 108 but also the second semiconductor layer 110 surrounding it, so that the second semiconductor layer 110 remains in a manner that surrounds at least a portion or the entirety of the first semiconductor layer 108. That is, only the second semiconductor layer 110 is removed by etching. Therefore, it is possible to select the most suitable mild conditions for etching the second semiconductor layer 110, so that the occurrence of damage can be suppressed to a minimum. As a result, it is possible to manufacture the stacked structure 100 containing gallium nitride-based materials with precisely controlled structure and characteristics.

[0063] <Second Embodiment>

[0064] In this embodiment, a semiconductor device including the stacked structure 100 described in the first embodiment is described. The description of the same or similar structure as that described in the first embodiment may be omitted.

[0065] There are no particular restrictions on the semiconductor device including the stacked structure 100, and examples thereof include transistors (thin film transistors, power transistors), light-emitting elements including laser elements, optical sensors including image sensors, solar cell units, various diodes including constant voltage diodes and variable capacitance diodes, piezoelectric elements, etc.

[0066] As an example, in Fig. 7A A schematic top view of a transistor 120 including a stacked structure 100 is shown in FIG. Figure 7B Indicates along Fig. 7A Schematic diagram of the end face of the dotted line BB'. When the stacked structure 100 is applied to a transistor, a portion of the first semiconductor layer 108 of the stacked structure 100 functions as an active layer (channel). As shown in these figures, the transistor 120 is directly provided on the substrate 102 or provided on the substrate 102 via the primer layer 104, and includes: the stacked structure 100, including the buffer layer 106, the first semiconductor layer 108 and the second semiconductor layer 110; the gate insulating film 122 on the stacked structure 100; the gate electrode 124, overlapping the stacked structure 100 via the gate insulating film 122; the interlayer insulating film 126, covering the gate insulating film 122; and the source / drain electrode 128, electrically connected to the first semiconductor layer 108 via the opening provided in the interlayer insulating film 126. Although not shown in the drawings, the transistor 120 may further include a protective insulating film covering the source / drain electrodes 128 and the interlayer insulating film 126 . Fig. 7A , Figure 7BThe transistor 120 shown is a so-called top-gate transistor. Although not shown, the transistor 120 may be a bottom-gate transistor or a dual-gate transistor having a pair of gate electrodes on the upper and lower sides of the stacked structure 100 .

[0067] The transistor 120 including the stacked structure 100 is particularly expected to exhibit excellent characteristics as a power transistor due to the large band gap, high dielectric breakdown electric field, and large saturation drift velocity of gallium nitride materials. In addition, by applying the method for manufacturing the stacked structure 100 of one embodiment of the present invention, the structure and characteristics of the stacked structure 100 can be precisely controlled, so the transistor 120 with controlled characteristics can also be realized. In addition, by forming the stacked structure 100 on the substrate 102 including amorphous glass by sputtering, a semiconductor device including the stacked structure 100 can be provided at low cost.

[0068] As another example, in Fig. 8A , a schematic end view of an electroluminescent light-emitting element 130 including a stacked structure 100 is shown. The light-emitting element 130 includes a lower electrode 132, the stacked structure 100 on the lower electrode 132, and an upper electrode 136 on the stacked structure 100. The light-emitting element 130 may further include an insulating film 134 covering the end of the stacked structure 100. At this time, when the buffer layer 106 has conductivity, the buffer layer 106 also functions as an electrode together with the lower electrode 132.

[0069] The first semiconductor layer 108 and the second semiconductor layer 110 of the stacked structure 100 have a stacked structure suitable for recombination of charges injected from the lower electrode 132 and the upper electrode 136 and conversion into photons. For example, the first semiconductor layer 108 and the second semiconductor layer 110 may be composed of semiconductor layers 108-1 and 110-1 containing a gallium nitride material having p-type conductivity, semiconductor layers 108-3 and 110-3 containing a gallium nitride material having n-type conductivity, and semiconductor layers 108-2 and 110-2 containing intrinsic gallium nitride or a gallium nitride material containing one or more elements selected from indium, aluminum, phosphorus, and arsenic. In such a structure, the semiconductor layers 108-1 and 110-1 function as electron transport layers or hole transport layers, the semiconductor layers 108-3 and 110-3 function as hole transport layers or electron transport layers, and the semiconductor layers 108-2 and 110-2 function as light emitting layers. Holes are injected from the lower electrode 132 through the semiconductor layers 108-1 and 110-1. On the other hand, electrons are injected from the upper electrode 136 through the semiconductor layers 108-3 and 110-3. Electrons and holes recombine in the semiconductor layers 108-2 and 110-2 to form an excited state, and light is emitted when they return to the ground state.

[0070] exist Fig. 8A In the embodiment, the lower electrode 132 is provided in a manner overlapping with the second semiconductor layer 110 and in contact with the second semiconductor layer 110. Therefore, when the lower electrode 132 has a function of promoting crystallization of the layer containing the gallium nitride-based material, as shown in FIG. Figure 8B As shown, it is preferred to provide a wiring 138 on the substrate 102 and form an insulating film 140 thereon. The insulating film 140 may be formed of, for example, polyimide, acrylic resin, epoxy resin, polysiloxane resin, or the like. An opening that reaches the wiring 138 is provided in the insulating film 140, and the buffer layer 106 is formed in a manner covering the opening. Thus, since the second semiconductor layer 110 is provided on the insulating film 140 that does not have the function of promoting its crystallization, it is possible to selectively improve the crystallinity of only the first semiconductor layer 108. In addition, the wiring 138 may also be electrically connected to a semiconductor element such as a transistor provided on the substrate 102. Thus, the conduction (on) and cutoff (off) of the light-emitting element 130 can be switched by the transistor.

[0071] As a field-induced luminescence type light-emitting element, an organic electroluminescent element is known. Organic electroluminescent elements deteriorate relatively quickly because they contain organic compounds in the electron transport layer, the hole transport layer, and the light-emitting layer. On the other hand, inorganic compounds such as gallium nitride materials deteriorate at a rate that is negligible compared to organic compounds. Therefore, by utilizing the light-emitting element 130, various light-emitting devices and display devices with high reliability can be obtained. In addition, by applying the method for manufacturing the stacked structure 100 of one of the embodiments of the present invention, the structure and characteristics of the stacked structure 100 can be precisely controlled, so it is also possible to realize a light-emitting element 130 with controlled characteristics and a light-emitting device and display device including it.

[0072] As embodiments of the present invention, the above-mentioned embodiments can be appropriately combined and implemented as long as they are not contradictory. In addition, those skilled in the art who appropriately add, delete or change the design of the display device of each embodiment, or add, omit or change the process, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0073] Even if there are other effects different from the effects brought about by the forms of the above-mentioned embodiments, it should be understood that the effects that are obvious from the description of this specification or the effects that can be easily predicted by those skilled in the art are brought about by the present invention.

[0074] Marking Description

[0075] 100: stacked structure; 102: substrate; 104: primer layer; 105: semiconductor layer; 106: buffer layer; 108: first semiconductor layer; 108-1: semiconductor layer; 108-2: semiconductor layer; 108-3: semiconductor layer; 108-4: semiconductor layer; 110: second semiconductor layer; 112: resist mask; 120: transistor; 122: gate insulating film; 124: gate electrode; 126: interlayer insulating film; 128: drain electrode; 130: light emitting element; 132: lower electrode; 134: insulating film; 136: upper electrode; 138: wiring; 140: insulating film.

Claims

1. A stacked structure, characterized in that: have: a buffer layer and a first semiconductor layer overlapping each other in a vertical direction; and a second semiconductor layer, which is in contact with a side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the up-down direction; The first semiconductor layer and the second semiconductor layer respectively include a Group III-V material or a Group III nitride material; The crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer; The buffer layer is exposed from the second semiconductor layer in the up-down direction.

2. The stacked structure according to claim 1, wherein: The buffer layer and the second semiconductor layer do not overlap in the up-down direction.

3. The stacked structure according to claim 1, wherein: The second semiconductor layer is in contact with a side surface of the buffer layer.

4. The stacked structure according to claim 1, wherein: The second semiconductor layer surrounds the entire first semiconductor layer in the plane.

5. The stacked structure according to claim 1, wherein: A side surface of the second semiconductor layer that is separated from the first semiconductor layer is inclined with respect to the up-down direction.

6. The stacked structure according to claim 5, wherein: The thickness of the second semiconductor layer decreases as the distance from the first semiconductor layer in the plane increases.

7. The stacked structure according to claim 5, wherein: The thickness of the second semiconductor layer increases as the distance from the first semiconductor layer in the plane increases.

8. A semiconductor device having a stacked structure, characterized in that: The above-mentioned stacked structure comprises: a buffer layer and a first semiconductor layer overlapping each other in a vertical direction; and a second semiconductor layer, which is in contact with a side surface of the first semiconductor layer and surrounds at least a portion of the first semiconductor layer in a plane perpendicular to the up-down direction; The first semiconductor layer and the second semiconductor layer respectively include a Group III-V material or a Group III nitride material; The crystallinity of the first semiconductor layer is higher than the crystallinity of the second semiconductor layer; The buffer layer is exposed from the second semiconductor layer in the up-down direction.

9. The semiconductor device according to claim 8, wherein: The buffer layer and the second semiconductor layer do not overlap in the up-down direction.

10. The semiconductor device according to claim 8, wherein The second semiconductor layer is in contact with a side surface of the buffer layer.

11. The semiconductor device according to claim 8, wherein The second semiconductor layer surrounds the entire first semiconductor layer in the plane.

12. The semiconductor device according to claim 8, wherein A side surface of the second semiconductor layer that is separated from the first semiconductor layer is inclined with respect to the up-down direction.

13. The semiconductor device according to claim 12, wherein: The thickness of the second semiconductor layer decreases as the distance from the first semiconductor layer in the plane increases.

14. The semiconductor device according to claim 12, wherein: The thickness of the second semiconductor layer increases as the distance from the first semiconductor layer in the plane increases.

15. The semiconductor device according to claim 8, wherein The semiconductor device is selected from a transistor, a light emitting element, a photosensor and a solar cell.

16. A method for manufacturing a stacked structure, characterized in that: include: forming a buffer layer on a substrate; forming a semiconductor layer including gallium nitride on the buffer layer so as to cover the buffer layer; and etching the semiconductor layer; The semiconductor layer is etched so that a first portion overlapping with the buffer layer in a vertical direction and a second portion not overlapping with the buffer layer remain.

17. The method of claim 16, wherein: The semiconductor layer is etched so that the second portion surrounds the first portion in a plane perpendicular to the up-down direction.

18. The method of claim 16, wherein: The semiconductor layer is formed by sputtering.

19. The method of claim 16, wherein: The semiconductor layer is etched so that a side surface of the semiconductor layer is inclined with respect to the up-down direction.

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