Detection circuit, chip and equipment

Abstract

The invention relates to the technical field of electronic circuits, and discloses a detection circuit, a chip and equipment. In the circuit, a bias module copies a first mirror current and a second mirror current to a reference module and a comparison module respectively; the current obtained by the first mirror current flowing through a first reference resistor unit in the reference module to generate voltage drop is used as the pull-down current of the target node, and the current obtained by the second mirror current flowing through a resistor unit to be detected in the comparison module to generate voltage drop is used as the pull-up current of the target node; the size of the resistor to be measured relative to the first reference resistor can be determined by comparing the pull-up current and the pull-down current, and a voltage comparison circuit does not need to be additionally deployed; and based on increasing the copy proportion of the first mirror current and the second mirror current, the size of the resistor to be measured relative to the first reference resistor can be relatively and equivalently enlarged, the comparison precision is improved to ensure the accuracy of the circuit output result, elements such as an amplifier do not need to be additionally deployed, and the occupied area of a chip is relatively reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a detection circuit, chip and device. Background Art

[0002] The resistance of variable resistors such as thermistors, photoresistors and varistors can change accordingly with changes in environmental conditions (such as temperature, light intensity, pressure, etc.). For example, in an electronic device that uses a varistor to wake up the screen, when the user touches the screen of the electronic device to apply pressure, the resistance of the varistor increases to output a control signal, thereby driving the screen to wake up. The resistance of the variable resistor is usually determined by setting a fixed resistor, for example, the size of the variable resistor relative to the fixed resistor is determined by the voltage drop of the current flowing through the fixed resistor and the variable resistor.

[0003] However, determining the resistance of a variable resistor by means of voltage drop usually requires the deployment of an additional voltage comparison circuit. In particular, when the resistance of the variable resistor is slightly different from that of the fixed resistor, it may be necessary to deploy amplifiers and other components in the voltage comparison circuit to amplify the voltage for comparison, which occupies a large chip area and is not conducive to chip design. Summary of the invention

[0004] The embodiments of the present application provide a detection circuit, a chip and a device.

[0005] In a first aspect, the present application provides a detection circuit, which includes: a bias module, a reference module and a comparison module, wherein the bias module is used to provide a first mirror current and a second mirror current to the reference module and the comparison module respectively; the reference module includes a first reference resistor unit, and the reference module is used to provide a pull-down current to a target node in the comparison module based on the first mirror current and the first reference resistor unit; the comparison module includes a resistance unit to be measured, and the comparison module is used to provide a pull-up current to the target node in the comparison module based on the second mirror current and the resistance unit to be measured, wherein the pull-up current and the pull-down current of the target node are used to determine the output result of the detection circuit.

[0006] In the embodiment of the present application, the resistance relationship between the resistor to be measured and the first reference resistor can be determined based on current comparison, without the need to deploy an additional voltage comparison circuit, thus saving chip area.

[0007] In a possible implementation of the first aspect above, the detection circuit determines the output result based on the following method: when the resistance value of the resistance unit to be measured is less than the resistance value of the first reference resistance unit, the current value of the pull-up current is less than the current value of the pull-down current, and the output result of the detection circuit is a low-level signal; when the resistance value of the resistance unit to be measured is greater than the resistance value of the first reference resistance unit, the current value of the pull-up current is greater than the current value of the pull-down current, and the output result of the detection circuit is a high-level signal.

[0008] In a possible implementation of the first aspect, the resistance unit to be measured includes at least any one of the following resistors: a thermistor, a photoresistor, a varistor, and an electric fuse.

[0009] In a possible implementation of the first aspect above, the bias module includes a first mirror unit, the reference module includes a second mirror unit, and the comparison module includes a third mirror unit, wherein the first mirror unit and the second mirror unit form a first current mirror branch, and the first mirror unit and the third mirror unit form a second current mirror branch; the bias module is used to provide a first mirror current to the reference module based on the first current mirror branch, the first mirror current flows through the first reference resistance unit to generate a first voltage drop so that the current flowing through the second mirror unit is the first current, and the first current is used as a pull-down current of a target node in the comparison module; the bias module is used to provide a second mirror current to the comparison module based on the second current mirror branch, the second mirror current flows through the resistance unit to be measured to generate a second voltage drop so that the current flowing through the third mirror unit is the second current, and the second current is used as a pull-up current of the target node.

[0010] In a possible implementation of the first aspect, the first mirror unit includes a first MOS transistor, the second mirror unit includes a second MOS transistor, the third mirror unit includes a third MOS transistor, the bias module includes a second reference resistor unit and a reference current source, and the second reference resistor unit has the same resistance as the first reference resistor unit; one end of the second reference resistor unit is connected to the output end of the power supply voltage, the other end of the second reference resistor unit is connected to the source of the first MOS transistor, one end of the first reference resistor unit is connected to the output end of the power supply voltage, the other end of the first reference resistor unit is connected to the source of the second MOS transistor, one end of the resistance unit to be measured is connected to the output end of the power supply voltage, the other end of the resistance unit to be measured is connected to the source of the third MOS transistor, and the source of the first MOS transistor is connected to the gate of the first MOS transistor, and the gate of the first MOS transistor is respectively connected to the gate of the second MOS transistor and the gate of the third MOS transistor, so that the first MOS transistor and the second MOS transistor form a first current mirror branch and provide a first mirror current to the bias module through the first current mirror branch, and the first MOS transistor and the third MOS transistor form a second current mirror branch and provide a second mirror current to the comparison module through the second current mirror branch.

[0011] In a possible implementation of the first aspect, the reference module includes a fourth MOS tube and a fifth MOS tube, and the comparison module includes a sixth MOS tube and a seventh MOS tube; the drain of the fourth MOS tube is connected to the drain of the second MOS, the source of the fourth MOS tube is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the ground terminal, the drain of the sixth MOS tube is connected to the drain of the third MOS tube, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, the source of the seventh MOS tube is connected to the ground terminal, and the gate of the fourth MOS tube is connected to the gate of the sixth MOS tube, and the gate of the fourth MOS tube and the gate of the sixth MOS tube are provided with a second driving voltage, the gate of the fifth MOS tube is connected to the gate of the seventh MOS tube, and the gate of the fifth MOS tube and the gate of the seventh MOS tube are both connected to the drain of the fourth MOS tube, so that the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube form a third current mirror branch, and the reference module provides the first current to the comparison module through the third current mirror branch, so that the first current is used as a pull-down current of the target node.

[0012] In a possible implementation of the first aspect, the ratio of the channel width-to-length ratios of the first MOS tube, the second MOS tube, and the third MOS tube is 1:1:1; the ratio of the channel width-to-length ratios of the fourth MOS tube and the sixth MOS tube is 1:1; and the ratio of the channel width-to-length ratios of the fifth MOS tube and the seventh MOS tube is 1:1.

[0013] In a possible implementation of the first aspect, the ratio of the channel width-to-length ratios of the first MOS tube, the second MOS tube, and the third MOS tube is 1:1:m; ​​the ratio of the channel width-to-length ratios of the fourth MOS tube and the sixth MOS tube is 1:m; and the ratio of the channel width-to-length ratios of the fifth MOS tube and the seventh MOS tube is 1:m; wherein m satisfies the following formula relationship:

[0014]

[0015] Among them, R01 is the resistance value of the first reference resistance unit, Rx pre VTH is the minimum resistance value of the resistance value variation range of the resistance unit to be tested. MP2 is the effective threshold voltage of the second MOS tube, VTH MP3 is the effective threshold voltage of the third MOS tube, Iref is the current value of the reference current source, and m is greater than 1.

[0016] In an embodiment of the present application, when the difference in resistance between the resistor to be measured and the first reference resistor is small and it is difficult to compare the current sizes, the current size comparison can be performed by changing the channel width-to-length ratio of the corresponding MOS tube in the circuit to relatively enlarge the current difference. There is no need to deploy additional components such as amplifiers, which relatively reduces the chip area occupied by the detection circuit and reduces chip power consumption.

[0017] In a possible implementation of the first aspect, the first MOS transistor, the second MOS transistor and the third MOS transistor are PMOS transistors, and the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are NMOS transistors.

[0018] In a second aspect, a chip is provided, in which a circuit as described in any one of the first aspects is formed.

[0019] According to a third aspect, an electronic device is provided. The electronic device includes a chip, in which a circuit as described in any one of the first aspects is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 According to some embodiments of the present application, a module diagram of a detection circuit 20 is shown;

[0021] Figure 2 According to some embodiments of the present application, a circuit diagram of a detection circuit 20 is shown;

[0022] Figure 3 According to some embodiments of the present application, an example schematic diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0023] The illustrative embodiments of the present application include, but are not limited to, a detection circuit, a chip, and a device.

[0024] The following is combined with Figures 1 to 3 The technical solution of this application is introduced.

[0025] As mentioned above, determining the resistance of a variable resistor by means of voltage drop usually requires the deployment of an additional voltage comparison circuit. In particular, when the resistance difference between the variable resistor and the fixed resistor is small, it may be necessary to deploy amplifiers and other components in the voltage comparison circuit to amplify the voltage for comparison, which occupies a large chip area and is not conducive to chip design.

[0026] For example, the resistance of a fixed resistor is 100 ohms, and the resistance range of a variable resistor when the user does not touch the screen of an electronic device is 1 to 10 ohms; that is, when the user does not touch the screen, the resistance of the variable resistor is much smaller than the fixed resistor, and at this time the circuit outputs a high-level control signal to put the screen of the electronic device in a dormant state. When the user touches the screen of the electronic device and the resistance of the variable resistor increases to 101 ohms, the difference between the resistance of the variable resistor and the resistance of the fixed resistor is small, and in the case where the voltage comparison circuit itself may still have an offset voltage, it is difficult to determine the voltage drop relationship between the fixed resistor and the variable resistor. In this way, it is necessary to amplify the voltage input to the voltage comparison circuit by deploying components such as amplifiers to increase the difference between the two. However, the aforementioned deployment of an additional voltage comparison circuit itself has increased the chip footprint, and the deployment of components such as amplifiers further increases the chip footprint, which is not conducive to chip design.

[0027] To this end, the present application proposes a detection circuit, such as Figure 1 As shown, the detection circuit 20 includes a bias module 21, a reference module 22 and a comparison module 23. The bias module 21 is used to provide a first mirror current and a second mirror current to the reference module 22 and the comparison module 23 respectively; the reference module 22 includes a first reference resistor unit, and the reference module 22 is used to provide a pull-down current to a target node in the comparison module 23 based on the first mirror current and the first reference resistor unit; the comparison module 23 includes a resistance unit to be measured, and the comparison module 23 is used to provide a pull-up current to a target node in the comparison module 23 based on the second mirror current and the resistance unit to be measured, wherein the pull-up current and the pull-down current of the target node are used to determine the output result of the detection circuit.

[0028] In some embodiments, the bias module 21 includes a first mirror unit, the reference module 22 includes a second mirror unit connected to the first reference resistor unit, and the comparison module 23 includes a third mirror unit connected to the resistance unit to be measured, wherein the first mirror unit and the second mirror unit form a first current mirror branch, and the first mirror unit and the third mirror unit form a second current mirror branch. The bias module 21 is used to provide a first mirror current to the reference module 22 based on the first current mirror branch, the first mirror current flows through the first reference resistor unit to generate a first voltage drop so that the current flowing through the second mirror unit is the first current, and the first current is used as a pull-down current of the target node in the comparison module 23; the bias module 21 is used to provide a second mirror current to the comparison module 23 based on the second current mirror branch, the second mirror current flows through the resistance unit to be measured to generate a second voltage drop so that the current flowing through the third mirror unit is the second current, and the second current is used as a pull-up current of the target node.

[0029] It can be understood that the present application can determine the potential state of the target node when the resistance to be measured (an instance of the resistance unit to be measured) changes through the magnitude relationship between the pull-up current and the pull-down current of the target node. For example, when the resistance to be measured changes so that the resistance value of the resistance to be measured is less than the resistance value of the first reference resistor (an instance of the first reference resistor unit), the current value of the pull-up current is greater than the current value of the pull-down current, the potential of the target node is a high potential, and the output result of the detection circuit is a high-level signal; corresponding to the screen sleep and wake-up scenarios of the above-mentioned electronic device, the high-level signal corresponds to the resistance value of the resistance to be measured being less than the resistance value of the first reference resistor, that is, the user has not touched the screen at this time, and the screen of the electronic device is in a sleep state; or for example, when the resistance to be measured changes so that the resistance value of the resistance to be measured is greater than the resistance value of the first reference resistor, the current value of the pull-up current is less than the current value of the pull-down current, and the potential of the target node is a low potential, then the output result of the detection circuit is a low-level signal; corresponding to the screen sleep and wake-up scenarios of the above-mentioned electronic device, the low-level signal corresponds to the resistance value of the resistance to be measured being greater than the resistance value of the first reference resistor, that is, the user has touched the screen at this time, and the screen of the electronic device is in an awake state.

[0030] It can be seen that the present application can determine the resistance relationship between the resistor to be measured and the first reference resistor based on current comparison, without the need to deploy an additional voltage comparison circuit, and adopts a simple circuit structure to realize the resistance comparison function, and the structure is simple and easy to implement. In addition, when the difference in resistance between the resistor to be measured and the first reference resistor is small and it is difficult to compare the current, the current size can be compared by changing the channel width-to-length ratio of the corresponding MOS tube in the circuit to relatively enlarge the current difference, that is, by appropriately adjusting the circuit parameters, the comparison errors caused by the current mirror mismatch and the incomplete blowing of the electric fuse can be offset, so that the output comparison result is more accurate, and there is no need to deploy additional components such as amplifiers, which relatively reduces the chip area occupied by the detection circuit and reduces the chip power consumption.

[0031] In some embodiments, the resistor to be measured includes any variable resistor such as a thermistor, a photoresistor, a varistor, an electric fuse, etc.

[0032] In some embodiments, Figure 2 FIG. 2 shows a circuit structure diagram of a detection circuit 20. Figure 2 As shown, the circuit detection circuit 20 includes a bias module 21, a reference module 22 and a comparison module 23; and each module is connected to the same power supply voltage VDD and the same ground terminal AGND.

[0033] In some embodiments, the bias module 21 includes a reference resistor R02 (an example of a second reference resistor unit), a PMOS tube MP1 (an example of a first MOS tube), and a reference current source Iref. One end of the reference resistor R02 is connected to the output end of the power supply voltage VDD, the other end of the reference resistor R02 is connected to the source of the PMOS tube MP1, the drain of the PMOS tube MP1 is connected to one end of the reference current source Iref, the other end of the reference current source Iref is connected to the input end of the ground terminal AGND, and the source of the PMOS tube MP1 is short-circuited with the gate of the PMOS tube MP1. It can be understood that the PMOS tube MP1 serves as the first mirror unit in the bias module 21.

[0034] In some embodiments, the reference module 22 includes a reference resistor R01 (an example of a first reference resistor unit), a PMOS transistor MP2 (an example of a second MOS transistor), an NMOS transistor MN4 (an example of a fourth MOS transistor), and an NMOS transistor MN5 (an example of a fifth MOS transistor). One end of the reference resistor R01 is connected to the output end of the power supply voltage VDD, the other end of the reference resistor R01 is connected to the source of the PMOS transistor MP2, the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN4, the source of the NMOS transistor MN4 is connected to the drain of the NMOS transistor MN5, the source of the NMOS transistor MN5 is connected to the input end of the ground terminal AGND, and the drain of the NMOS transistor MN4 is short-circuited with the gate of the NMOS transistor MN5. It can be understood that the MOS transistor MP2 serves as the second mirror unit in the reference module 22.

[0035] In some embodiments, the comparison module 23 includes a resistor to be measured Rx (an example of a resistor unit to be measured), a PMOS tube MP3 (an example of a third MOS tube), an NMOS tube MN6 (an example of a sixth MOS tube), an NMOS tube MN7 (an example of a seventh MOS tube), and a comparator buffer. Among them, one end of the resistor to be measured Rx is connected to the output end of the power supply voltage VDD, the other end of the resistor to be measured Rx is connected to the source of the PMOS tube MP3, the drain of the PMOS tube MP3 is connected to the drain of the NMOS tube MN6, the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN7, the source of the NMOS tube MN7 is connected to the input end of the ground terminal AGND, and the drain of the PMOS tube MP3 is connected to the input end of the comparator buffer, and the output end of the comparator buffer is used to output the control signal OUT. It can be understood that the PMOS tube MP3 serves as the third mirror unit in the comparison module 23.

[0036] In some embodiments, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, and the sources of the PMOS tubes MP1 and MP2 are connected to the output end of the power supply voltage VDD through corresponding resistors, that is, the PMOS tubes MP1 and MP2 form a current mirror structure, and a first current mirror branch is formed between the PMOS tubes MP1 and MP2. The bias module can copy the current of the reference current source Iref to the reference module through the first current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the PMOS tubes MP1 and MP2. Similarly, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP3, and the sources of the PMOS tubes MP1 and MP3 are connected to the output end of the power supply voltage VDD through corresponding resistors, that is, the PMOS tubes MP1 and MP3 form a current mirror structure, and a second current mirror branch is formed between the PMOS tubes MP1 and MP3. The bias module can copy the current of the reference current source Iref to the comparison module through the second current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the PMOS tubes MP1 and MP3.

[0037] In some embodiments, since the drain of NMOS tube MN4 is short-circuited with the gate of NMOS tube MN5, and the gate of NMOS tube MN5 is connected to the gate of NMOS tube MN7, the sources of NMOS tubes MN5 and MN7 are both connected to the ground terminal, that is, the drain potential of NMOS tubes MN5 and MN7 is the same, and the gate drive voltage of NMOS tubes MN5 and MN7 is the drain voltage of NMOS tube MN4. Further, since the drain potential of NMOS tubes MN5 and MN7 is the same, and the gate of NMOS tube MN4 is connected to the gate of NMOS tube MN6, that is, the drain potential of NMOS tubes MN4 and MN6 is the same, and the gate voltage of NMOS tubes MN4 and MN6 is Vbn. It can be seen that NMOS tubes MN5 and MN7 form a cascode power mirror, and NMOS tubes MN5 and MN7 form a cascode power mirror.

[0038] It can be understood that, since the third current mirror branch is formed between the NMOS tubes MN4 and MN5 and the NMOS tubes MN6 and MN7, that is, the NMOS tube MN4 can copy the current flowing through the NMOS tube MN4 to the NMOS tube MN6 through the third current mirror branch, and the NMOS tube MN5 can copy the current flowing through the NMOS tube MN7 to the NMOS tube MN6 through the third current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the NMOS tubes MN4 and MN6 and the NMOS tubes MN5 and MN7. In addition, since the NMOS tubes MN4 and MN5 are connected in series with the PMOS tube MP2, that is, the currents of the NMOS tubes MN4 and MN5 are the same as those of the PMOS tube MP2, that is, the currents copied by the NMOS tubes MN4 and MN5 to the corresponding NMOS tubes MN6 and MN7 are equivalent to the current flowing through the PMOS tube MP2 being copied by the PMOS tube MP2 to the MOS tubes MN6 and MN7.

[0039] In some embodiments, Figure 2 The pull-up current at point c (an instance of the target node) is the current flowing through the PMOS tube MP3 (an instance of the second current), and the pull-down current at point c is the current flowing through the NMOS tube MN6. Since the current flowing through the NMOS tube MN6 is a copied current from the PMOS tube MP2, the pull-down current at point c is the current flowing through the PMOS tube MP2 (an instance of the first current).

[0040] In some embodiments, the channel width-to-length ratio of the PMOS tubes MP1, MP2 and MP3 is 1:1:m; ​​the channel width-to-length ratio of the NMOS tubes MN4 and MN6 is 1:m; the channel width-to-length ratio of the NMOS tubes MN5 and MN7 is 1:m.

[0041] In some embodiments, when m is 1, the ratio of the channel width-to-length ratios of the PMOS tube MP1, the PMOS tube MP2, and the PMOS tube MP3 is 1:1:1; the ratio of the channel width-to-length ratios of the NMOS tube MN4 and the NMOS tube MN6 is 1:1; the ratio of the channel width-to-length ratios of the NMOS tube MN5 and the NMOS tube MN7 is 1:1; that is, the current ratio of the bias module 21, the reference module 22, and the comparison module 23 is 1:1:1. The magnitude relationship between the reference resistor R01 and the resistor to be measured Rx can be determined based on the current flowing through the PMOS tube MP3 and the current flowing through the PMOS tube MP2.

[0042] For example, when the resistance of the resistor to be measured Rx is greater than the resistance of the reference resistor R01, the voltage at point a (the source end of the PMOS tube MP2) is VDD-Iref*R01 (the value of Iref*R01 is an example of the first voltage drop), and the voltage at point b (the source end of the PMOS tube MP3) is VDD-1*Iref*Rx (the value of 1*Iref*Rx is an example of the second voltage drop), that is, the voltage at point b is less than the voltage at point a. Since the gate voltages of the PMOS tubes MP2 and MP3 are the same, the effective threshold voltages of the PMOS tubes MP2 and MP3 are the same. Thus, according to the MOS tube saturation region current formula (1):

[0043] I M =1 / 2*μ n* C ox *(W / L)*(Vgs-Vth) 2 (1)

[0044] In formula (1), I M is the current flowing through the corresponding MOS tube, μ n is the surface mobility of the corresponding MOS tube, Cox is the gate oxide capacitance per unit area of ​​the corresponding MOS tube, W is the width of the channel of the corresponding MOS tube, L is the length of the channel of the corresponding MOS tube, Vgs is the gate-source voltage of the corresponding MOS tube, and Vth is the effective threshold voltage of the corresponding MOS tube.

[0045] It can be seen that, when the source terminal voltage of the PMOS tube MP3 is less than the source terminal voltage of the PMOS tube MP2, the current (IMp3) flowing through the PMOS tube MP3 is less than the current (IMp2) flowing through the PMOS tube MP2, that is, the current value of the pull-up current at point c is less than the current value of the pull-down current, and the potential at point c is a low potential, then the output result of the detection circuit is a low-level signal, and according to the low-level signal, it can be determined that the resistance value of the resistor to be measured Rx is greater than the resistance value of the reference resistor R01.

[0046] In other embodiments, when the resistance of the resistor to be measured Rx is greater than the resistance of the reference resistor R01, but the difference between the resistance of the resistor to be measured Rx and the resistance of the reference resistor R01 is small, the error in the effective threshold voltage caused by the manufacturing process of the PMOS tubes MP2 and MP3 may cause errors in the currents flowing through the PMOS tubes MP2 and MP3, making it difficult to accurately determine the potential at point c based on the currents flowing through the PMOS tubes MP2 and MP3.

[0047] For example, when the resistance value of the resistor to be measured Rx is 101 ohms and the resistance value of the reference resistor R01 is 100 ohms, the gate voltages of the PMOS tubes MP2 and MP3 are the same, that is, the effective threshold voltages of the PMOS tubes MP2 and MP3 should be the same, and the current flowing through the PMOS tube MP3 should be less than the current flowing through the PMOS tube MP2. However, due to the error in the effective threshold voltage caused by the manufacturing process of the PMOS tubes MP2 and MP3, the effective threshold voltage of the PMOS tube MP3 may be less than the effective threshold voltage of the PMOS tube MP2, that is, when the source voltage of the PMOS tube MP3 is less than the source voltage of the PMOS tube MP2, the current flowing through the PMOS tube MP3 may be equal to or greater than the current flowing through the PMOS tube MP2, resulting in a current comparison error. In this way, m can be set to satisfy the following formula (2):

[0048]

[0049] In formula (2), R01 is the resistance of the reference resistor R01, Rx pre VTH is the minimum resistance value of the resistance variation range of the resistor to be measured Rx. MP2 VTH is the effective threshold voltage of PMOS tube MP2. MP3 is the effective threshold voltage of the PMOS tube MP3, Iref is the current value of the reference current source, and m is greater than 1.

[0050] It can be understood that the current flowing through the comparison module is enlarged based on the current copy ratio m. According to the modified formula U=IR of Ohm's law, it can be known that enlarging the current I based on the current copy ratio m can be equivalent to enlarging the resistance R based on the current copy ratio m. For example, when the resistance value of the resistor to be measured Rx is 101 ohms, the resistance value of the reference resistor R01 is 100 ohms, and m is equal to 2, enlarging the current flowing through the resistor to be measured Rx by 2 times is equivalent to enlarging the resistance value of the resistor to be measured Rx by 2 times to 202 ohms. 202 ohms is significantly different from 100 ohms, which improves the accuracy of subsequent current comparison results.

[0051] At the same time, through VTH MP2 -VTH MP3 Determine the voltage error of the effective threshold voltage caused by the manufacturing process of PMOS tubes MP2 and MP3, and determine the error resistance generated by the voltage error The resistance value of the reference resistor R01 is set to be greater than the sum of the minimum resistance value of the resistance variation range of the resistor to be measured Rx m times and the error resistance, that is, the value of the error resistance is reduced compared to the reference resistor R01, so that the resistance value of the reference resistor R01 becomes smaller but not less than the minimum resistance value of the resistance variation range of the resistor to be measured Rx m times, ensuring that a correct comparison result can be output when the resistance value of the resistor to be measured Rx is smaller than the resistance value of the reference resistor R01, avoiding an erroneous comparison result while equivalently enlarging the resistance value of the resistor to be measured Rx through the current copy ratio m.

[0052] It can be seen that the present application can determine the resistance relationship between the resistor to be measured Rx and the reference resistor R01 based on current comparison, without the need to deploy an additional voltage comparison circuit, and adopts a simple circuit structure to realize the resistance comparison function, and the structure is simple and easy to implement. In addition, when the resistance difference between the resistor to be measured Rx and the reference resistor R01 is small and it is difficult to compare the current size, the current size comparison can be performed by changing the channel width-to-length ratio of the corresponding MOS tube in the circuit to relatively enlarge the current difference, that is, by appropriately adjusting the circuit parameters, the comparison errors caused by the current mirror mismatch and the incomplete blowing of the electric fuse can be offset, so that the output comparison result is more accurate, and there is no need to deploy additional components such as amplifiers, which relatively reduces the chip area occupied by the detection circuit and reduces the chip power consumption.

[0053] Figure 3 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Figure 3 As shown, the electronic device 100 includes: a processor 101, a communication interface 103 and a memory 102. Among them, the processor 101, the communication interface 103 and the memory 102 can be connected to each other through an internal bus 104, and can also communicate through other means such as wireless transmission. In the embodiment of the present application, the connection through the bus 104 is taken as an example. The bus 104 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 104 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 104 can also include a power bus, a control bus, and a status signal bus. For the sake of clarity, various buses are marked as bus 104 in the figure.

[0054] The processor 101 may be composed of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 101 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 102, which enables the electronic device 100 to provide a variety of services.

[0055] It should be noted that this embodiment can be implemented by a general physical server, for example, an ARM server or an X86 server, or it can be implemented by a virtual machine based on a general physical server combined with NFV technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment. This application does not make any specific limitations.

[0056] The memory 102 may include a volatile memory, such as a random access memory (RAM); the memory 102 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 102 may also include a combination of the above types.

[0057] The communication interface 103 can be a wired interface (such as an Ethernet interface), an internal interface (such as a PCIe bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless LAN interface) for communicating with other devices or modules.

[0058] Need to explain, Figure 3This is only one possible implementation of the embodiment of the present application. In actual applications, the electronic device 100 may also include more or fewer components, which will not be elaborated here.

[0059] The present application also provides a chip, which can be deployed in the electronic device 100, and the chip forms a circuit as described in any of the above embodiments. The chip can be an analog-to-digital conversion chip, an interface chip, or a power management chip.

[0060] In the accompanying drawings, some structures or features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structure or feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0061] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0062] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of further restrictions, the elements defined by the statement "including one" do not exclude the existence of other identical elements in the process, article or device including the elements.

[0063] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. A detection circuit, characterized in that: It includes a bias module, a reference module and a comparison module, among which, The bias module is used to provide a first mirror current and a second mirror current to the reference module and the comparison module respectively; The reference module includes a first reference resistance unit, and the reference module is used to provide a pull-down current to a target node in the comparison module based on the first mirror current and the first reference resistance unit; The comparison module includes a resistance unit to be measured, and the comparison module is used to provide a pull-up current to a target node in the comparison module based on the second mirror current and the resistance unit to be measured, wherein the pull-up current and the pull-down current of the target node are used to determine an output result of the detection circuit.

2. The circuit according to claim 1, characterized in that The detection circuit determines the output result based on the following method: When the resistance value of the resistance unit to be measured is greater than the resistance value of the first reference resistance unit, the current value of the pull-up current is less than the current value of the pull-down current, and the output result of the detection circuit is a low level signal; When the resistance of the resistance unit to be measured is smaller than the resistance of the first reference resistance unit, the current value of the pull-up current is larger than the current value of the pull-down current, and the output result of the detection circuit is a high level signal.

3. The circuit according to claim 1, characterized in that The resistance unit to be measured includes at least any one of the following resistors: a thermistor, a photoresistor, a varistor, and an electric fuse.

4. The circuit according to any one of claims 1 to 3, characterized in that: The bias module includes a first mirror unit, the reference module includes a second mirror unit, and the comparison module includes a third mirror unit, wherein the first mirror unit and the second mirror unit form a first current mirror branch, and the first mirror unit and the third mirror unit form a second current mirror branch; The bias module is used to provide a first mirror current to the reference module based on the first current mirror branch, the first mirror current flows through the first reference resistor unit to generate a first voltage drop so that the current flowing through the second mirror unit is a first current, and the first current is used as a pull-down current of the target node in the comparison module; The bias module is used to provide a second mirror current to the comparison module based on the second current mirror branch, and the second mirror current flows through the resistance unit to be measured to generate a second voltage drop so that the current flowing through the third mirror unit is a second current, and the second current is used as a pull-up current of the target node.

5. The circuit according to claim 4, characterized in that The first mirror unit includes a first MOS transistor, the second mirror unit includes a second MOS transistor, the third mirror unit includes a third MOS transistor, the bias module includes a second reference resistance unit and a reference current source, and the second reference resistance unit has the same resistance as the first reference resistance unit; One end of the second reference resistance unit is connected to the output end of the power supply voltage, the other end of the second reference resistance unit is connected to the source of the first MOS tube, one end of the first reference resistance unit is connected to the output end of the power supply voltage, the other end of the first reference resistance unit is connected to the source of the second MOS tube, one end of the resistance unit to be measured is connected to the output end of the power supply voltage, the other end of the resistance unit to be measured is connected to the source of the third MOS tube, and The source of the first MOS tube is terminated with the gate of the first MOS tube, and the gate of the first MOS tube is respectively connected with the gate of the second MOS tube and the gate of the third MOS tube, so that the first MOS tube and the second MOS tube form a first current mirror branch and provide a first mirror current to the bias module through the first current mirror branch, and the first MOS tube and the third MOS tube form a second current mirror branch and provide a second mirror current to the comparison module through the second current mirror branch.

6. The circuit according to claim 5, characterized in that The reference module includes a fourth MOS tube and a fifth MOS tube, and the comparison module includes a sixth MOS tube and a seventh MOS tube; The drain of the fourth MOS tube is connected to the drain of the second MOS tube, the source of the fourth MOS tube is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the ground terminal, the drain of the sixth MOS tube is connected to the drain of the third MOS tube, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, and the source of the seventh MOS tube is connected to the ground terminal, and The gate of the fourth MOS tube is connected to the gate of the sixth MOS tube, and the gate of the fourth MOS tube and the gate of the sixth MOS tube are provided with a second driving voltage, the gate of the fifth MOS tube is connected to the gate of the seventh MOS tube, and the gate of the fifth MOS tube and the gate of the seventh MOS tube are both connected to the drain of the fourth MOS tube, so that the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube form a third current mirror branch, and the reference module provides the first current to the comparison module through the third current mirror branch, so that the first current is used as a pull-down current of the target node.

7. The circuit according to claim 6, characterized in that The ratio of the channel width to length ratio of the first MOS tube, the second MOS tube and the third MOS tube is 1:1:1; The ratio of the channel width to length ratio of the fourth MOS tube to the sixth MOS tube is 1:1; The ratio of the channel width to length ratio of the fifth MOS tube to that of the seventh MOS tube is 1:

1.

8. The circuit according to claim 6, characterized in that The ratio of the channel width to length ratio of the first MOS tube, the second MOS tube and the third MOS tube is 1:1:m; The ratio of the channel width to length ratio of the fourth MOS tube to the sixth MOS tube is 1:m; The ratio of the channel width to length ratio of the fifth MOS tube to the seventh MOS tube is 1:m; Among them, m satisfies the following formula relationship: Wherein, R01 is the resistance value of the first reference resistance unit, Rx pre is the minimum resistance value of the resistance value variation range of the resistance unit to be tested, VTH MP2 is the effective threshold voltage of the second MOS tube, VTH MP3 is the effective threshold voltage of the third MOS tube, Iref is the current value of the reference current source, and m is greater than 1.

9. The circuit according to claim 6, characterized in that The first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes, and the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are NMOS tubes.

10. A chip, characterized in that: The chip has the circuit according to any one of claims 1 to 9 formed therein.

11. An electronic device, characterized in that: The electronic device comprises a chip, in which the circuit according to any one of claims 1 to 9 is formed.

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