Logic BIST circuit and semiconductor device including the same

Abstract

A logical built-in self-test (BIST) circuit that performs a scan test that improves test coverage for each clock domain, and a semiconductor device including the logical BIST circuit are provided. The logic BIST circuit includes: an OR gate configured to: receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to: output an enable clock independently of the function enable signal when the register setting signal has a first logic value; and a scan chain configured to capture an output of the first logic circuit connected with the flip-flop according to the enable clock.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0080679 filed on June 22, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0121271 filed on September 12, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a logic built-in self-test (BIST) circuit including a clock gating circuit and a semiconductor device including the logic BIST circuit, and more particularly, to a logic BIST circuit that performs a scan test capable of improving test coverage for each clock domain. Background Art

[0004] Design for testability (hereinafter referred to as DFT) technology has been widely used to test semiconductor devices. Using DFT technology, defects in logic circuits and defects that affect operating speed can be detected. For example, a scan test in which a scan trigger connected in the form of a scan chain is added to the logic circuit to be tested can be used. Scan testing can be performed in the following manner: the best mode for testing the circuit in the semiconductor device is prepared in advance, and the expected data for comparing the mode and the test output is stored in a large memory of the automatic test equipment (ATE). However, when a test is required during the operation of a system equipped with a semiconductor device, an external storage device and ATE may not be available for storing a large amount of data. Therefore, logic built-in self-test (hereinafter referred to as LBIST) technology has been used for self-testing logic circuits in semiconductor devices.

[0005] However, the signals used in LBIST may be randomly generated, which may negatively affect the reliability and accuracy of the tests performed.Therefore, there is a need for improved LBIST techniques and devices. Summary of the invention

[0006] One or more example embodiments provide a logic built-in self-test (BIST) circuit with improved scan test coverage.

[0007] The inventive concept also provides a logic BIST circuit having improved test coverage and performing low-power testing on a semiconductor device mounted on a system.

[0008] According to one aspect of an example embodiment, a logic BIST circuit includes: a first OR gate configured to receive a scan enable signal and a first register setting signal, and generate a first modified scan enable signal; a first clock gating circuit configured to receive a first clock according to the first modified scan enable signal and a first function enable signal, and output the first enable clock; a first scan chain configured to load first scan data into a first flip-flop according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flop, and output the captured data; a second OR gate configured to receive a scan enable signal and a second register setting signal, and generate a second modified scan enable signal; a second clock gating circuit configured to receive a second clock according to the second modified scan enable signal and the second function enable signal, and output the second enable clock; and a second scan chain configured to load second scan data into a second flip-flop according to the second enable clock, capture an output of a second logic circuit connected to the second flip-flop, and output the captured data. At least one of the first clock gating circuit and the second clock gating circuit is configured to output a corresponding enable clock when the corresponding register setting signal has a first logic value regardless of the corresponding function enable signal.

[0009] According to another aspect of an example embodiment, a logic BIST circuit includes: a decompressor configured to sequentially generate a plurality of test patterns; a pattern counter configured to count the number of the plurality of test patterns and generate a count signal; a first OR gate configured to receive a first count signal among a scan enable signal and a count signal and generate a first modified scan enable signal; a first clock gating circuit configured to receive a first clock according to the first modified scan enable signal and a first function enable signal and output a first enable clock; and a first scan chain configured to load first scan data into a first flip-flop according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flop, and output the captured data. The first clock gating circuit is further configured to output a first enable clock when the first count signal has a first logic value, regardless of a state of the first function enable signal.

[0010] According to another aspect of the example embodiment, a logic BIST circuit includes: a decompressor configured to sequentially generate multiple test patterns; a pattern counter configured to count the number of multiple test patterns generated by the decompressor and generate a count signal; a pulse generator configured to receive at least some of the count signals and generate a pulse signal; a first OR gate configured to receive a first pulse signal among a scan enable signal and a pulse signal and generate a first modified scan enable signal; a first clock gating circuit configured to receive a first clock according to the first modified scan enable signal and a first functional enable signal and output a first enable clock; and a first scan chain configured to load first scan data into a first flip-flop according to the first enable clock and capture and output an output of a first logic circuit connected to the first flip-flop.

[0011] According to another aspect of an example embodiment, a semiconductor device includes: a first core including a first logic circuit and a first logic BIST circuit, the first logic BIST circuit being configured to perform a first scan test on the first logic circuit; and a second core including a second logic circuit and a second logic BIST circuit, the second logic BIST circuit being configured to perform a second scan test on the second logic circuit. Each of the first logic BIST circuit and the second logic BIST circuit includes: a decompressor configured to sequentially generate a plurality of test patterns; a pattern counter configured to count the number of the generated plurality of test patterns and generate a count signal; a pulse generator configured to receive at least some of the count signals and generate a pulse signal; a first OR gate configured to receive a first pulse signal from among a scan enable signal and a pulse signal and generate a first modified scan enable signal; a first clock gating circuit configured to receive a first clock and output a first enable clock according to the first modified scan enable signal and a first functional enable signal; and a first scan chain configured to load the first scan data into a first flip-flop according to the first enable clock and capture and output an output of a first logic circuit connected to the first flip-flop.

[0012] According to another aspect of the example embodiment, a pulse generating circuit includes: a first AND gate configured to receive a first signal having a first period and a second signal having a second period, and output a first pulse signal, the second period being twice as long as the first period; a first XOR gate configured to receive the second signal and the first signal, and output a first internal signal; a first NAND gate configured to receive the first pulse signal and the first internal signal, and output a second pulse signal; a second XOR gate configured to receive the first signal and a third signal having a third period, and output a second internal signal, the third period being twice as long as the second period; a second AND gate configured to receive the first internal signal and the second internal signal, and output a third pulse signal; a third XOR gate configured to receive the second signal and the third signal, and output a third internal signal; and a third AND gate configured to receive the second internal signal and the third internal signal, and output a fourth pulse signal. Each of the first to fourth pulse signals maintains a first logic value during a half period of the first signal in a different portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects will become more apparent from the following description of example embodiments taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A block diagram of a logic built-in self-test (LBIST) including multiple scan chains is shown;

[0015] Figure 2 Shows Figure 1 The connection between the scan chain and the clock gating circuit;

[0016] Figure 3 is a timing diagram of scan test operation;

[0017] Figure 4 shows the connection between the test clock gating circuit and the scan chain according to an example embodiment;

[0018] Figure 5 shows a portion of a LBIST including a plurality of scan chains according to an example embodiment;

[0019] Figure 6 According to an example embodiment Figure 5 A detailed diagram of multiple scan chains and test clock gating circuits;

[0020] Figure 7 is a timing diagram of a scan test operation according to an example embodiment;

[0021] Figure 8 Shown are connections between a pattern counter, a test clock gating circuit, and a scan chain in a LBIST according to an example embodiment;

[0022] Fig. 9 According to an example embodiment Figure 8 A timing diagram of a count signal of a mode counter and a modified scan enable signal;

[0023] Fig.10 According to an example embodiment, Figure 8 Example of modification of the OR gate of the test clock gating circuit;

[0024] Fig.11 Shown are connections between a pattern counter, a pulse generator, a test clock gating circuit, and a scan chain in a LBIST according to an example embodiment;

[0025] Fig. 12A According to an example embodiment Fig.11 Detailed circuit diagram of the pulse generator;

[0026] Fig. 12B According to an example embodiment Fig.11 and Fig. 12A A timing diagram of a pulse signal and a modified scan enable signal;

[0027] Fig. 12C According to an example embodiment Fig. 12A The truth table of the pulse generator;

[0028] Fig.13 According to an example embodiment, Fig.11 Example of modification of the OR gate of the test clock gating circuit;

[0029] Fig.14 is a graph showing test coverage of a LBIST according to an example embodiment and test coverage of a LBIST according to a comparative example; and

[0030] Fig.15 is a block diagram illustrating a semiconductor device including a plurality of intellectual property (IP) cores according to example embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. Each example embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment that is also provided herein or is not provided herein but consistent with the present disclosure. Statements such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0032] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the example embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element, or there can be intervening elements between them. On the other hand, it should be understood that when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Other expressions describing the relationship between elements (e.g., "between" and "directly between" or "adjacent to" and "directly adjacent to") can also be interpreted in the same manner as described above.

[0034] The terms herein are used to explain the exemplary embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form also includes the plural form. In this specification, it should be understood that the term "include" or "comprise" when used in this article indicates the presence of the described features, wholes, steps, operations, elements, components or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components or combinations thereof.

[0035] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same symbols or reference numerals may be used to describe the same components if possible.

[0036] Figure 1An LBIST block including multiple scan chains is shown. The LBIST structure 10 may include a controller 12, a clock generator 14, a decompressor 16, a scan chain 18, and a compressor 19. The controller 12 includes: a finite state machine (FSM) 12_1 for controlling the overall operating state of the LBIST structure 10 and generating a scan enable signal SE for each test mode; a shift counter 12_2 for counting the shift operation of the flip-flop of each scan chain 18; and a pattern counter 12_3 for counting the number of test modes. The clock generator 14 may receive a shift clock CLKs, receive an operation clock CLKf from a phase-locked loop (PLL), and generate a clock for a test operation under the control of the controller 12. The decompressor 16 may include a pseudo-random pattern generator (PRPG) and an exclusive OR (XOR) phase shifter, the pseudo-random pattern generator (PRPG) including a linear feedback shift register (LFSR), and the exclusive OR (XOR) phase shifter is used to add more randomness to the data generated by the PRPG. Each of the plurality of scan chains 18 includes a flip-flop connected in a chain and a logic circuit connected to the flip-flop. Each scan chain 18 latches the scan data sent from the decompressor 16 to the flip-flop in response to the scan enable signal SE generated by the controller 12, and captures the resulting data through the logic circuit connected to the scan chain, and then outputs the captured data to the compressor 19. The above operation is repeated for each test mode. The compressor 19 includes an exclusive OR compressor for compressing the data output from the plurality of scan chains 18, a multi-input signature register (MISR), and a comparator for generating a test result.

[0037] Figure 2 Shows Figure 1 A connection between one of the scan chains of the LBIST structure 10 and the clock gating circuit. Figure 3 A timing diagram illustrating a portion of a scan test operation in LBIST is shown.

[0038] refer to Figure 2 For low power functional mode and low power test operation, the clock gating circuit 20 can send the gated enable clock ECLK to the flip-flops FF1, FF2, FF3, ... of the scan chain 18-1, or block the gated enable clock ECLK. Figure 1 The controller 12 receives the scan enable signal SE, receives the clock CLK from the clock generator 14 , and receives the function enable signal FEN from the function enable logic 23 and the flip-flop 21 connected to the function enable logic 23 .

[0039] refer to Figure 3The scan test operation sequentially includes a shift-in portion where the scan enable signal SE is at logic "1", a capture portion where the scan enable signal SE is at logic "0", and a shift-out portion where the scan enable signal SE is at logic "1".

[0040] Reference together Figure 2 and Figure 3 In the shift-in and shift-out parts where the scan enable signal SE is at logic "1", the clock gating circuit 20 sends the gated enable clock ECLK to all flip-flops in the scan chain 18-1. In the capture part where the scan enable signal SE is at logic "0", the clock gating circuit 20 sends the gated enable clock ECLK to the flip-flops of the scan chain 18-1 only when the function enable signal FEN is at logic "1". However, in the capture part, the output logic values ​​of the flip-flops 21 and the function enable logic 23 that determine the function enable signal FEN are determined by Figure 1 The random scan data generated by the PRPG of the scan test is randomly determined. Therefore, it is not easy to specify the logic value of the function enable signal FEN as "1" in the capture part. Therefore, there may be limitations in capturing the output value of the logic circuit of the scan chain 18-1 for the flip-flops (FF1, FF2, FF3, ...) in the desired capture part. This makes it difficult to detect defects defined in the scan test and increase test coverage.

[0041] Figure 4 A connection relationship between the test clock gating circuit 300 and the scan chain 18 - 2 according to an example embodiment is shown.

[0042] refer to Figure 4 The test clock gating circuit 300 may include a first OR gate 311 and a clock gating circuit 20-1. The test clock gating circuit 300 may also include a trigger 21-1 and a function enable logic 23-1. The trigger 21-1 and the function enable logic 23-1 may be the same as those described above. Figure 2 The trigger and function enable logic described are the same. The first OR gate 311 can receive the scan enable signal SE and the register setting signal RS and generate a modified scan enable signal MSE. Figure 3 As shown, the scan enable signal SE is Figure 1 The register setting signal RS may be sent to the controller 12 of the scan test operation, and may maintain a logic "1" in both the shift-in portion and the shift-out portion of the scan test operation, and may maintain a logic "0" in the capture portion of the scan test operation. The register setting signal RS may be set by an external device or a user for the scan test operation, and may be set to a logic "1" or "0" during the scan test. For example, when the register setting signal RS is set to a logic "1", the first OR gate 311 may generate a modified scan enable signal MSE, and maintain the modified scan enable signal MSE at a logic "1", regardless of the scan enable signal SE.

[0043] The clock gating circuit 20-1 receives the modified scan enable signal MSE via the test enable terminal TE, and receives the function enable signal FEN from the function enable logic 23-1 via the function enable terminal EN. In response to these signals (e.g., the modified scan enable signal MSE and the function enable signal FEN), the clock gating circuit 20-1 may use the gated enable clock ECLK to send the clock CLK received via the clock terminal CLK to the flip-flop of the scan chain 18-2, or may not use the gated enable clock ECLK to send the clock CLK received via the clock terminal CLK to the flip-flop of the scan chain 18-2. That is, the clock gating circuit 20-1 may output the received clock CLK via the gated enable clock ECLK only when at least one of the signals input to the test enable terminal TE and the function enable terminal EN is at logic "1". The gated enable clock ECLK may be referred to as the enable clock ECLK. In addition, the gated enable clock ECLK may be referred to as a gated clock signal.

[0044] When the register setting signal RS is set to logic "1", the first OR gate 311 maintains the modified scan enable signal MSE at logic "1" regardless of the scan enable signal SE. In response to this state, the clock gating circuit 20-1 can send the received clock CLK to the flip-flop of the scan chain 18-2 via the gated enable clock ECLK regardless of the function enable signal FEN. On the other hand, when the register setting signal RS is set to logic "0", the test clock gating circuit 300 can send or block the gated enable clock ECLK in the capture part in response to the function enable signal FEN, regardless of the function enable signal FEN. Figure 2 The clock gating circuit 20 in is similar.

[0045] The scan chain 18-2 may include a plurality of flip-flops connected in a chain and a logic circuit connected to the plurality of flip-flops. The scan chain 18-2 may be responsive to the enable clock ECLK to Figure 1 The scan data sent by the decompressor 16 is loaded into the flip-flops of the plurality of scan chains 18, and the output of the logic circuit connected to the plurality of flip-flops can be captured and sent to Figure 1 The compressor 19 outputs the captured data.

[0046] In the test clock gating circuit 300, when the register setting signal RS is set to logic "1", the enable clock ECLK can be sent from the clock gating circuit 20-1 to the scan chain 18-2 even in the capture part during the scan test operation. Therefore, during the capture part of the scan test operation, the capture operation can be accurately performed at the desired time in the scan chain 18-2. This can improve the test time and test coverage.

[0047] Figure 4 The test clock gating circuit 300 connected to a single scan chain 18-2 is shown. However, a scan chain may be configured for each clock domain according to an operating frequency of a logic circuit of a semiconductor device, and the test clock gating circuits may be connected to the scan chains, respectively.

[0048] Figure 5 A portion of a circuit including a plurality of scan chains SC_0 to SC_n of a logic built-in self-test (LBIST) structure 500 according to an example embodiment is shown. Figure 6 Shows Figure 5 Detailed connections between the four test clock gating circuits 300_0 to 300_3 and the four scan chains SC_0 to SC_3 in the circuit of the LBIST structure 500 .

[0049] First, refer to Figure 5 , the LBIST structure 500 may include a clock generator 14-1, a plurality of test clock gating circuits 300_0 to 300_n (which may be referred to as first test clock gating circuits 300_0 to nth test clock gating circuits 300_n), a plurality of scan chains SC_0 to SC_n (which may be referred to as first scan chains SC_0 to nth scan chains SC_n), a decompressor 16, and a compressor 19. Figure 5 In the LBIST structure, for the convenience of description, the Figure 1 The blocks in LBIST are identical to the blocks in LBIST.

[0050] The clock generator 14-1 may receive the shift clock CLKs and the functional operation clock CLKf, and output the clocks CLK_0:n in response to the scan enable signal SE. The clock generator 14-1 may output the shift clock CLKs as the clocks CLK_0 to CLK_n when the scan enable signal SE is at logic "1", and may output the functional operation clock CLKf as the clocks CLK_0 to CLK_n in the capture portion where the scan enable signal SE is at logic "0". The frequency of the shift clock CLKs may be slower (or lower) than the frequency of the functional operation clock CLKf. The functional operation clock CLKf may have an operating frequency for operating a logic circuit of a scan chain. For example, the clock generator 14-1 may include a first clock generator that receives a shift clock CLKs and a first functional operation clock CLKf and generates a first clock CLK_0 in response to a scan enable signal SE, and a second clock generator that receives a shift clock CLKs and a second functional operation clock CLKf and generates a second clock CLK_1 in response to the scan enable signal SE.

[0051] Each of the plurality of test clock gating circuits 300_0 to 300_n may have a Figure 4 Each of the plurality of test clock gating circuits 3000 to 300n may include an OR gate that receives a scan enable signal SE and a corresponding register setting signal among register setting signals RS_0 to RS_n and generates a modified scan enable signal MSE. Each of the plurality of test clock gating circuits 300_0 to 300_n may receive a corresponding clock among a plurality of clock signals CLK_0 to CLK_n and may output an enable clock ECLK in response to the modified scan enable signal MSE and a function enable signal FEN.

[0052] Each of the plurality of scan chains SC_0 to SC_n may receive a scan enable signal SE and a corresponding enable clock among the plurality of gated enable clocks ECLK_0 to ECLK_n.

[0053] The decompressor 16 may transmit the scan data. For example, the decompressor 16 may include a pseudo-random pattern generator having a linear feedback shift register, a phase shifter, etc., but example embodiments are not limited thereto.

[0054] The compressor 19 may generate a test result based on the captured data. For example, the compressor 19 may include an exclusive OR (XOR) compressor, a multi-input signature register, a comparator, etc., but example embodiments are not limited thereto.

[0055] Figure 5 It is shown that only one scan chain is connected to one of the test clock gating circuits, but this is only an example. The number of scan chains that can be connected to one test clock gating circuit may vary depending on the configuration of the logic circuits operating at the same operating frequency.

[0056] Figure 6 yes Figure 5 Detailed diagram of the connection relationship between the four test clock gating circuits and the four scan chains in the LBIST structure 500. Figure 6 , the first test clock gating circuit 300_0 may include a first OR gate 311_0 and a first clock gating circuit 20_0. The second test clock gating circuit 300_1 may include a second OR gate 311_1 and a second clock gating circuit 20_1. The third test clock gating circuit 300_2 may include a third OR gate 311_2 and a third clock gating circuit 20_2. The fourth test clock gating circuit 300_3 may include a fourth OR gate 311_3 and a fourth clock gating circuit 20_3.

[0057] Each OR gate may receive the scan enable signal SE and the register setting signal corresponding thereto, and generate a modified scan enable signal MSE. For example, the first OR gate 311_0 may receive the scan enable signal SE and the first register setting signal RS_0, and generate a first modified scan enable signal MSE_0. The second OR gate 311_1 may receive the scan enable signal SE and the second register setting signal RS_1, and generate a second modified scan enable signal MSE_1. The third OR gate 311_2 may receive the scan enable signal SE and the third register setting signal RS2, and generate a third modified scan enable signal MSE 2. The fourth OR gate 311_3 may receive the scan enable signal SE and the fourth register setting signal RS_3, and generate a fourth modified scan enable signal MSE_3.

[0058] Each of the first to fourth clock gating circuits 20_0 to 20_3 may output the input clock CLK as the gating enable clock ECLK in response to a first logic value (eg, logic “1”) of the modified scan enable signal MSE or a first logic value (eg, logic “1”) of the function enable signal FEN. Figure 5 and Figure 6 , for example, the first clock gating circuit 20_0 may output the first clock CLK_0 as the first enable clock ECLK_0 in response to the logic “1” of the first modified scan enable signal MSE_0 or the logic “1” of the function enable signal FEN. The second clock gating circuit 20_1 may output the second clock CLK_1 as the second enable clock ECLK_1 in response to the logic “1” of the second modified scan enable signal MSE_1 or the logic “1” of the function enable signal FEN. The third clock gating circuit 20_2 may output the third clock CLK_2 as the third enable clock ECLK_2 in response to the logic “1” of the third modified scan enable signal MSE_2 or the logic “1” of the function enable signal FEN. The fourth clock gating circuit 20_3 may output the fourth clock CLK_3 as the fourth enable clock ECLK_3 in response to the logic “1” of the fourth modified scan enable signal MSE_3 or the logic “1” of the function enable signal FEN.

[0059] Each of the first to fourth scan chains SC_0 to SC_3 can load scan test data into a flip-flop in response to an input gating enable clock (e.g., the first to fourth enable clocks ECLK_0 to ECLK_3), and can capture the output of a combinational logic circuit connected to the flip-flop and output the captured data.

[0060] The test clock gating circuit inputted with the register setting signal set to logic "1" can accurately send the enable clock to the scan chain in the capture part of the scan test operation, so that the data generated by the logic circuit can be captured on the flip-flop of the scan chain. The test clock gating circuit inputted with the register setting signal set to logic "0" sends the enable clock to the scan chain or blocks the enable clock according to the state of the function enable signal FEN in the capture part of the scan test operation.

[0061] In an example embodiment of determining which register setting signal among a plurality of register setting signals is to be set to logic "1", a scan test is first performed in a state where all register setting signals of the LBIST structure 500 are set to logic "0". Then, a scan chain whose test coverage is weaker than a reference value may be determined, and the register setting signal corresponding to the scan chain may be set to logic "1".

[0062] Additionally, when the scan test operation is performed in a state where all register setting signals are set to logic "1", all clock gating circuits send enable clocks to the scan chain in the capture section. Therefore, there can be an effect of performing the test in a state where the power stress of the semiconductor device including the LBIST is high (i.e., in an aging state).

[0063] Figure 7 is a timing diagram of a scan test operation according to an example embodiment. Figures 5 to 7 , the scan test operation may include a shift-in portion (Shift-in), a capture portion (Capture), and a shift-out portion (Shift-out) for each test mode in sequence. The clock generator 14-1 in the shift-in portion (Shift-in) may send a shift clock CLKs to the first test clock gating circuit 300_0 via the first clock CLK_0 in response to the logic "1" of the scan enable signal SE. The first OR gate 311_0 maintains the first modified scan enable signal MSE_0 at logic "1" in response to the logic "1" of the first register setting signal RS_0. The first clock gating circuit 20_0 outputs the first clock CLK_0, which is the same as the shift clock CLKs, to the first scan chain SC_0 via the first enable clock ECLK_0 in response to the first modified scan enable signal MSE_0 of logic "1". The trigger of the first scan chain SC_0 may latch the scan data in response to the first enable clock ECLK_0 of the same frequency as the shift clock CLKs.

[0064] The clock generator 14_1 in the capture part (Capture) may send two pulses of the functional operation clock CLKf to the first test clock gating circuit 300_0 via the first clock CLK_0 in response to the scan enable signal SE of logic "0". The first clock gating circuit 20_0 may output the first clock CLK_0 including the two pulses of the functional operation clock CLKf to the first scan chain SC_0 via the first enable clock ECLK_0 in response to the first modified scan enable signal MSE_0 of logic "1", regardless of the function enable signal FEN. The flip-flop of the first scan chain SC_0 may capture data output from the logic circuit connected to the flip-flop in response to the first enable clock ECLK_0 including the two pulses of the functional operation clock CLKf. That is, in the example embodiment, the first register setting signal RS_0 is set to logic "1". Therefore, data may be accurately captured in the scan chain regardless of the state of the function enable signal FEN randomly set in the capture part output by the function enable logic FBL_0.

[0065] Figure 7 The timing chart of shows that the clock generator 14 - 1 outputs two pulses of the functional operation clock CLKf in the capture section, but the clock generator 14 - 1 may output one pulse of the functional operation clock CLKf or one pulse of the shift clock CLKs.

[0066] The clock generator 14-1 in the shift-out part (Shift-out) can send the shift clock CLKs to the first test clock gating circuit 300_0 again via the first clock CLK_0 in response to the scan enable signal SE of logic "1". The first clock gating circuit 20_0 outputs the first enable clock ECLK_0, which is the same as the shift clock CLKs, to the first scan chain SC_0 in response to the first modified scan enable signal MSE_0 of logic "1". The flip-flops of the first scan chain SC_0 can sequentially output the captured data in response to the first enable clock ECLK_0.

[0067] Figure 8 Connections between a pattern counter, a test clock gating circuit, and a scan chain in a LBIST according to example embodiments are shown. Fig. 9 yes Figure 8 1 is a timing diagram of the count signal of the mode counter and the modified scan enable signal.

[0068] In addition to the count signal CNT of the pattern counter 12_3 being input to the OR gate (eg, the first OR gate 611_0) of the test clock gating circuit (eg, the first test clock gating circuit 600_0) instead of the register setting signal RS, Figure 8 Configuration and Figure 5 and Figure 6 The configuration is the same. Figure 8 Only three scan chains (i.e., SC_0 to SC_2) and three test clock gating circuits (i.e., 600_0 to 600_2) connected to the three scan chains (i.e., SC_0 to SC_2) are shown, but this is only an example. A large number of scan chains can be set, and the test clock gating circuits can be connected to the scan chains respectively. In this case, each test clock gating circuit can receive a count signal corresponding to it from the pattern counter 12_3.

[0069] refer to Fig. 9 , the three counting signals CNT_0 to CNT_2 from the pattern counter 12_3 are input to the corresponding test clock gating circuit. In addition, Fig. 9 The timing of generating the modified scan enable signal is shown. The first counting signal CNT_0 has a value when the scan enable signal SE changes from logic "0" to logic "1" (ie, each time a test mode starts (eg, each time the number of modes ( Fig. 9 The first cycle of the switching is increased when the "number of modes" shown in FIG. 1 increases. The cycle of the second counting signal CNT_1 is twice as long as the first cycle of the first counting signal CNT_0. The cycle of the third counting signal CNT_2 is twice as long as the cycle of the second counting signal CNT_1.

[0070] When the first counting signal CNT_0 is input to the first OR gate 611_0 of the first test clock gating circuit 600_0, the first modified scan enable signal MSE_0 is in four even patterns (eg, Fig. 9 , "2", "4", "6", and "8" (shown in the figure)) in the capture portion (i.e., in the portion where the scan enable signal SE is at logic "0"), logic "1" is maintained. Therefore, the first enable clock ECLK_0 is sent to the first scan chain SC_0, so that accurate capture can be performed. In addition, in the remaining four odd-numbered patterns (e.g., Fig. 9 In the capture parts (shown as numbers “1”, “3”, “5” and “7”), the capture operation can be performed according to the state of the function enable signal FEN.

[0071] When the second count signal CNT_1 is input to the second OR gate 611_1 of the second test clock gating circuit 600_1, the second modified scan enable signal MSE_1 maintains logic "1" in the capture parts of the third mode, the fourth mode, the seventh mode, and the eighth mode for every eight modes. Therefore, the second enable clock ECLK_1 is sent to the second scan chain SC_1, so that accurate capture can be performed. In addition, in the capture parts of the remaining first mode, the second mode, the fifth mode, and the sixth mode, a capture operation can be performed according to the state of the function enable signal FEN.

[0072] When the third counting signal CNT_2 is input to the third OR gate 611_2 of the third test clock gating circuit 600_2, the third modified scan enable signal MSE_2 maintains logic "1" in the capture parts of the fifth mode, the sixth mode, the seventh mode, and the eighth mode for every eight modes. Therefore, accurate capture can be performed in the third scan chain SC_2. In addition, in the capture parts of the remaining first mode, the second mode, the third mode, and the fourth mode, a capture operation can be performed according to the state of the function enable signal FEN.

[0073] exist Figure 8 In the LBIST shown, the pattern count information is used to accurately send an enable clock to the scan chain at a constant rate in the capture part for every specific number of patterns. Therefore, the capture operation is accurately performed and the test coverage is improved.

[0074] Fig.10 Shows Figure 8 Example of modification of the OR gate for testing clock gating circuits. Fig.10 , each OR gate can receive the count signal, scan enable signal SE and register setting signal RS_all corresponding thereto. When the register setting signal RS_all is set to logic "1", all modified scan enable signals remain at logic "1". Therefore, all test clock gating circuits can accurately send an enable clock for capture to all scan chains in the capture part.

[0075] Fig.11 Connections between a pulse generator, a test clock gating circuit, and a scan chain in a LBIST according to an example embodiment are shown.

[0076] refer to Fig.11 ,and Figure 8 In contrast, the pulse generator 700 can receive the count signals CNT_0 to CNT_2 of the pattern counter 12_3 and generate a plurality of pulse signals P_0 to P_3. The OR gate of each test clock gating circuit can receive a corresponding pulse signal among the plurality of pulse signals P_0 to P_3 and send an enable clock to the corresponding scan chain in response to the corresponding pulse signal.

[0077] Fig. 12A yes Fig.11 Detailed diagram of a pulse generator 700 . Fig. 12B yes Fig.11 and Fig. 12A The timing diagram of the pulse signal and the modified scan enable signal. Fig. 12C yes Fig. 12A The truth table of the pulse generator. In the following, reference is made to FIG. 12A to FIG. 12Cto describe the pulse generator circuit and its operation.

[0078] refer to Fig.11 and Fig. 12A , the pulse generator 700 may include: a first AND gate D, receiving the first counting signal CNT_0 and the second counting signal CNT_1, and generating a first pulse signal P_0; a first XOR gate A, receiving the second counting signal CNT_1 and the first counting signal CNT_0, and generating a first internal signal I_0; a first NAND gate E, receiving the first pulse signal P_0 and the first internal signal I_0, and generating a second pulse signal P_1; a second XOR gate B, receiving the first counting signal CNT_0 and the third counting signal CNT_2, and generating a second internal signal I_1; a second AND gate F, receiving the first internal signal I_0 and the second internal signal I_1, and generating a third pulse signal P_2; a third XOR gate C, receiving the second counting signal CNT_1 and the third counting signal CNT_2, and outputting a third internal signal I_2; and a third AND gate G, receiving the first internal signal I_0 and the third internal signal I_2, and generating a fourth pulse signal P_3.

[0079] refer to Fig. 12B , the first counting signal CNT_0 has a first period that switches for each test mode (i.e., each time the scan enable signal SE switches from logic "0" to logic "1"). The second period of the second counting signal CNT_1 is twice as long as the first period of the first counting signal CNT_0. The period of the third counting signal CNT_2 is twice as long as the second period of the second counting signal CNT_1. The first counting signal CNT_0 switches each time the scan enable signal SE switches from logic "0" to logic "1".

[0080] Fig. 12C The truth value of the first counting signal CNT_0 to the third counting signal CNT_2 is input to Fig. 12A The pulse generator 700 is a first internal signal I_0 to a third internal signal I_2 and a logic value of each pulse.

[0081] Reference together Fig. 12B and Fig. 12C , each of the four pulse signals P_0 to P_3 can maintain logic "1" only when testing one mode for every four test modes, and maintain logic "0" during the test parts of the remaining three modes. In addition, the logic "1" parts of the pulse signals do not overlap with each other (that is, offset from each other). Each pulse signal can maintain logic "1" only during different half-cycle times for every two cycles of the first count signal.

[0082] The first pulse signal P_0 may maintain logic "1" in the portion testing the fourth mode and the eighth mode. The second pulse signal P_1 may maintain logic "1" in the portion testing the first mode and the fifth mode. The third pulse signal P_2 may maintain logic "1" in the portion testing the second mode and the seventh mode. The fourth pulse signal P_3 may maintain logic "1" in the portion testing the third mode and the sixth mode.

[0083] FIG. 12A to FIG. 12C It is shown that each pulse signal only keeps logic "1" in the part that tests a non-overlapping pattern for every four test patterns. However, this can be changed to keep logic "1" in the part that tests only one pattern for every specific number of test patterns according to the number of test clock gating circuits of the LBIST circuit.

[0084] Reference together Fig.11 and Fig. 12B, each of the OR gates of the first test clock gating circuit 600_0 to the fourth test clock gating circuit 600_3 can generate a modified scan enable signal MSE in response to the corresponding pulse signal and the scan enable signal SE. The first OR gate of the first test clock gating circuit 600_0 receiving the first pulse signal P_0 can maintain the logic "1" of the first modified scan enable signal MSE_0 during the test parts of the fourth mode and the eighth mode. Therefore, even in the capture part during the test parts of the fourth mode and the eighth mode, the first test clock gating circuit 600_0 can accurately provide the first enable clock ECLK_0 to the first scan chain SC_0. The second OR gate of the second test clock gating circuit 600_1 receiving the second pulse signal P_1 can maintain the logic "1" of the second modified scan enable signal MSE_1 during the test parts of the first mode and the fifth mode. Therefore, even in the capture portion during the test portion of the first mode and the fifth mode, the second test clock gating circuit 600_1 can accurately provide the second enable clock ECLK_1 to the second scan chain SC_1. The third OR gate of the third test clock gating circuit 600_2 receiving the third pulse signal P_2 can maintain the logic "1" of the third modified scan enable signal MSE_2 during the test portion of the second mode and the seventh mode. Therefore, even in the capture portion during the test portion of the second mode and the seventh mode, the third test clock gating circuit 600_2 can accurately provide the third enable clock ECLK_2 to the third scan chain SC_2. The fourth OR gate of the fourth test clock gating circuit 600_3 receiving the fourth pulse signal P_3 can maintain the logic "1" of the fourth modified scan enable signal MSE_3 during the test portion of the third mode and the sixth mode. Therefore, even in the capture section during the test section of the third mode and the sixth mode, the fourth test clock gating circuit 600_3 can accurately provide the fourth enable clock ECLK_3 to the fourth scan chain SC_3.

[0085] exist Fig.11 In the LBIST of , each scan chain can accurately receive the enable clock in the capture part while testing one mode for every four test modes. As a result, the loss of test coverage caused by the uncertainty of the capture part caused by the randomness of the function enable signal FEN in the comparative example can be prevented. For each scan chain, the enable clock is accurately sent in the capture part for one of the four modes (i.e., 25% of the total test mode). In addition, the enable clock is accurately provided in the capture part of different modes for each scan chain. Therefore, appropriate power consumption effects can be expected together with improved test coverage.

[0086] Fig.13 Shows Fig.11A modified example of the OR gates of the first test clock gating circuit 600_0 to the fourth test clock gating circuit 600_3. Fig.13 and will Fig.13 and Fig.10 For comparison, each OR gate can receive the count signal, scan enable signal SE and register setting signal RS_all corresponding thereto. When the register setting signal RS_all is set to logic "1", all modified scan enable signals MSE_0 to MSE_3 remain at logic "1". Therefore, all test clock gating circuits 600_0 to 600_3 can accurately send enable clocks ECLK_0 to ECLK_3 for capture to all scan chains SC_0 to SC_3 in the capture part.

[0087] Fig.14 is a graph showing the test coverage of the LBIST according to the example embodiment and the test coverage of the LBIST according to the comparative example. Fig.14 In the graph, the X-axis represents the number of patterns to be tested, and the Y-axis represents the test coverage. Fig.14 , when testing the same number of test patterns, the LBIST that accurately provides an enable clock to the scan chain during the capture part of the scan operation can achieve better test coverage than the LBIST according to the comparative example.

[0088] Fig.15 1 is a block diagram illustrating a semiconductor device 1000 including a plurality of intellectual property (IP) cores according to an example embodiment. For example, an IP core may include a circuit that performs a specific function and may have a design that includes a trade secret. Fig.15 , the semiconductor device 1000 may include one or more IP cores 110, 120, 130, 140 and 150 (e.g., a central processing unit (CPU) 110, a graphics processing unit (GPU) 120, a multimedia core (MMC) 130, a memory controller 140, and a peripheral interface 150), a system bus 160, and a test interface 180. For example, the semiconductor device 1000 may include an application processor as a system on chip. The application processor may include IP cores (e.g., CPU 110, GPU 120, MMC 130, memory controller 140, and peripheral interface 150 and test interface 180) connected to each other via the system bus 160. In addition, the application processor may also include a modem. Fig.15 In the figure, each IP core is shown as one, but the semiconductor device 1000 may also include multiple CPUs or multiple GPUs.

[0089] The Advanced Microcontroller Bus Architecture (AMBA) protocol of Advanced RISC Machine (ARM) may be applied as a standard for the system bus 160. The bus types of the AMBA protocol may include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced Extensible Interface (AXI), AXI4, and AXI Coherence Extension (ACE). In addition, other types of protocols optimized for each system (e.g., uNetwork, CoreConnect, or Open Core Protocol) may be applied.

[0090] The CPU 110 may control all operations of the application processor. For example, the CPU 110 may perform various management operations by executing software for managing the operations of various IP cores in the application processor. Fig.15 As shown, the logic circuit of the CPU 110 may be coupled to the circuit of the first LBIST LB_0 in which a scan chain is formed for each clock domain and an enable clock is accurately provided to the scan chain even in a capture portion through a test clock gating circuit.

[0091] GPU 120 includes a graphics processing device and renders graphics data. The graphics processing device converts the graphics data corresponding to the two-dimensional or three-dimensional object into a two-dimensional pixel representation and creates a frame for display. Semiconductor device 1000 (i.e., application processor) may also include a neural processing unit (NPU) as a computing device for performing calculations for deep learning (or neural network). When an application based on deep learning is executed on an application processor, performance can be guaranteed by performing the NPU for calculating deep learning. The logic circuits of GPU 120 and NPU may be coupled to the circuit of the second LBIST LB_1, in which a scan chain is formed for each clock domain, and by testing the clock gating circuit, the clock is accurately provided to the scan chain even if it is enabled in the capture part.

[0092] MMC 130 can receive image data from an external source such as a camera, and directly perform image processing. That is, MMC 130 can include several modules for recording and playing videos (e.g., recording and replaying video images). The logic circuit of MMC 130 can also be coupled to the circuit of the third LBIST LB_2, in which a scan chain is formed for each clock domain, and by testing the clock gating circuit, the clock is accurately provided to the scan chain even if the enabling clock is in the capture part.

[0093] The memory controller 140 functions as a data interface with a memory device that may be connected to the outside of the semiconductor device 1000. The peripheral interface 150 may include a storage interface and a display interface. The memory controller 140 and the peripheral interface 150 may each include a LBIST according to example embodiments.

[0094] The test interface 180 may start a scan test of the LBIST of each IP core using a Joint Test Action Group (JTAG) BIST interface, receive a setting value of a setting register signal according to some example embodiments, and output a test result value to the outside.

[0095] Even when mounted on a real system, a semiconductor device including a LBIST according to example embodiments may achieve high test coverage while maintaining appropriate test power consumption.

[0096] In some example embodiments, Figure 1 , Figure 2 , Figures 4 to 6 , Figure 8 , Fig.10 , Fig.11 , Fig. 12A , Fig.13 and Fig.15 Each component represented by the shown box can be implemented as various numbers of hardware and / or firmware structures that perform the above-mentioned various functions according to the example embodiments. For example, at least one of these components may include various hardware components including the following: digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuits using direct circuit structures (e.g., memories, processors, logic circuits, lookup tables, etc.) configured to perform various functions under the control of one or more microprocessors or other control devices. In addition, at least one of these components may also include a processor, microprocessor, etc. such as a central processing unit (CPU) that performs various functions, or may be implemented by a processor, microprocessor, etc. such as a central processing unit (CPU) that performs various functions.

[0097] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A logic built-in self-test circuit, comprising: a first OR gate configured to: receive a scan enable signal and a first register setting signal, and generate a first modified scan enable signal; A first clock gating circuit configured to: receive a first clock according to the first modified scan enable signal and a first function enable signal, and output a first enable clock; a first scan chain configured to: load first scan data into a first flip-flop according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flop, and output the captured data; a second OR gate configured to: receive the scan enable signal and the second register setting signal, and generate a second modified scan enable signal; A second clock gating circuit is configured to: receive a second clock according to the second modified scan enable signal and the second function enable signal, and output a second enable clock; as well as a second scan chain configured to: load second scan data into a second flip-flop according to the second enable clock, capture an output of a second logic circuit connected to the second flip-flop, and output the captured data; Wherein, at least one of the first clock gating circuit and the second clock gating circuit is configured to output a corresponding enable clock when a corresponding register setting signal has a first logic value, regardless of a corresponding function enable signal.

2. The logic built-in self-test circuit according to claim 1, wherein: The first clock gating circuit is further configured to output or block the first enable clock according to a state of the first function enable signal in a capture portion of a scan test operation when the first register set signal has a second logic value different from the first logic value.

3. The logic built-in self-test circuit according to claim 2, further comprising: A first clock generator, configured to: receive a shift clock and a third clock, generate the first clock according to the scan enable signal, and send the first clock to the first clock gating circuit; as well as a second clock generator configured to: receive the shift clock and the fourth clock, generate the second clock according to the scan enable signal, and send the second clock to the second clock gating circuit; wherein the third clock has the same frequency as the operating frequency of the first logic circuit, and The fourth clock has a frequency that is the same as an operating frequency of the second logic circuit.

4. The logic built-in self-test circuit according to claim 3, wherein: When the scan enable signal has the first logic value, the first clock is equal to the shift clock, and When the scan enable signal has the second logic value different from the first logic value, the first clock includes one or two pulses of the third clock.

5. The logic built-in self-test circuit according to claim 4, further comprising: a decompressor, comprising a linear feedback shift register and a phase shifter, the decompressor being configured to generate the first scan data and the second scan data; as well as A compressor is configured to receive output data from each of the first scan chain and the second scan chain and generate a test result.

6. A logic built-in self-test circuit, comprising: The decompressor is configured to: sequentially generate a plurality of test patterns; A mode counter configured to: count the number of the plurality of test modes and generate a counting signal; a first OR gate configured to: receive a scan enable signal and a first count signal among the count signals, and generate a first modified scan enable signal; A first clock gating circuit configured to: receive a first clock according to the first modified scan enable signal and a first function enable signal, and output a first enable clock; as well as a first scan chain configured to: load first scan data into a first flip-flop according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flop, and output the captured data; The first clock gating circuit is further configured to: output the first enable clock when the first counting signal has a first logic value, regardless of the state of the first function enable signal.

7. The logic built-in self-test circuit according to claim 6, further comprising: a second OR gate configured to: receive the scan enable signal and a second count signal among the count signals, and generate a second modified scan enable signal; A second clock gating circuit is configured to: receive a second clock according to the second modified scan enable signal and the second function enable signal, and output a second enable clock; as well as a second scan chain configured to: load second scan data into a second flip-flop according to the second enable clock, capture an output of a second logic circuit connected to the second flip-flop, and output the captured data; The second clock gating circuit is further configured to: output the second enable clock when the second counting signal has the first logic value, regardless of the state of the second function enable signal.

8. The logic built-in self-test circuit according to claim 7, wherein: The first counting signal has a first period, and The second counting signal has a second period, and the second period is twice as long as the first period.

9. The logic built-in self-test circuit according to claim 8, further comprising: a first clock generator configured to: receive a shift clock and a third clock having an operating frequency of the first logic circuit, generate the first clock according to the scan enable signal, and send the first clock to the first clock gating circuit; as well as The second clock generator is configured to receive the shift clock and a fourth clock having an operating frequency of the second logic circuit, generate the second clock according to the scan enable signal, and send the second clock to the second clock gating circuit.

10. The logic built-in self-test circuit according to claim 9, wherein: Each of the first OR gate and the second OR gate is further configured to receive a register setting signal, and The first clock gating circuit and the second clock gating circuit are further configured to output the first enable clock and the second enable clock respectively when the register setting signal has the first logic value, regardless of the state of the first function enable signal and the state of the second function enable signal.

11. A logic built-in self-test circuit, comprising: The decompressor is configured to: sequentially generate a plurality of test patterns; a pattern counter configured to: count the number of the plurality of test patterns generated by the decompressor and generate a counting signal; a pulse generator configured to: receive at least some of the count signals and generate a pulse signal; A first OR gate configured to: receive a scan enable signal and a first pulse signal among the pulse signals, and generate a first modified scan enable signal; A first clock gating circuit configured to: receive a first clock according to the first modified scan enable signal and a first function enable signal, and output a first enable clock; as well as The first scan chain is configured to: load the first scan data into the first trigger according to the first enable clock, and capture and output the output of the first logic circuit connected to the first trigger.

12. The logic built-in self-test circuit according to claim 11, further comprising: a second OR gate configured to: receive a second pulse signal from among the scan enable signal and the pulse signal, and generate a second modified scan enable signal; A second clock gating circuit is configured to: receive a second clock according to the second modified scan enable signal and the second function enable signal, and output a second enable clock; a second scan chain configured to: load second scan data into a second flip-flop according to the second enable clock, and capture and output an output of a second logic circuit connected to the second flip-flop; a third OR gate configured to: receive a third pulse signal among the scan enable signal and the pulse signal, and generate a third modified scan enable signal; a third clock gating circuit configured to: receive a third clock according to the third modified scan enable signal and the third function enable signal, and output a third enable clock; a third scan chain, configured to: load third scan data into a third flip-flop according to the third enable clock, and capture and output an output of a third logic circuit connected to the third flip-flop; a fourth OR gate configured to: receive a fourth pulse signal among the scan enable signal and the pulse signal, and generate a fourth modified scan enable signal; a fourth clock gating circuit, configured to: receive a fourth clock according to the fourth modified scan enable signal and the fourth function enable signal, and output a fourth enable clock; as well as The fourth scan chain is configured to: load fourth scan data into a fourth flip-flop according to the fourth enable clock, and capture and output an output of a fourth logic circuit connected to the fourth flip-flop.

13. The logic built-in self-test circuit according to claim 12, wherein: The counting signal includes a first counting signal, a second counting signal and a third counting signal, wherein the first counting signal has a first cycle that switches according to a conversion of a logic value of the scan enable signal, wherein the second counting signal has a second period, the second period is twice as long as the first period, and The third counting signal has a third period, and the third period is twice as long as the second period.

14. The logic built-in self-test circuit according to claim 13, wherein: Each of the first to fourth pulse signals has a first logic value in a section for testing one pattern for every four test patterns.

15. The logic built-in self-test circuit according to claim 14, wherein: The first logic values ​​of the first pulse signal to the fourth pulse signal are offset from each other.

16. The logic built-in self-test circuit according to claim 11, further comprising a first clock generator, the first clock generator being configured to: receive a shift clock and a third clock having an operating frequency of the first logic circuit, generate the first clock according to the scan enable signal, and send the first clock to the first clock gating circuit.

17. The logic built-in self-test circuit according to claim 16, wherein: When the scan enable signal is at logic "1", the first clock is equal to the shift clock, and When the scan enable signal is at logic "0", the first clock is equal to the third clock.

18. The logic built-in self-test circuit according to claim 13, wherein: Each of the first to fourth OR gates is further configured to: receive a register setting signal, and The first clock gating circuit to the fourth clock gating circuit are configured to output the first enable clock to the fourth enable clock when the register setting signal is at logic "1".

19. A semiconductor device comprising: a first core including a first logic circuit and a first logic built-in self-test circuit, wherein the first logic built-in self-test circuit is configured to perform a first scan test on the first logic circuit; as well as a second core including a second logic circuit and a second logic built-in self-test circuit, wherein the second logic built-in self-test circuit is configured to perform a second scan test on the second logic circuit, Wherein, each of the first logic built-in self-test circuit and the second logic built-in self-test circuit comprises: The decompressor is configured to: sequentially generate a plurality of test patterns; a pattern counter configured to: count the number of the plurality of test patterns generated and generate a counting signal; a pulse generator configured to: receive at least some of the count signals and generate a pulse signal; A first OR gate configured to: receive a scan enable signal and a first pulse signal among the pulse signals, and generate a first modified scan enable signal; a first clock gating circuit configured to: receive a first clock and output a first enable clock according to the first modified scan enable signal and the first function enable signal; and The first scan chain is configured to: load the first scan data into the first trigger according to the first enable clock, and capture and output the output of the first logic circuit connected to the first trigger.

20. The semiconductor device according to claim 19, wherein The first pulse signal has a pulse of a first logic value in a portion for testing one pattern for every specific number of consecutive patterns among the plurality of test patterns.

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