Semiconductor device and manufacturing method thereof

Abstract

Optical devices and methods of manufacture are presented in which a multi-level connection is utilized to transmit optical signals to and receive optical signals from the optical device. In an embodiment, a multi-level connection unit receives optical signals from outside of the optical device, where the optical signals are initially located in a plurality of layers. The multi-level connection unit then routes the optical signals into the optical component of the single layer. The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Electrical signaling and processing is a technology used for signal transmission and processing. In recent years, optical signaling and processing has been used in an increasing number of applications, especially due to the use of optical fiber related applications for signal transmission.

[0003] Optical signals and processing are often combined with electrical signals and processing to provide sophisticated applications. For example, optical fibers can be used for long-range signal transmission, and electrical signals can be used for short-range signal transmission and processing and control. Thus, a device integrating long-range optical components and short-range electrical components is formed for conversion between optical and electrical signals and processing of optical and electrical signals. Thus, a package may include: an optical (photonic) die including an optical device and an electronic die including an electronic device. Summary of the invention

[0004] Some embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: receiving a multi-level connection unit, the multi-level connection unit comprising: a first level, including a first reflector having a first orientation; a second level, including a second reflector having a second orientation the same as the first orientation; and a third level, including a third reflector, the third reflector having a third orientation different from the first orientation; and attaching the multi-level connection unit to a first optical package, the first optical package comprising a semiconductor die.

[0005] Other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: attaching an electrical integrated circuit to an optical interposer; and bonding a first-level active layer above the electrical integrated circuit and the optical interposer, the first-level active layer comprising: a first optical component; and a first reflector aligned with the first optical component.

[0006] Some other embodiments of the present application provide a semiconductor device, comprising: a multi-level connection unit, the multi-level connection unit comprising: a first level, including a first reflector; a second level, including a second reflector, a first lens and a second lens; and a third level, including a third reflector and a third lens; and a first optical package attached to the multi-level connection unit, the first optical package comprising a semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 9 The formation of a first optical package according to some embodiments is shown.

[0009] Fig.10 The bonding of a first optical package is shown according to some embodiments.

[0010] FIG. 11A to FIG. 11B The formation of a first level active layer is shown according to some embodiments.

[0011] FIG. 12A to FIG. 12B The formation of a second level active layer according to some embodiments is shown.

[0012] Fig.13 Bonding of a first level active layer to a substrate is shown in accordance with some embodiments.

[0013] Fig.14 Exposure of a first level active layer is shown in accordance with some embodiments.

[0014] Fig.15 A singulation process according to some embodiments is shown.

[0015] FIG. 16A to FIG. 16B The formation of a third level active layer is shown according to some embodiments.

[0016] Fig.17 Attachment of multiple levels of connection units is shown according to some embodiments.

[0017] FIG. 18A to FIG. 18B Attaching multiple levels of connectors is shown according to some embodiments.

[0018] Fig.19 The path of an optical signal is shown according to some embodiments.

[0019] FIG. 20A to FIG. 20B A multi-level connection unit is shown without multiple layers of an optical component according to some embodiments.

[0020] Fig.21 A multi-level connection unit having a constant width is shown according to some embodiments.

[0021] Fig. 22 A multi-level connection unit with a constant width bonded to an interposer is shown in accordance with some embodiments.

[0022] Figures 23 to 28DThe formation of a first level active layer over an optical interposer is shown according to some embodiments.

[0023] FIG. 29A to FIG. 29C An array of interleaved optical fibers is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0026] Embodiments will now be discussed with respect to certain embodiments in which multiple levels of connectors are utilized to provide multiple inputs to an optical device. However, the embodiments presented are intended to be illustrative and are not intended to limit the ideas presented to the precise embodiments described. Rather, the ideas presented may be incorporated into a wide variety of embodiments, and all such embodiments may be included within the overall scope of the disclosed embodiments.

[0027] Reference now Figure 1 , showing an optical interposer 100 ( Figure 5 The initial structure of Figure 1 In the particular embodiment shown in FIG. 1 , the optical interposer 100 is a photonic integrated circuit (PIC) and at this stage comprises a first substrate 101, a first insulating layer 103 and a first active layer 201 for a first optical component 203 (in Figure 1 Not shown separately, but the following Figure 21 and 2. In an embodiment, the first substrate 101, the first insulating layer 103, and the layer of material 105 for the first active layer 201 of the first optical component 203 may be collectively part of a silicon-on-insulator (SOI) substrate when starting the manufacturing process of the optical interposer 100. Looking first at the first substrate 101, the first substrate 101 may be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that allows structural support of the devices thereon.

[0028] The first insulating layer 103 may be a dielectric layer that separates the first substrate 101 from the first active layer 201 thereon, and in some embodiments, may additionally serve as a portion of a cladding material surrounding a subsequently fabricated first optical component 203 (discussed further below). In embodiments, the first insulating layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, or the like, formed using methods such as implantation (e.g., to form a buried oxide (BOX) layer), or may be deposited onto the first substrate 101 using deposition methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material and fabrication method may be used.

[0029] The material 105 for the first active layer 201 is initially (before patterning) a conformal material layer of the first active layer 201 that will be used to begin fabricating the first optical component 203. In embodiments, the material 105 for the first active layer 201 may be a semi-transparent material that may be used as a core material for the desired first optical component 203, such as a semiconductor material such as silicon, germanium, silicon germanium, combinations of these, and the like, while in other embodiments, the material 105 for the first active layer 201 may be a dielectric material such as silicon nitride, and the like, but in other embodiments, the material 105 for the first active layer 201 may be a III-V material, a lithium niobate material, or a polymer. In embodiments of depositing the material 105 for the first active layer 201, the material 105 for the first active layer 201 may be deposited using methods such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, and the like. In other embodiments where the first insulating layer 103 is formed using an implantation method, the material 105 of the first active layer 201 may initially be part of the first substrate 101 before the implantation process to form the first insulating layer 103. However, the material 105 of the first active layer 201 may be formed using any suitable material and fabrication method.

[0030] Figure 2It is shown that once the material 105 for the first active layer 201 is prepared, the first optical component 203 for the first active layer 201 is manufactured using the material 105 for the first active layer 201. In an embodiment, the first optical component 203 of the first active layer 201 may include such components as an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a buried channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler that is a narrow waveguide with a width between about 1 nm and about 200 nm, etc.), a directional coupler, an optical modulator (e.g., a Mach-Zehnder silicon photonic switch, a micro-electromechanical switch, a micro-ring resonator, etc.), an amplifier, a multiplexer, a demultiplexer, an optical-to-electrical converter (e.g., a PN junction), an electro-optical converter, a laser, a combination of these, etc. However, any suitable first optical component 203 may be used.

[0031] In order to form the first active layer 201 of the first optical component 203 starting from the initial material, the material 105 for the first active layer 201 can be patterned into a desired shape of the first active layer 201 for the first optical component 203. In an embodiment, the material 105 for the first active layer 201 can be patterned using, for example, one or more photolithography masking and etching processes. However, any suitable method of patterning the material 105 for the first active layer 201 can be utilized. For some of the first optical components 203, such as waveguides or edge couplers, the patterning process can be all or at least most of the fabrication used to form these first optical components 203.

[0032] Figure 3 It is shown that for those components that utilize further manufacturing processes, such as Mach-Zehnder silicon photonic switches that utilize resistive heating elements, additional processing can be performed before or after patterning the material for the first active layer 201. For example, implantation processes, additional deposition and patterning processes for different materials (e.g., resistive heating elements, III-V materials for converters), combinations of all of these processes, etc. can be utilized to help further manufacture various desired first optical components 203. In certain embodiments, and as Figure 3 As specifically shown in FIG. 1 , in some embodiments, epitaxial deposition of semiconductor material 301 such as germanium (e.g., for electrical / optical signal modulation and conversion) may be performed on patterned portions of material 105 of first active layer 201. In such embodiments, semiconductor material 301 may be epitaxially grown to help fabricate, for example, photodiodes for photoelectric converters. All such fabrication processes and all suitable first optical components 203 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

[0033] Figure 4It is shown that once the independent first optical component 203 of the first active layer 201 has been formed, the second insulating layer 401 can be deposited to cover the first optical component 203 and provide additional cladding material. In an embodiment, the second insulating layer 401 can be a dielectric layer that separates the independent components of the first active layer 201 from each other and from the structure above, and can additionally serve as another portion of the cladding material surrounding the first optical component 203. In an embodiment, the second insulating layer 401 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination of these, etc., formed using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of these, etc. Once the material of the second insulating layer 401 has been deposited, the material can be planarized using, for example, a chemical mechanical polishing process to planarize the top surface of the second insulating layer 401 (in an embodiment where the second insulating layer 401 is intended to completely cover the first optical component 203) or to planarize the second insulating layer 401 and the top surface of the first optical component 203. However, any suitable material and manufacturing method can be used.

[0034] Figure 5 2 shows that once the first optical component 203 of the first active layer 201 has been fabricated and the second insulating layer 401 has been formed, a first metallization layer 501 is formed to electrically connect the first active layer 201 of the first optical component 203 to the control circuit, to each other, and to subsequently attached devices (in Figure 5 Not shown, but the following Figure 6 1 and 2 ). In an embodiment, the first metallization layer 501 is formed of alternating layers of dielectric material and conductive material and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In a particular embodiment, there may be multiple metallization layers for interconnecting the various first optical components 203, but the exact number of first metallization layers 501 depends on the design of the optical interposer 100.

[0035] Furthermore, during the manufacture of the first metallization layer 501, one or more second optical components 503 may be formed as part of the first metallization layer 501. In some embodiments, the second optical components 503 of the first metallization layer 501 may include components such as couplers (e.g., edge couplers, grating couplers, etc.) for connecting to external signals, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (e.g., Mach-Zehnder silicon photonic switches, micro-electromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optical converters, lasers, combinations of these, etc. However, any suitable optical components may be used for the one or more second optical components 503.

[0036] In an embodiment, the one or more second optical components 503 may be formed by initially depositing a material for the one or more second optical components 503. In an embodiment, the material for the one or more second optical components 503 may be a dielectric material such as silicon nitride, silicon oxide, combinations of these, or a semiconductor material such as silicon, deposited using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, etc. However, any suitable material and any suitable deposition method may be utilized.

[0037] Once the material for the one or more second optical components 503 has been deposited or otherwise formed, the material can be patterned into a desired shape for the one or more second optical components 503. In an embodiment, the material for the one or more second optical components 503 can be patterned using, for example, one or more photolithographic masking and etching processes. However, any suitable method of patterning the material for the one or more second optical components 503 can be utilized.

[0038] For some of the one or more second optical components 503, such as waveguides or edge couplers, the patterning process may be all or at least a majority of the fabrication used to form these components. In addition, for those components that utilize further fabrication processes, such as Mach-Zehnder silicon photonic switches that utilize resistive heating elements, additional processing may be implemented before or after patterning the material for the one or more second optical components 503. For example, implantation processes, additional deposition and patterning processes for different materials, combinations of all of these processes, and the like may be utilized to further assist in fabricating various desired one or more second optical components 503. All such fabrication processes and all suitable one or more second optical components 503 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

[0039] Once the one or more second optical components 503 of the first metallization layer 501 have been fabricated, a first bonding layer 505 is formed over the first metallization layer 501. In an embodiment, the first bonding layer 505 may be used for dielectric-to-dielectric and metal-to-metal bonding. According to some embodiments, the first bonding layer 505 is formed of a first dielectric material 509 such as silicon oxide, silicon nitride, etc. The first dielectric material 509 may be deposited using any suitable method, such as CVD, high density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), etc. However, any suitable material and deposition process may be utilized.

[0040] Once the first dielectric material 509 has been formed, a first opening is formed in the first dielectric material 509 to expose the conductive portion of the underlying layer, in preparation for forming the first bonding pad 507 in the first bonding layer 505. Once the first opening has been formed in the first dielectric material 509, the first opening can be filled with a seed layer and a plated metal to form the first bonding pad 507 in the first dielectric material 509. The seed layer can be blanket deposited on the top surface of the first dielectric material 509 and the exposed conductive portion of the underlying layer and the sidewalls of the opening and the second opening. The seed layer can include a copper layer. The seed layer can be deposited using a process such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD), depending on the desired material. The plated metal can be deposited on the seed layer by a plating process such as electroplating or chemical plating. The plated metal can include copper, copper alloys, etc. The plated metal can be a filling material. Prior to the seed layer, a barrier layer (not shown separately) can be blanket deposited on the top surface of the first dielectric material 509 and the sidewalls of the opening and the second opening. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0041] After filling the first opening, a planarization process, such as CMP, is performed to remove the seed layer and excess portions of the plated metal, and form a first bonding pad 507 in the first bonding layer 505. In some embodiments, a bonding pad via (not separately shown) may also be used to connect the first bonding pad 507 to the underlying conductive portion, and to connect the first bonding pad 507 to the first metallization layer 501 through the underlying conductive portion.

[0042] In addition, the first bonding layer 505 may also include one or more third optical components 511 incorporated into the first bonding layer 505. In such an embodiment, the one or more third optical components 511 may be manufactured using similar methods and similar materials as the one or more second optical components 503 (described above), such as by waveguides and other structures formed at least in part by deposition and patterning processes, prior to depositing the first dielectric material 509. However, any suitable structures, materials, and any suitable manufacturing methods may be utilized.

[0043] Figure 6A first bonding layer 505 is shown bonding a first semiconductor device 601 to an optical interposer 100. In some embodiments, the first semiconductor device 601 is an electronic integrated circuit (EIC—e.g., a device without optical devices) and may have a semiconductor substrate 603, a layer of active devices 605, an interconnect structure 607 thereon, a second bonding layer 609, and associated third bonding pads 611. In an embodiment, the semiconductor substrate 603 may be similar to the first substrate 101 (e.g., a semiconductor material such as silicon or silicon germanium), the active devices 605 may be transistors, capacitors, resistors, etc. formed above the semiconductor substrate 603, the interconnect structure 607 may be similar to the first metallization layer 501 (without optical components), the second bonding layer 609 may be similar to the first bonding layer 505, and the third bonding pads 611 may be similar to the first bonding pads 507. However, any suitable device may be utilized.

[0044] In an embodiment, the first semiconductor device 601 may be configured to work with the optical interposer 100 for a desired function. In some embodiments, the first semiconductor device 601 may be a high bandwidth memory (HBM) module, an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, a combination of these, etc. Any suitable device having any suitable function may be used, and all such devices are fully intended to be included within the scope of the embodiments.

[0045] In an embodiment, the first semiconductor device 601 and the first bonding layer 505 can be bonded using dielectric to dielectric and metal to metal bonding processes. In a specific embodiment utilizing dielectric to dielectric and metal to metal bonding processes, the process can start by activating the surface of the second bonding layer 609 and the surface of the first bonding layer 505. As an example, activating the top surface of the first bonding layer 505 and the second bonding layer 609 may include dry processing, wet processing, plasma processing, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, their combination, etc. In an embodiment using wet processing, for example, RCA cleaning can be used. In another embodiment, the activation process may include other types of processing. The activation process helps the bonding of the first bonding layer 505 and the second bonding layer 609.

[0046] After the activation process, the optical interposer 100 and the first semiconductor device 601 may be cleaned using, for example, chemical cleaning, and then the first semiconductor device 601 is aligned with the optical interposer 100 and placed in physical contact with the optical interposer 100. The optical interposer 100 and the first semiconductor device 601 are then subjected to heat treatment and contact pressure to bond the optical interposer 100 and the first semiconductor device 601. For example, the optical interposer 100 and the first semiconductor device 601 may be subjected to a pressure of about 200 kPa or less and a temperature between about 25° C. and about 250° C. to fuse the optical interposer 100 and the first semiconductor device 601. The optical interposer 100 and the first semiconductor device 601 may then be subjected to a temperature at or above the eutectic point of the material for the first bonding pad 507 and the third bonding pad 611, for example, between about 150° C. and about 650° C. to fuse the metals. In this manner, the optical interposer 100 and the first semiconductor device 601 form a dielectric-to-dielectric and metal-to-metal bonded device. In some embodiments, the bonded dies are subsequently baked, annealed, pressed, or otherwise processed to strengthen or finalize the bond.

[0047] In addition, although specific processes have been described to initiate and strengthen bonding, these descriptions are intended to be illustrative and are not intended to limit the embodiments. Instead, any suitable combination of baking, annealing, pressing, or process combinations may be utilized. All such processes are fully intended to be included within the scope of the embodiments.

[0048] Figure 6 Additionally shown, once the first semiconductor device 601 has been bonded, a first gap fill material 613 is deposited to fill the space around the first semiconductor device 601 and provide additional support. In an embodiment, the first gap fill material 613 can be a material deposited to fill and overfill the space around the first semiconductor device 601, such as silicon oxide, silicon nitride, silicon oxynitride, combinations of these, etc. However, any suitable material and deposition method can be utilized.

[0049] Once the first gap-fill material 613 has been deposited, the first gap-fill material 613 may be planarized to expose the first semiconductor device 601. In an embodiment, the planarization process may be a chemical mechanical planarization process, a grinding process, etc. However, any suitable planarization process may be utilized.

[0050] Figure 7 The first support substrate 701 is shown attached to the first semiconductor device 601 and the first gap filling material 613. In an embodiment, the first support substrate 701 can be a support material transparent to the wavelength of light desired to be used, such as silicon, and can be bonded using, for example, an adhesive (in Figure 7However, in other embodiments, the first support substrate 701 may be bonded to the first semiconductor device 601 and the first gap filling material 613 using, for example, a bonding process. Any suitable method of attaching the first support substrate 701 may be used.

[0051] Figure 8 The first substrate 101 and (optionally) the first insulating layer 103 are shown removed, thereby exposing the first active layer 201 of the first optical component 203. In an embodiment, the first substrate 101 and the first insulating layer 103 may be removed using a planarization process, such as a chemical mechanical polishing process, a grinding process, one or more etching processes, combinations of these, etc. However, any suitable method may be used to remove the first substrate 101 and / or the first insulating layer 103.

[0052] Once the first substrate 101 and the first insulating layer 103 have been removed, the second active layer 801 of the fourth optical component 803 may be formed on the back side of the first active layer 201. In an embodiment, the second active layer 801 of the fourth optical component 803 may be formed using similar materials and similar processes as the second optical component 503 of the first metallization layer 501 (described above with respect to Figure 5 For example, the second active layer 801 of the fourth optical component 803 may be formed of alternating layers of a cladding material such as silicon oxide and a core material such as silicon nitride formed using deposition and patterning processes to form an optical component such as a waveguide.

[0053] Fig. 9 The formation of a first device through via (TDV) 901 and the formation of a third bonding layer 903 are shown to form a first optical package 900. In an embodiment, the first device through via 901 extends through the second active layer 801 and the first active layer 201 to provide a fast path for power, data, and ground through the optical interposer 100. In an embodiment, the first device through via 901 can be formed by initially forming a device through via opening in the optical interposer 100. The device through via opening can be formed by applying and developing a suitable photoresist (not shown) and removing exposed portions of the second active layer 801 and the optical interposer 100.

[0054] Once the device via opening has been formed in the optical interposer 100, the device via opening may be lined with a liner. The liner may be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes such as physical vapor deposition or thermal processes may also be used.

[0055] Once the liner has been formed along the sidewalls and bottom of the device via opening, a barrier layer (also not shown separately) can be formed, and the remainder of the device via opening can be filled with a first conductive material. The first conductive material can include copper, but other suitable materials can be utilized, such as aluminum, alloys, doped polysilicon, combinations thereof, etc. The first conductive material can be formed by electroplating copper on a seed layer (not shown), filling, and overfilling the device via opening. Once the device via opening has been filled, excess liner, barrier layer, seed layer, and first conductive material outside the device via opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can be used.

[0056] Optionally, in some embodiments, once the first device via 901 has been formed, a second metallization layer (at the top) electrically connected to the first device via 901 may be formed. Fig. 9 In an embodiment, the second metallization layer may be formed as described above with respect to the first metallization layer 501, such as alternating layers of dielectric material and conductive material using a damascene process, a dual damascene process, etc. In other embodiments, the second metallization layer may be formed using a plating process to form and shape the conductive material, and then cover the conductive material with a dielectric material. However, any suitable structure and manufacturing method may be utilized.

[0057] The third bonding layer 903 is formed to provide electrical connection between the optical interposer 100 and a subsequently attached device. In an embodiment, the third bonding layer 903 may be similar to the first bonding layer 505, such as having a third bonding pad 909 (similar to the first bonding pad 507) and even a fifth optical component 911 (similar to the third optical component 511). However, any suitable device may be utilized.

[0058] Fig. 9 The placement of the first external connector 913 is additionally shown, and the first external connector 913 can be formed to provide a conductive area for contact between the third bonding pad 909 and other external devices. The first external connector 913 can be a conductive bump (e.g., C4 bump, ball grid array, micro bump, etc.) or a conductive column using materials such as solder and copper. In an embodiment where the first external connector 913 is a contact bump, the first external connector 913 may include a material such as tin or other suitable materials such as silver, lead-free tin or copper. In an embodiment where the first external connector 913 is a tin solder bump, the first external connector 913 can be formed by initially forming a tin layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the tin layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape.

[0059] Fig.10As shown, once the first optical package 900 has been formed, the first optical package 900 can be attached to an interposer substrate 1001, which is used to couple the first optical package 900 with other devices to form, for example, a chip-on-wafer-on-substrate. In an embodiment, the interposer substrate 1001 includes a semiconductor substrate 1003, an optional third metallization layer ( Fig.10 ), a third device through hole (TDV) 1007 and a second external connection 1009. The semiconductor substrate 1003 may include bulk silicon (doped or undoped) or an active layer of a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate includes a semiconductor material layer such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0060] Optionally, a first active device (not separately shown) may be added to the semiconductor substrate 1003. The first active device includes a variety of active and passive devices, such as capacitors, resistors, inductors, etc., that may be used to generate the desired structural and functional requirements for the design of the semiconductor substrate 1003. The first active device may be formed in or on the semiconductor substrate 1003 using any suitable method.

[0061] The third metallization layer is formed over the semiconductor substrate 1003 and the first active device, and is designed to connect the various devices to form a functional circuit. In an embodiment, the third metallization layer is formed of alternating layers of dielectric materials (e.g., low-k dielectric materials, very low-k dielectric materials, ultra-low-k dielectric materials, combinations of these materials, etc.) and conductive materials, and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). However, any suitable material and process can be utilized.

[0062] In addition, if desired, the third metallization layer may also include an interposer optical component that may interact with the fifth optical component 911 of the first optical package 900. In an embodiment, the interposer optical component may be used as described above with respect to Figure 5 The third optical assembly 511 is formed by similar methods and materials as described above. However, any suitable methods and materials may be utilized.

[0063] In addition, at any desired point in the manufacturing process, a third TDV 1007 can be formed within one or more layers of the semiconductor substrate 1003 and (if desired) the third metallization layer to provide an electrical connection from the front side of the semiconductor substrate 1003 to the back side of the semiconductor substrate 1003. In an embodiment, the third TDV 1007 can be formed by initially forming a through device via (TDV) opening in the semiconductor substrate 1003 and (if desired) any upper third metallization layer (e.g., after the desired third metallization layer has been formed but before the next upper third metallization layer is formed). The TDV opening can be formed by applying and developing a suitable photoresist and removing portions of the underlying material exposed to a desired depth. The TDV opening can be formed to extend into the semiconductor substrate 1003 to a depth greater than the final desired height of the semiconductor substrate 1003.

[0064] Once the TDV opening has been formed in the semiconductor substrate 1003 and / or any third metallization layer, the TDV opening may be lined with a liner. The liner may be an oxide formed, for example, from tetraethyl orthosilicate (TEOS) or silicon nitride, but any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, but other suitable processes may be used, such as physical vapor deposition or thermal processes.

[0065] Once the liner has been formed along the sidewalls and bottom of the TDV opening, a barrier layer can be formed and the remainder of the TDV opening can be filled with a first conductive material. The first conductive material can include copper, but other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, etc. can be utilized. The first conductive material can be formed by electroplating copper on a seed layer, filling and overfilling the TDV opening. Once the TDV opening has been filled, excess liner, barrier layer, seed layer, and first conductive material outside the TDV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can be used.

[0066] Once the TDV opening has been filled, the semiconductor substrate 1003 may be thinned until the third TDV 1007 has been exposed. In an embodiment, the semiconductor substrate 1003 may be thinned using, for example, a chemical mechanical polishing process, a grinding process, etc. Further, once exposed, the semiconductor substrate 1003 may be recessed using, for example, one or more etching processes (such as a wet etching process) to recess the semiconductor substrate 1003 such that the third TDV 1007 extends out of the semiconductor substrate 1003.

[0067] In an embodiment, the second external connector 1009 may be placed on the semiconductor substrate 1003 and electrically connected to the third TDV 1007, and may be, for example, a ball grid array (BGA) including a eutectic material such as solder, but any suitable material may be used. Optionally, an under-bump metallization (UBM) or additional metallization layer ( Fig.10 In an embodiment where the second external connector 1009 is a solder bump, the second external connector 1009 can be formed using a ball drop method, such as a direct ball drop process. In another embodiment, the solder bump can be formed by initially forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow to shape the material into the desired bump shape. Once the second external connector 1009 has been formed, testing can be performed to ensure that the structure is suitable for further processing.

[0068] Once the interposer substrate 1001 has been formed, the first optical package 900 can be attached to the interposer substrate 1001. In an embodiment, the first optical package 900 can be attached to the interposer substrate 1001 by aligning the first external connector 913 with the conductive portion of the interposer substrate 1001. Once aligned and in physical contact, the first external connector 913 is reflowed by increasing the temperature of the first external connector 913 above the eutectic point of the first external connector 913, thereby transforming the material of the first external connector 913 into a liquid phase. Once reflowed, the temperature is reduced to transform the material of the first external connector 913 back into a solid phase, thereby bonding the first optical package 900 to the interposer substrate 1001.

[0069] Fig.10 The second semiconductor device 1011 and the third semiconductor device 1013 are additionally shown to be bonded to the semiconductor substrate 1003. In some embodiments, the second semiconductor device 1011 is an electronic integrated circuit (EIC), such as a stacked device including multiple, interconnected semiconductor substrates. For example, the second semiconductor device 1011 can be a memory device including multiple stacked memory dies, such as a high bandwidth memory (HBM) module, a hybrid memory multidimensional cube (HMC) module, etc. In such an embodiment, the second semiconductor device 1011 includes multiple semiconductor substrates interconnected by device through vias (TDVs). Each of the semiconductor substrates may (or may not) have an active device layer and an interconnect structure, a bonding layer, and associated bonding pads thereon to interconnect multiple devices within the second semiconductor device 1011.

[0070] Of course, although the second semiconductor device 1011 is an HBM module in one embodiment, the embodiments are not limited to the second semiconductor device 1011 being an HBM module. Instead, the second semiconductor device 1011 may be any suitable semiconductor device, such as a processor die or other types of functional dies. In a particular embodiment, the second semiconductor device 1011 may be an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, a combination of these, and the like. Any suitable device having any suitable function may be used, and all such devices are fully intended to be included within the scope of the embodiments.

[0071] The third semiconductor device 1013 may be another EIC intended to work with the first optical package 900 and the second semiconductor device 1011. In some embodiments, the third semiconductor device 1013 may have a different functionality from the second semiconductor device 1011, such as by being an xPU, GPU, ASIC device, or may have the same functionality as the second semiconductor device 1011, such as by being another high bandwidth memory device.

[0072] In an embodiment, the second semiconductor device 1011 and the third semiconductor device 1013 can be bonded to the interposer substrate 1001 using, for example, a third external connection 1015. The third external connection 1015 can be a conductive bump (e.g., a ball grid array, a microbump, etc.) or a conductive column using a material such as solder and copper. In an embodiment where the third external connection 1015 is a contact bump, the third external connection 1015 can include a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the third external connection 1015 is a tin solder bump, the third external connection 1015 can be formed by initially forming a tin layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the tin layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape.

[0073] Furthermore, once the third external connection 1015 has been placed, the second semiconductor device 1011 and the third semiconductor device 1013 are aligned with the interposer substrate 1001. Once aligned and in physical contact, the third external connection 1015 is reflowed by increasing the temperature of the third external connection 1015 above the eutectic point of the third external connection 1015, thereby transforming the material of the third external connection 1015 into a liquid phase. Once reflowed, the temperature is reduced to transform the material of the third external connection 1015 back into a solid phase, thereby bonding the second semiconductor device 1011 and the third semiconductor device 1013 to the interposer substrate 1001.

[0074] Optionally, an underfill material (not shown separately) may be placed. The underfill material may reduce stress and protect joints created by reflow of the third external connection 1015 and the first external connection 913. The underfill material may be formed by a capillary flow process after attaching the first optical package 900, the second semiconductor device 1011, and the third semiconductor device 1013.

[0075] Once the second semiconductor device 1011, the third semiconductor device 1013, and the first optical package 900 have been bonded to the interposer substrate 1001, the interposer substrate 1001 can be bonded to the second substrate 1021 with, for example, the second external connector 1009. In an embodiment, the second substrate 1021 can be a packaging substrate, which can be a printed circuit board (PCB), etc. The second substrate 1021 may include one or more dielectric layers and conductive components, such as wires and vias. In some embodiments, the second substrate 1021 may include vias, active devices, passive devices, etc. The second substrate 1021 may also include conductive pads formed at the upper and lower surfaces of the second substrate 1021.

[0076] The second external connectors 1009 may be aligned with corresponding conductive connections on the second substrate 1021. Once aligned, the second external connectors 1009 may then be reflowed to bond the second substrate 1021 to the interposer substrate 1001. However, any suitable bonding process may be used to connect the interposer substrate 1001 to the second substrate 1021.

[0077] In addition, the second substrate 1021 can be prepared for further connection by placing a fourth external connection (not shown separately) on the side of the second substrate 1021 opposite the first optical package 900. In an embodiment, the fourth external connection can be formed using a process and materials similar to the second external connection 1009. However, any suitable materials and processes can be utilized.

[0078] FIG. 11A to FIG. 16B The formation of a multi-level connection unit 1600 (eg, a fan-in fiber array unit) for use with the first optical package 900 is shown. Fig.11A , Fig.11A A first level substrate 1101, a first lens 1103 formed within the first level substrate 1101, a first level active layer 1105 having a sixth optical component 1107, and a first reflector 1109 bonded to a first carrier substrate 1111 are shown. In an embodiment, the first level substrate 1101 may be similar to that described above with respect to Figure 1 The first substrate 101 is described as being, for example, a silicon substrate, however, any suitable material may be utilized.

[0079] The first lens 1103 is formed within the first level substrate 1101. In an embodiment, the first lens 1103 may be formed by shaping the material (eg, silicon) of the support substrate using a masking and etching process. However, any suitable process may be utilized.

[0080] Additionally, if desired, a first anti-reflective coating (ARC) 1113 can be formed on the first lens 1103. In embodiments, the first ARC 1113 can be one or more material layers that help prevent unwanted reflections when light is focused through the first lens 1103. In certain embodiments, the one or more material layers can be a material such as silicon oxide, silicon nitride, combinations of these, etc., formed using a process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, oxidation, nitridation, combinations of these, etc.

[0081] In a particular embodiment, the first ARC 1113 can be formed using a first silicon oxide layer and a first silicon nitride layer formed above the first silicon oxide layer. A second silicon oxide layer and a second silicon nitride layer are deposited over the first silicon oxide layer and the first silicon nitride layer to form an alternating stack of silicon oxide and silicon nitride. Once all desired layers have been deposited, the layers can be patterned using, for example, photolithographic masking and etching processes. However, any suitable combination of materials and processes can be utilized.

[0082] Additionally, if the recess formed by the first lens 1103 is not otherwise filled, a fill material may be deposited to fill the recess formed by the first lens 1103. In embodiments, the fill material may be a cladding material such as silicon oxide deposited using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations of these, etc. Once the recess has been filled, the fill material may be planarized using a process such as chemical mechanical polishing to remove portions of the fill material that are outside the recess.

[0083] Once the first lens 1103 has been formed, a first level active layer 1105 having a sixth optical component 1107 is formed over the first level substrate 1101. In an embodiment, the first level active layer 1105 having the sixth optical component 1107 may be formed using the same method as described above with respect to Figure 8 The fourth optical component 803 is formed by similar materials and processes as the second active layer 801 described above. However, any suitable materials and processes may be utilized.

[0084] In certain embodiments, the sixth optical component 1107 includes at least one integrated multicoupler (IMC) (eg, an edge coupler), such as one positioned to receive an optical signal (described below with respect to Fig.191 and 10. Further described) and a multi-waveguide edge coupler interacting with the waveguides within the first optical package 900. However, any suitable optical assembly may be formed.

[0085] Once the first level active layer 1105 having the sixth optical component 1107 has been formed, a first reflector 1109 may be formed to extend into the first level active layer 1105 and have a first orientation. In an embodiment, the first reflector 1109 may be formed by initially patterning the first level active layer 1105 to form a groove. In an embodiment, the groove may be formed using one or more photolithography masking and etching processes, such as one or more wet etching processes or dry etching processes. However, any suitable process may be utilized.

[0086] Once the groove has been formed, a first reflector 1109 may be formed along the sidewalls of the groove. In embodiments, the first reflector 1109 may be a single layer of reflective material, such as aluminum copper, copper, gold, aluminum, titanium nitride, combinations of these, or the like, or may be a multilayer structure, such as a Bragg reflector including alternating layers of different materials, such as alternating layers of silicon dioxide and amorphous silicon. The separate material of the first reflector 1109 may be deposited using any suitable method, such as chemical vapor deposition, physical vapor deposition, plating, combinations of these, or the like, and the separate layer may then be further patterned (e.g., to remove horizontal portions of the deposited material) using, for example, photolithographic masking and etching processes. However, any suitable material and method may be utilized to form the first reflector 1109 along the sidewalls of the groove.

[0087] In addition, if the formation of the first reflector 1109 does not completely fill the groove, the groove can be filled and planarized. In an embodiment, the groove can be filled and / or overfilled with a material similar to the cladding material of the first level active layer 1105 deposited using a method such as chemical vapor deposition, followed by a planarization process such as a chemical mechanical polishing process. However, any suitable material and any suitable process can be utilized.

[0088] Once the first reflector 1109 has been formed, the first level active layer 1105 may be bonded to a first carrier substrate 1111. In an embodiment, the first carrier substrate 1111 may include a material such as glass, silicon, silicon germanium, combinations of these, and the first carrier substrate 1111 may be bonded to the first level active layer 1105 using, for example, a dielectric to dielectric bonding process. However, any suitable material and any suitable bonding process may be utilized.

[0089] Fig. 11BA top view of the first level active layer 1105 with the sixth optical component 1107 and the first reflector 1109 is shown. In an embodiment, each of the sixth optical components 1107 (e.g., waveguides) within the first level active layer 1105 is aligned so that the transmitted and received optical signals will be reflected by the first reflector 1109. However, because of the optical signals from the above structures (e.g., the second reflector 1207, as described below) FIG. 12A to FIG. 12B Further discussed) will pass through the first level active layer 1105, so the first reflector 1109 can be shaped and formed to allow the optical signal to pass through the channel of the first reflector 1109. Therefore, the first reflector 1109 may not be formed as a single unit, but rather have multiple segments, each of which is aligned to reflect one or more but not all of the optical signals from the sixth optical component 1107, while still allowing optical signals reflected from, for example, the second reflector 1207 to pass through the first reflector 1109.

[0090] Fig. 12A The second lens 1201 is shown formed on the side of the first level substrate 1101 opposite to the first lens 1103. In an embodiment, the second lens 1201 may be formed using the same Fig.11A The second ARC 1209 may be formed using a similar process as the first lens 1103 described above, and if desired, the second ARC 1209 may be formed using a similar process as the first ARC 1113. However, any suitable process may be utilized.

[0091] A second level active layer 1203 having a seventh optical component 1205 may be formed above the second lens 1201. In an embodiment, the second level active layer 1203 and the seventh optical component 1205 may be formed using the same method as described above with respect to Fig.11A The first level active layer 1105 with the sixth optical component 1107 is formed using similar materials and methods as described.

[0092] Fig. 12A The formation of a second reflector 1207 having a second orientation different from the first orientation is additionally shown. In an embodiment, the second reflector 1207 may be formed using the same method as described above with respect to Fig.11A The first reflector 1109 is formed using similar processes and materials as described above. However, any suitable processes and materials may be utilized.

[0093] Fig. 12B A top view of the second level active layer 1203 with the seventh optical component 1205 and the second reflector 1207 is shown, wherein the seventh optical component 1205 is shown as having a fan-in design. Fig. 12B As can be seen in FIG. 1 , the second reflector 1207 is designed to receive signals from the first reflector 1109 and the third reflector 1611 ( Fig. 12BNot shown, but the following FIG. 16A to FIG. 16B 1206 and 1207. The second reflector 1207 is further shown and described in detail, and reflects the light signal into the seventh optical component 1205. Therefore, the second reflector 1207 can be formed and shaped as a single unit (such as Fig. 12B ), or may be formed and shaped to have multiple, separate segments (similar to the above with respect to Fig. 11B The first reflector 1109 shown in FIG. 1 ) may be of any suitable shape.

[0094] Fig.13 The bonding of the second level active layer 1203 to the second level substrate 1301 is shown. In an embodiment, the second level substrate 1301 can be similar to the first level substrate 1101, such as by being a silicon substrate, and can be bonded using, for example, a dielectric to dielectric bonding process. However, any suitable material and any suitable bonding process can be utilized.

[0095] Additionally, if desired, at this point in the manufacturing process, the second level active layer 1203 can be thinned (after bonding). In certain embodiments, the second level active layer 1203 can be thinned using a planarization process, such as a chemical mechanical polishing process. However, any suitable planarization process can be utilized, such as a grinding process or one or more etching processes.

[0096] Fig.14 It is shown that once the second level substrate 1301 has been bonded to the second level active layer 1203, the first carrier substrate 1111 can be stripped and removed to expose the first level active layer 1105. In an embodiment, the second level substrate 1301 can be removed using any suitable method, such as one or more planarization processes (e.g., chemical mechanical polishing processes) or one or more etching processes. However, any suitable stripping process can be utilized.

[0097] Fig.15 Segmentation of the first level substrate 1101 and the second level substrate 1301 is shown. In an embodiment, segmentation may be implemented using a saw to physically cut the structure. In other embodiments, the structure may be segmented using one or more masking and etching processes or a combination of sawing and etching processes. Any suitable method or combination of methods may be used.

[0098] Fig.16A The first level active layer 1105 is shown joined to the third level substrate 1601, wherein the third lens 1603 and the fourth lens 1605 are located on opposite sides of the third level substrate 1601. First, the third level substrate 1601 can be similar to the above Fig.11AThe first level substrate 1101 is described as being, for example, a silicon substrate, however, any suitable material may be used.

[0099] The third lens 1603 and the fourth lens 1605 may be formed on opposite sides of the third level substrate 1601. In an embodiment, the third lens 1603 and the fourth lens 1605 may be formed using similar methods as the first lens 1103, such as using one or more photolithography masking and etching processes to shape the surface of the third level substrate 1601, and if desired, the third ARC 1613 and the fourth ARC 1615 may be formed using similar processes and materials as the first ARC 1113. However, any suitable method may be utilized.

[0100] After the third lens 1603 and the fourth lens 1605 have been formed, the third level active layer 1607 having the eighth optical component 1609 may be formed. In an embodiment, the third level active layer 1607 having the eighth optical component 1609 may be used in conjunction with the first level active layer 1105 having the sixth optical component 1107 (described above with respect to FIG. Fig.11A However, any suitable method and material may be used.

[0101] Fig.16A The formation of a third reflector 1611 having a third orientation is additionally shown, the third orientation being the same as the first orientation within the third level active layer 1607. In an embodiment, the third reflector 1611 may be formed using the same method as described above with respect to Fig.11A The first reflector 1109 is formed using similar processes and materials as described above. However, any suitable processes and materials may be utilized.

[0102] Once the third reflector 1611 has been formed, the first level active layer 1105 may be bonded to the third level substrate 1601 to form the multi-level connection unit 1600. In an embodiment, the first level active layer 1105 may be bonded to the third level substrate 1601 using, for example, a dielectric to dielectric bonding process. However, any suitable bonding process may be utilized.

[0103] Fig. 16B A top view of the third level active layer 1607 with an eighth optical component 1609 and a third reflector 1611 is shown. In an embodiment, as in Fig. 16B As can be seen in FIG. 1 , the third reflector 1611 is designed to receive the optical signal from the eighth optical component 1609 and reflect the optical signal toward the fourth lens 1605. Therefore, the third reflector 1611 can be formed and shaped as a single unit, or can be formed and shaped to have multiple, separate segments. Any suitable shape can be utilized.

[0104] Fig.17 The multi-level connection unit 1600 is shown attached to the second substrate 1021 and the first optical package 900. In an embodiment, the multi-level connection unit 1600 may be attached to the first optical package 900 using, for example, an optical glue 1701. In some embodiments, the optical glue 1701 includes a polymer material, such as an epoxy acrylate oligomer, and may have a refractive index between about 1 and about 3. However, any suitable material may be utilized.

[0105] In addition, the multi-level connection unit 1600 can be attached to the second substrate 1021 to provide auxiliary support and help avoid warping of the second substrate 1021. In an embodiment, the multi-level connection unit 1600 can be attached to the second substrate 1021 using a first gasket 1703, which can be a rubber material, a soft and supportive polymer material, a combination of these, etc. However, any suitable material can be utilized.

[0106] Fig.18A The optical fiber 1803 is shown connected from the sleeve 1805 to the multi-level connection unit 1600 using multiple rows of connectors 1801. In an embodiment, each of the optical fibers 1803 may include a core material, such as glass, surrounded by one or more coating materials. Optionally, a surrounding covering material may be used to surround the outer coating material to provide additional protection.

[0107] In a particular embodiment, the core material may have a thickness of approximately 10 μm. Additionally, the cladding material has a thickness of approximately 125 μm along one side of the core material. However, any suitable dimensions may be utilized.

[0108] In an embodiment, the sleeve 1805 can be used to receive a plurality of optical fibers 1803 (from outside the figure), align the optical fibers 1803, and connect the optical fibers 1803 to the multi-row connector 1801. In an embodiment, the sleeve 1805 can be a mechanical transfer (MT) sleeve made of a material that can be used to protect, support and align the independent optical fibers 1803. However, any suitable material can be used. In an embodiment, the optical fiber 1803 can be inserted into an opening located in the sleeve 1805. Once a glue material is inserted, such as epoxy resin, silicone resin, photocurable elastic polymer, a combination of these, etc., can be injected or otherwise placed into the opening in the sleeve 1805 to fix the optical fiber 1803 in the sleeve 1805. In addition, a curing process such as light curing, heat curing, etc. can be used to harden the glue material. In this embodiment, the sleeve 1805 helps fix the optical fiber 1803 so that the optical signal provided by the optical fiber 1803 can be sent to the multi-level connection unit 1600.

[0109] The multi-row connector 1801 receives the optical fibers 1803 from the ferrule 1805 and separates them into more than one row. Fig.18A In the particular embodiment shown in FIG. 1 , the more than one row includes two rows of optical fibers 1803, such as a first row 1811 and a second row 1813. However, any suitable number of rows may be utilized, such as three or four rows.

[0110] In an embodiment, once the multi-row connector 1801 is attached to the multi-level connector unit 1600, each of the individual rows of optical fibers 1803 is aligned with a corresponding level within the multi-row connector 1801. In a specific embodiment utilizing two rows, the first row 1811 is aligned such that the optical signal from the first row enters the eighth optical component 1609 of the third level active layer 1607. In addition, the second row 1813 is aligned such that the optical signal from the second row enters the sixth optical component 1107 of the first level active layer 1105. In a specific embodiment, the first row 1811 can be separated from the second row 1813 by a first pitch P1 between about 250 μm and about 500 μm. However, any suitable distance can be utilized.

[0111] Once the multiple rows of connectors 1801 are prepared, the multiple rows of connectors 1801 are connected to the multi-level connector unit 1600 and the second substrate 1021. In an embodiment, the multiple rows of connectors 1801 can be attached to the multi-level connector unit 1600 using, for example, a second optical glue 1807 and a sidewall anti-reflection coating 1806. In some embodiments, the second optical glue 1807 and the sidewall anti-reflection coating 1806 can be used as described above. Fig.17 and Fig.11A The optical adhesive 1701 and the first ARC 1113 are formed using similar materials and methods as described.

[0112] Additionally, multiple rows of connectors 1801 may be attached to the second substrate 1021 to provide additional support and help prevent warping of the second substrate 1021. In an embodiment, multiple rows of connectors 1801 may be attached to the second substrate 1021 using a second gasket 1809, which may be a rubber material, a soft and supportive polymer material, a combination of these, etc. However, any suitable material may be utilized.

[0113] Fig.18B 1703 and the second gasket 1809 are shown in a top view. In an embodiment, the first gasket 1703 is located below the multi-level connection unit 1600 (at Fig.18B 1801 is indicated by being located on the left side of the dashed line), and the second gasket 1809 is located below the multiple rows of connectors 1801 (in Fig.18B is indicated by being located on the upper right side of the dashed line).

[0114] Fig.19 shows the operation of the optical signal (in Fig.191801), wherein the optical signal enters from the sleeve 1805 and then enters the multi-row connector 1801, wherein the optical signal is divided into a first row 1811 and a second row 1813 within the multi-row connector 1801. The optical signal from the second row 1813 enters the sixth optical component 1107 in the first-level active layer 1105, is reflected by the first reflector 1109 toward the second reflector, and is reflected by the second reflector 1207 to enter the seventh optical component 1205 of the second-level active layer 1203. From the seventh optical component 1205, the optical signal can be routed to the first optical package 900 through, for example, an edge coupler located in the seventh optical component 1205 and the second active layer 801 of the fourth optical component 803.

[0115] In addition, the optical signal from the first row 1811 enters the eighth optical component 1609 in the third level active layer 1607, is reflected by the third reflector 1611, passes between the individual elements of the first reflector 1109, and is reflected by the second reflector 1207 before entering the seventh optical component 1205 of the second level active layer 1203. From the seventh optical component 1205, the optical signal can be routed into the first optical package 900 through, for example, an edge coupler located within the seventh optical component 1205 and the second active layer 801 of the fourth optical component 803.

[0116] By utilizing multiple rows of connectors 1801, more optical fibers 1803 can be connected to the first optical package 900. In particular, the third level active layer 1607 can be used to ensure compatibility with the multiple rows of connectors 1801, the first level active layer 1105 is used to provide a height aligned with each row of the multiple rows of connectors 1801 without cutting the substrate, and the second level active layer 1203 is used to help ensure that the seventh optical component 1205 is accurately aligned with the coupler of the first optical package 900.

[0117] Furthermore, by increasing the number of optical fibers 1803, this allows a higher bandwidth to enter and leave the first optical package 900. Therefore, coupling losses from the optical fibers 1803 to the first optical package 900 can be reduced and a more efficient device can be formed.

[0118] Fig. 20A Another embodiment is shown in which the sixth optical component 1107 and the eighth optical component 1609 are not formed. Looking first at the removal of the eighth optical component 1609, the eighth optical component 1609, the third level active layer 1607 and the fourth lens 1605 are not formed during the manufacturing process as described above. Instead, the third reflector 1611 uses, for example, the same method as described above with respect to Fig.16ASimilar processes as described are formed directly into the third level substrate 1601, such as patterning openings, lining the openings with reflective material, and removing undesirable portions of the reflective material.

[0119] Furthermore, during the formation of the first optical package 900, the sixth optical component 1107 may also be removed and not fabricated, but dielectric material and / or cladding material may still be fabricated to facilitate bonding. Thus, the first reflector 1109 may be fabricated using, for example, the same techniques as described above with respect to Fig.11A Similar processes as described are formed within the first level substrate 1101, such as patterning openings, lining the openings with reflective material, and removing undesirable portions of the reflective material.

[0120] In addition, in this embodiment, the first reflector 1109 may not be located directly below the third reflector 1611, and the position of the first reflector 1109 may be offset relative to the position of the third reflector 1611. Therefore, the third lens 1603 and the first lens 1103 may be further offset relative to the position of the first reflector 1109 so as to be used to transmit the optical signal from the third reflector 1611.

[0121] Focusing on the second-level active layer 1203, in this embodiment, the second lens 1201 and the second reflector 1207 may be retained as discussed above to be able to reflect the optical signal received from the first reflector 1109. In this embodiment, however, the second-level active layer 1203 may additionally include a fifth lens 2001 and a fourth reflector 2003. In an embodiment, the fifth lens 2001 and the fourth reflector 2003 are used to receive the reflected optical signal from the third reflector 1611 and reflect the optical signal into the seventh optical component 1205 of the second-level active layer 1203, and the fifth lens 2001 and the fourth reflector 2003 may be used in the same manner as described above with respect to Fig.11A The first lens 1103 and first reflector 1109 are formed using similar methods and materials as described, and if desired, the fifth ARC 2005 can be formed with the fifth lens 2001 using similar methods and materials as the first ARC 1113. However, any suitable materials and methods may be utilized.

[0122] Fig. 20B A top view of the second level active layer 1203 in this embodiment is shown. As can be seen in this embodiment, the second level active layer 1203 includes a second reflector 1207 (which can be a single continuous structure) and a fourth reflector 2003 (which can include multiple, separate structures). Therefore, the seventh optical component 1205 (e.g., a waveguide) that receives the optical signal from the second reflector 1207 can pass between separate sections of the fourth reflector 2003 to form a fan-in design and avoid interference between independent components.

[0123] Back to Fig. 20A In operation, optical signals enter from sleeve 1805 and then enter multi-row connector 1801, where they are divided into first row 1811 and second row 1813 within multi-row connector 1801. Optical signals from second row 1813 enter first level substrate 1101, are reflected by first reflector 1109, and are reflected by second reflector 1207 before entering seventh optical component 1205 of second level active layer 1203. From seventh optical component 1205, optical signals are routed between elements of fourth reflector 2003 (see Fig. 20B ) and enters the first optical package 900.

[0124] In addition, the optical signal from the first row 1811 enters the third level substrate 1601 and is reflected by the third reflector 1611. From the reflection from the third reflector 1611, the optical signal is reflected by the fourth reflector 2003 into the seventh optical component 1205 of the second level active layer 1203. From the seventh optical component 1205, the optical signal is then routed into the first optical package 900.

[0125] Fig.21 shows a similar Fig.19 Another embodiment of the embodiment discussed. In this embodiment, however, the multi-level connection unit 1600 has a constant width from the top of the multi-level connection unit 1600 to the bottom of the multi-level connection unit 1600. Therefore, the multi-level connection unit 1600 may not extend above the first optical package 900, and the first optical package 900 may have a height coplanar with the second semiconductor device 1011 and the third semiconductor device 1013.

[0126] Fig. 22 Shows something like Fig.21 Another embodiment of the embodiment of the present invention (e.g., wherein the multi-level connection unit 1600 has a constant width), but wherein the multi-level connection unit 1600 is bonded to the interposer substrate 1001 instead of the second substrate 1021. In this embodiment, the multi-level connection unit 1600 can be bonded to the interposer substrate 1001 using a dielectric-to-dielectric bond instead of the first pad 1703. The bonding process can be as described above with respect to Figure 7 100 is implemented as described, but any suitable bonding process may be used. In this embodiment, a similar bonding process may be used to bond the first optical package 900, the second semiconductor device 1011 (if present and Fig. 22 (not shown separately) and the third semiconductor device 1013. Such bonding allows easy integration with, for example, a subsequently attached cover (not shown separately) for heat dissipation.

[0127] Furthermore, in this embodiment, although the multi-level connection unit 1600 may be optically connected to the first optical package 900 as described above (e.g., directly from the multi-level connection unit 1600 to the first optical package 900), in other embodiments, the multi-level connection unit 1600 may be optically connected to the first optical package 900 through, for example, an interposer optical component 2201 (described above with respect to FIG. Fig. 9 described, but in Fig. 22 ) is indirectly connected to the first optical package 900. Therefore, the optical signal will propagate from the seventh optical component 1205, through the interposer optical component 2201 and to the fifth optical component 911 to enter the first optical package 900.

[0128] Fig.23 1 shows a starting process for manufacturing another embodiment, in which the first level active layer 1105 (previously described as part of the multi-level connection unit 1600) is directly merged with the first optical package 900. In this embodiment, the process can be as described above with respect to Fig.11A Starting as described, where a first level active layer 1105 with a sixth optical component 1107 and a first reflector 1109 is fabricated on a first level substrate 1101 (without a first lens 1103) and then bonded to a first carrier substrate 1111 (using, for example, a bonding film). However, any suitable structure may be utilized.

[0129] Fig.24 It is shown that once the first carrier substrate 1111 has been bonded to the first level active layer 1105, the first level substrate 1101 may be thinned. In an embodiment, the first level substrate 1101 may be thinned using one or more planarization processes, such as a chemical mechanical planarization process. However, any suitable method may be utilized.

[0130] After the first level substrate 1101 has been thinned, a first bonding layer 2401 is deposited on the first level substrate 1101. In an embodiment, the first bonding layer 2401 may be a bonding material such as silicon oxide, silicon nitride, combinations of these, etc., deposited using a method such as a chemical mechanical polishing process. However, any suitable method and material may be utilized.

[0131] Fig.25 As shown, once the first level substrate 1101 has been thinned, the first level substrate 1101 can be bonded to Figure 7 structure (rather than the first supporting substrate 701, such as Figure 7 For example, in some embodiments, the first semiconductor device 601 is bonded and thinned, and the first gap fill material 613 is deposited and planarized, as described above with respect to Figure 7However, any suitable process may be utilized.

[0132] Once the gap fill material 613 has been deposited, a second bonding layer 2501 is deposited over the first semiconductor device 601 and the first gap fill material 613. In an embodiment, the second bonding layer 2501 may be similar to the first bonding layer 2401, such as by being silicon oxide deposited by chemical vapor deposition. However, any suitable methods and materials may be utilized.

[0133] Once the first bonding layer 2401 and the second bonding layer 2501 have been formed, the first bonding layer 2401 is bonded to the second bonding layer 2501. In an embodiment, the first bonding layer 2401 and the second bonding layer 2501 may be bonded using a dielectric to dielectric bonding process. However, any suitable bonding process may be utilized.

[0134] Fig.26 It is shown that once the first bonding layer 2401 and the second bonding layer 2501 have been bonded, the first substrate 101 is removed. In an embodiment, the first substrate 101 can be removed using a planarization process, such as a chemical mechanical polishing process, a grinding process, one or more etching processes, a combination of these, etc. However, any suitable method can be used to remove the first substrate 101.

[0135] Once the first substrate 101 has been removed, the second active layer 801 of the fourth optical component 803 is fabricated along the back side of the first active layer 201. In an embodiment, the second active layer 801 of the fourth optical component 803 may be fabricated as described above with respect to Figure 8 However, any suitable method may be used.

[0136] In this embodiment, however, in addition to forming the fourth optical component 803 in the second active layer 801, a fifth reflector 2701 is additionally formed in the second active layer 801. In an embodiment, the fifth reflector 2701 can be formed in a similar manner and using the same method as described above with respect to Fig.11A The first reflector 1109 is formed of a similar material as described above. However, any suitable method and material may be utilized.

[0137] Fig. 27 Additionally shown, once the second active layer 801 with the fourth optical component and the fifth reflector 2701 has been fabricated, the first device via 901 and the third bonding layer 903 may be fabricated. Furthermore, the first external connector 913 may be formed to form the second optical package 2700. Any suitable structure may be utilized.

[0138] Fig.28A1. As shown, once the second optical package 2700 has been prepared as described above, the second optical package 2700 can be bonded to the interposer substrate 1001 (where, for clarity, the second optical package 2700 is shown) along with the rows of connectors 1801. Fig.28A In an embodiment, the second optical package 2700 may be as described above with respect to Fig.10 As described above, the multiple rows of connectors 1801 can be connected as described above Fig.18A The bonding may be performed as described (eg, where a second shim 1809 is used). However, any suitable bonding process may be utilized.

[0139] In this embodiment, multiple rows of connectors 1801 can be used to space the first row 1811 from the second row 1813 to align the first row 1811 and the second row 1813 with a desired portion of the second optical package 2700. In a particular embodiment, the first row 1811 and the second row 1813 can have a second pitch P2 between about 127 μm and about 250 μm. However, any suitable pitch can be utilized.

[0140] In operation, the optical signals from the second row 1813 are directed directly into the second active layer 801 having the fourth optical component 803. However, the optical signals from the first row 1811 above are directed into the sixth optical component 1107 of the first level active layer 1105, reflected off the first reflector 1109 by the first gap filling material 613 and reflected into the fifth reflector 2701. The fifth reflector 2701 receives the optical signals and reflects them into the fourth optical component 803 of the second active layer 801.

[0141] Fig.28B A top view of the first level active layer 1105 is shown. As can be seen in this embodiment, the first reflector 1109 can be formed in a plurality of discrete segments, wherein each segment is aligned with a separate one of the sixth optical components 1107 of the first level active layer 1105. In this embodiment, the separate segments can be offset relative to each other, but in other embodiments, the separate segments can all be located in a single line. However, any suitable configuration can be utilized.

[0142] Fig.28CA top view of a second active layer 801 with a fourth optical component 803 and a fifth reflector 2701 is shown. As can be seen in this embodiment, the fifth reflector 2701 can be arranged in a similar manner to the first reflector 1109 (e.g., with independent segments offset relative to each other). In addition, the fourth optical component 803 within the second active layer 801 can implement multiple functions, such as directly receiving optical signals from the second optical fiber 1813 and routing the optical signals around the fifth reflector 2701 (only one of which is shown for clarity), and also receiving signals that have been reflected from the fifth reflector 2701 (again, only one of which is shown for clarity). However, any suitable fourth optical component 803 with any desired routing can be utilized.

[0143] Fig.28D A view of optical fibers 1803 in a first row 1811 and a second row 1813 is shown. In this embodiment, the individual optical fibers 1803 are arranged in an array-type layout, where the optical fibers 1803 in the first row 1811 are arranged directly above corresponding optical fibers 1803 in the second row 1813. However, any suitable arrangement may be utilized.

[0144] FIG. 29A to FIG. 29C Yet another embodiment is shown, in which optical fibers 1803 are arranged in a staggered configuration by multiple rows of connectors 1801. In this embodiment, the individual optical fibers 1803 are not separated from each other, but are arranged adjacent to each other. Thus, the optical fibers 1803 in the first row and the optical fibers in the second row can have a third pitch P3 between about 127 μm and about 250 μm, such as about 108 μm. In addition, the center of each of the optical fibers 1803 can be offset relative to the center of the optical fibers 1803 in the adjacent rows.

[0145] Fig.29B A top view of a portion of the first level active layer 1105 and a portion of the second active layer 801 is shown. As can be seen in this embodiment, the first reflector 1109 can be formed in a plurality of discrete segments, wherein each segment is aligned with a separate one of the sixth optical components 1107 of the first level active layer 1105. In addition, some of the fourth optical components 803 of the second active layer 801 can be interspersed below and between the separate sixth optical components 1107. However, any suitable configuration may be utilized.

[0146] Fig.29CA view of optical fibers 1803 in a first row 1811 and a second row 1813 is shown. In this embodiment, the individual optical fibers 1803 are arranged in a staggered layout, where an optical fiber 1803 in the first row 1811 is adjacent to and possibly between corresponding optical fibers 1803 in the second row 1813. Additionally, the centers of the optical fibers 1803 within the first row 1811 are offset relative to the centers of the optical fibers 1803 within the second row 1813. However, any suitable arrangement may be utilized.

[0147] By utilizing the first level active layer 1105 above the second active layer 801, more optical fibers 1803 can be connected. This allows a higher bandwidth to enter and leave the second active layer 801 by increasing the number of optical fibers 1803. Therefore, the coupling loss from the optical fibers 1803 to the second active layer 801 can be reduced, and a more efficient device can be formed.

[0148] In an embodiment, a method for manufacturing an optical device includes: receiving a multi-level connection unit, the multi-level connection unit including: a first level, including a first reflector having a first orientation; a second level, including a second reflector having a second orientation that is the same as the first orientation; and a third level, including a third reflector, the third reflector having a third orientation that is different from the first orientation; and attaching the multi-level connection unit to a first optical package. In an embodiment, the third level also includes a fan-in waveguide. In an embodiment, the second reflector includes multiple, separated portions. In an embodiment, the first reflector is a single unit. In an embodiment, the multi-level connection unit has a constant width. In an embodiment, the first reflector is located within a semiconductor substrate. In an embodiment, the first level also includes a waveguide aligned with the first reflector.

[0149] In another embodiment, a method for manufacturing an optical device includes: attaching an electrical integrated circuit to an optical interposer; and bonding a first-level active layer over the electrical integrated circuit and the optical interposer, the first-level active layer including: a first optical component; and a first reflector aligned with the first optical component. In an embodiment, after bonding, the first reflector is aligned with a second reflector located on a side of the electrical integrated circuit opposite to the first reflector, the second reflector being located in the first active layer of the second optical component. In an embodiment, the method also includes attaching a multi-level connection unit to the optical interposer. In an embodiment, the multi-level connection unit includes: a first optical fiber aligned with the first reflector; and a second optical fiber aligned with the second optical component. In an embodiment, the first center of the first optical fiber is located directly above the second center of the second optical fiber. In an embodiment, the first optical fiber is staggered with the second optical fiber. In an embodiment, the spacing between the first optical fiber and the second optical fiber is about 108 μm.

[0150] In yet another embodiment, the optical device includes: a multi-level connection unit, the multi-level connection unit including: a first level including a first reflector; a second level including a second reflector, a first lens, and a second lens; and a third level including a third reflector and a third lens; and a first optical package attached to the multi-level connection unit. In an embodiment, the first lens and the second lens are adjacent to the second reflector. In an embodiment, the first lens and the second lens are offset relative to the second reflector. In an embodiment, the third level includes a fourth reflector aligned with the first lens and the second lens. In an embodiment, the optical device also includes a plurality of rows of connectors attached to the multi-level connection unit, wherein a first row of optical fibers is aligned with the first reflector, and wherein a second row of optical fibers is aligned with the second reflector. In an embodiment, the first level also includes a first optical component adjacent to the first reflector.

[0151] Some embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: receiving a multi-level connection unit, the multi-level connection unit comprising: a first level, including a first reflector having a first orientation; a second level, including a second reflector having a second orientation the same as the first orientation; and a third level, including a third reflector, the third reflector having a third orientation different from the first orientation; and attaching the multi-level connection unit to a first optical package, the first optical package comprising a semiconductor die.

[0152] In some embodiments, the third level further comprises a fan-in waveguide. In some embodiments, the second reflector comprises multiple, separated portions. In some embodiments, the first reflector is a single unit. In some embodiments, the multi-level connection unit has a constant width. In some embodiments, the first reflector is located within the semiconductor substrate. In some embodiments, the first level further comprises a waveguide aligned with the first reflector.

[0153] Other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: attaching an electrical integrated circuit to an optical interposer; and bonding a first-level active layer above the electrical integrated circuit and the optical interposer, the first-level active layer comprising: a first optical component; and a first reflector aligned with the first optical component.

[0154] In some embodiments, after the joining, the first reflector is aligned with a second reflector located on a side of the integrated circuit opposite to the first reflector, and the second reflector is located in a first active layer of a second optical component. In some embodiments, the method also includes attaching a multi-level connection unit to the optical interposer. In some embodiments, the multi-level connection unit includes: a first optical fiber aligned with the first reflector; and a second optical fiber aligned with the second optical component. In some embodiments, the first center of the first optical fiber is directly above the second center of the second optical fiber. In some embodiments, the first optical fiber is staggered with the second optical fiber. In some embodiments, the spacing between the first optical fiber and the second optical fiber is about 108μm.

[0155] Some other embodiments of the present application provide a semiconductor device, comprising: a multi-level connection unit, the multi-level connection unit comprising: a first level, including a first reflector; a second level, including a second reflector, a first lens and a second lens; and a third level, including a third reflector and a third lens; and a first optical package attached to the multi-level connection unit, the first optical package comprising a semiconductor die.

[0156] In some embodiments, the first lens and the second lens are adjacent to the second reflector. In some embodiments, the first lens and the second lens are offset relative to the second reflector. In some embodiments, the third level includes a fourth reflector aligned with the first lens and the second lens. In some embodiments, the semiconductor device also includes a plurality of rows of connectors attached to the multi-level connection unit, wherein a first row of optical fibers is aligned with the first reflector, and wherein a second row of optical fibers is aligned with the second reflector. In some embodiments, the first level also includes a first optical component adjacent to the first reflector.

[0157] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A multi-level connection unit is received, wherein the multi-level connection unit comprises: a first level including a first reflector having a first orientation; a second level including a second reflector having a second orientation that is the same as the first orientation; and a third level including a third reflector having a third orientation different from the first orientation; and The multi-level connection unit is attached to a first optical package, the first optical package including a semiconductor die.

2. The method according to claim 1, wherein: The third level also includes a fan-in waveguide.

3. The method according to claim 1, wherein: The second reflector includes multiple, separate sections.

4. The method according to claim 1, wherein: The first reflector is a single unit.

5. The method according to claim 1, wherein: The multi-level connection unit has a constant width.

6. The method according to claim 1, wherein: The first reflector is located in the semiconductor substrate.

7. The method according to claim 1, wherein: The first level also includes a waveguide aligned with the first reflector.

8. A method for manufacturing a semiconductor device, the method comprising: attaching the electrical integrated circuit to the optical interposer; as well as Bonding a first level active layer over the electrical integrated circuit and the optical interposer, the first level active layer comprising: a first optical component; as well as A first reflector is aligned with the first optical component.

9. The method according to claim 8, wherein: After said bonding, the first mirror is aligned with a second mirror located on an opposite side of the electrical integrated circuit from the first mirror, the second mirror being located in a first active layer of a second optical component.

10. A semiconductor device comprising: A multi-level connection unit, the multi-level connection unit comprising: The first level includes a first reflector; a second stage including a second reflector, a first lens, and a second lens; and a third stage, including a third reflector and a third lens; and A first optical package is attached to the multi-level connection unit, the first optical package including a semiconductor die.

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